From 068d9bf2cfa9110ae44008da45bfd0419cb45b52 Mon Sep 17 00:00:00 2001
From: Angus Gratton <angus@redyak.com.au>
Date: Tue, 25 Jun 2024 16:20:59 +1000
Subject: [PATCH] rp2: Fix USB PLL glitch during wake from light sleep.

Follow-up to a84c7a0ed93, this commit works most of the time but has an
intermittent bug where USB doesn't resume as expected after waking from
light sleep.

Turns out waking calls clocks_init() which will re-initialise the USB PLL.
Most of the time this is OK but occasionally it seems like the clock
glitches the USB peripheral and it stops working until the next hard reset.

Adds a machine.lightsleep() test that consistently hangs in the first
two dozen iterations on rp2 without this fix. Passed over 100 times in a
row with this fix.

The test is currently rp2-only as it seems similar lightsleep USB issues
exist on other ports (both pyboard and ESP32-S3 native USB don't send any
data to the host after waking, until they receive something from the host
first.)

This work was funded through GitHub Sponsors.

Signed-off-by: Angus Gratton <angus@redyak.com.au>
---
 ports/rp2/modmachine.c                |  4 ++--
 tests/ports/rp2/rp2_lightsleep.py     | 31 +++++++++++++++++++++++++++
 tests/ports/rp2/rp2_lightsleep.py.exp |  2 ++
 3 files changed, 35 insertions(+), 2 deletions(-)
 create mode 100644 tests/ports/rp2/rp2_lightsleep.py
 create mode 100644 tests/ports/rp2/rp2_lightsleep.py.exp

diff --git a/ports/rp2/modmachine.c b/ports/rp2/modmachine.c
index 4eebb3d16..9cc15080c 100644
--- a/ports/rp2/modmachine.c
+++ b/ports/rp2/modmachine.c
@@ -31,7 +31,7 @@
 #include "mp_usbd.h"
 #include "modmachine.h"
 #include "uart.h"
-#include "hardware/clocks.h"
+#include "clocks_extra.h"
 #include "hardware/pll.h"
 #include "hardware/structs/rosc.h"
 #include "hardware/structs/scb.h"
@@ -213,7 +213,7 @@ static void mp_machine_lightsleep(size_t n_args, const mp_obj_t *args) {
     rosc_hw->ctrl = ROSC_CTRL_ENABLE_VALUE_ENABLE << ROSC_CTRL_ENABLE_LSB;
 
     // Bring back all clocks.
-    clocks_init();
+    clocks_init_optional_usb(disable_usb);
     MICROPY_END_ATOMIC_SECTION(my_interrupts);
 }
 
diff --git a/tests/ports/rp2/rp2_lightsleep.py b/tests/ports/rp2/rp2_lightsleep.py
new file mode 100644
index 000000000..3587def68
--- /dev/null
+++ b/tests/ports/rp2/rp2_lightsleep.py
@@ -0,0 +1,31 @@
+# This test is mostly intended for ensuring USB serial stays stable over
+# lightsleep, but can double as a general lightsleep test.
+#
+# In theory this should run on any port, but native USB REPL doesn't currently
+# recover automatically on all ports. On pyboard and ESP32-S3 the host needs to
+# send something to the port before it responds again. Possibly the same for other
+# ports with native USB.
+#
+# A range of sleep periods (1 to 512ms) are tested. The total nominal sleep time
+# is 10.23 seconds, but on most ports this will finish much earlier as interrupts
+# happen before each timeout expires.
+try:
+    from machine import lightsleep, Pin
+except ImportError:
+    print("SKIP")
+    raise SystemExit
+
+from sys import stdout, platform
+
+try:
+    led = Pin(Pin.board.LED, Pin.OUT)
+except AttributeError:
+    led = None
+
+for n in range(100):
+    if led:
+        led.toggle()
+    stdout.write(chr(ord("a") + (n % 26)))
+    lightsleep(2 ** (n % 10))
+
+print("\nDONE")
diff --git a/tests/ports/rp2/rp2_lightsleep.py.exp b/tests/ports/rp2/rp2_lightsleep.py.exp
new file mode 100644
index 000000000..81d1c231c
--- /dev/null
+++ b/tests/ports/rp2/rp2_lightsleep.py.exp
@@ -0,0 +1,2 @@
+abcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuv
+DONE