shared/runtime/gchelper: Drop cpu directive from ARM asm helpers.

This drops the `.cpu` directive from the ARM gchelper_*.s files.  Having
this directive breaks the linker when targeting older CPUs (e.g. `-mthumb
-mthumb-interwork` for `-mcpu=arm7tdmi`).  The actual target CPU should be
determined by the compiler options.

The exact CPU doesn't actually matter, but rather the supported assembly
instruction set.  So the files are renamed to *_thumb1.s and *thumb2.s to
indicate the instruction set support instead of the CPU support.

Signed-off-by: David Lechner <david@pybricks.com>

shared/runtime/gchelper_generic.c

@@ -98,7 +98,7 @@ STATIC void gc_helper_get_regs(gc_helper_regs_t arr) {
 
 #elif defined(__thumb2__) || defined(__thumb__) || defined(__arm__)
 
-// Fallback implementation, prefer gchelper_m0.s or gchelper_m3.s
+// Fallback implementation, prefer gchelper_thumb1.s or gchelper_thumb2.s
 
 STATIC void gc_helper_get_regs(gc_helper_regs_t arr) {
     register long r4 asm ("r4");

shared/runtime/gchelper_thumb1.s

@@ -25,7 +25,6 @@
  */
 
     .syntax unified
-    .cpu cortex-m0
     .thumb
 
     .section .text
@@ -34,6 +33,9 @@
     .global gc_helper_get_regs_and_sp
     .type gc_helper_get_regs_and_sp, %function
 
+@ This function will compile on processors like Cortex M0 that don't support
+@ newer Thumb-2 instructions.
+
 @ uint gc_helper_get_regs_and_sp(r0=uint regs[10])
 gc_helper_get_regs_and_sp:
     @ store registers into given array

shared/runtime/gchelper_thumb2.s

@@ -25,7 +25,6 @@
  */
 
     .syntax unified
-    .cpu cortex-m3
     .thumb
 
     .section .text
@@ -34,6 +33,8 @@
     .global gc_helper_get_regs_and_sp
     .type gc_helper_get_regs_and_sp, %function
 
+@ This function requires Thumb-2 instruction support, e.g. Cortex M3/M4.
+
 @ uint gc_helper_get_regs_and_sp(r0=uint regs[10])
 gc_helper_get_regs_and_sp:
     @ store registers into given array