TonBERRY/micropython
3
0
Fork 0
Code Pull Requests Activity

stm32/system_stm32: Allow boards to configure PLL VCI, VCO and FRACN.

Browse Source 
This removes hard-coded PLL1/3 VCI, VCO and FRACN.
This commit is contained in:
iabdalkader
2022-04-08 09:41:19 +02:00
committed by Damien George
parent a3e5a68c46
commit 36cac5e154
4 changed files with 46 additions and 26 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
ports/stm32/system_stm32.c
View File

@@ -351,9 +351,9 @@ MP_WEAK void SystemClock_Config(void) {
#endif
#if defined(STM32H7)
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_1;
RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
RCC_OscInitStruct.PLL.PLLFRACN = 0;
RCC_OscInitStruct.PLL.PLLRGE = MICROPY_HW_CLK_PLLVCI;
RCC_OscInitStruct.PLL.PLLVCOSEL = MICROPY_HW_CLK_PLLVCO;
RCC_OscInitStruct.PLL.PLLFRACN = MICROPY_HW_CLK_PLLFRAC;
#endif
#if defined(STM32F4) || defined(STM32F7)
@@ -392,9 +392,9 @@ MP_WEAK void SystemClock_Config(void) {
PeriphClkInitStruct.PLL3.PLL3P = MICROPY_HW_CLK_PLL3P;
PeriphClkInitStruct.PLL3.PLL3Q = MICROPY_HW_CLK_PLL3Q;
PeriphClkInitStruct.PLL3.PLL3R = MICROPY_HW_CLK_PLL3R;
PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3VCIRANGE_1;
PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3VCOWIDE;
PeriphClkInitStruct.PLL3.PLL3FRACN = 0;
PeriphClkInitStruct.PLL3.PLL3RGE = MICROPY_HW_CLK_PLL3VCI;
PeriphClkInitStruct.PLL3.PLL3VCOSEL = MICROPY_HW_CLK_PLL3VCO;
PeriphClkInitStruct.PLL3.PLL3FRACN = MICROPY_HW_CLK_PLL3FRAC;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
__fatal_error("HAL_RCCEx_PeriphCLKConfig");
}