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alif/mpu: Define constants for MPU regions.

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Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
This commit is contained in:
iabdalkader
2024-11-21 07:55:10 +01:00
committed by Damien George
parent 41e16886b1
commit 3d17f63478
2 changed files with 29 additions and 22 deletions
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34
ports/alif/mpu.c
View File

@@ -29,48 +29,48 @@
#include ALIF_CMSIS_H #include ALIF_CMSIS_H
static const ARM_MPU_Region_t mpu_table[] __STARTUP_RO_DATA_ATTRIBUTE = { static const ARM_MPU_Region_t mpu_table[] __STARTUP_RO_DATA_ATTRIBUTE = {
{ /* SRAM0 - 4MB : RO-0, NP-1, XN-0 */ [MP_MPU_REGION_SRAM0] = { /* SRAM0 - 4MB : RO-0, NP-1, XN-0 */
.RBAR = ARM_MPU_RBAR(0x02000000, ARM_MPU_SH_NON, 0, 1, 0), .RBAR = ARM_MPU_RBAR(0x02000000, ARM_MPU_SH_NON, 0, 1, 0),
.RLAR = ARM_MPU_RLAR(0x023FFFFF, MP_MPU_ATTR_INDEX_NORMAL_WT_RA_TRANSIENT) .RLAR = ARM_MPU_RLAR(0x023FFFFF, MP_MPU_ATTR_NORMAL_WT_RA_TRANSIENT)
}, },
{ /* SRAM1 - 2.5MB : RO-0, NP-1, XN-0 */ [MP_MPU_REGION_SRAM1] = { /* SRAM1 - 2.5MB : RO-0, NP-1, XN-0 */
.RBAR = ARM_MPU_RBAR(0x08000000, ARM_MPU_SH_NON, 0, 1, 0), .RBAR = ARM_MPU_RBAR(0x08000000, ARM_MPU_SH_NON, 0, 1, 0),
.RLAR = ARM_MPU_RLAR(0x0827FFFF, MP_MPU_ATTR_INDEX_NORMAL_WB_RA_WA) .RLAR = ARM_MPU_RLAR(0x0827FFFF, MP_MPU_ATTR_NORMAL_WB_RA_WA)
}, },
{ /* Host Peripherals - 16MB : RO-0, NP-1, XN-1 */ [MP_MPU_REGION_HOST_PERIPHERALS] = { /* Host Peripherals - 16MB : RO-0, NP-1, XN-1 */
.RBAR = ARM_MPU_RBAR(0x1A000000, ARM_MPU_SH_NON, 0, 1, 1), .RBAR = ARM_MPU_RBAR(0x1A000000, ARM_MPU_SH_NON, 0, 1, 1),
.RLAR = ARM_MPU_RLAR(0x1AFFFFFF, MP_MPU_ATTR_INDEX_DEVICE_nGnRE) .RLAR = ARM_MPU_RLAR(0x1AFFFFFF, MP_MPU_ATTR_DEVICE_nGnRE)
}, },
{ /* MRAM - 5.5MB : RO-1, NP-1, XN-0 */ [MP_MPU_REGION_MRAM] = { /* MRAM - 5.5MB : RO-1, NP-1, XN-0 */
.RBAR = ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_NON, 1, 1, 0), .RBAR = ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_NON, 1, 1, 0),
.RLAR = ARM_MPU_RLAR(0x8057FFFF, MP_MPU_ATTR_INDEX_NORMAL_WT_RA) .RLAR = ARM_MPU_RLAR(0x8057FFFF, MP_MPU_ATTR_NORMAL_WT_RA)
}, },
{ /* OSPI Regs - 16MB : RO-0, NP-1, XN-1 */ [MP_MPU_REGION_OSPI_REGISTERS] = { /* OSPI Regs - 16MB : RO-0, NP-1, XN-1 */
.RBAR = ARM_MPU_RBAR(0x83000000, ARM_MPU_SH_NON, 0, 1, 1), .RBAR = ARM_MPU_RBAR(0x83000000, ARM_MPU_SH_NON, 0, 1, 1),
.RLAR = ARM_MPU_RLAR(0x83FFFFFF, MP_MPU_ATTR_INDEX_DEVICE_nGnRE) .RLAR = ARM_MPU_RLAR(0x83FFFFFF, MP_MPU_ATTR_DEVICE_nGnRE)
}, },
{ /* OSPI0 XIP flash - 512MB : RO-1, NP-1, XN-0 */ [MP_MPU_REGION_OSPI0_XIP] = { /* OSPI0 XIP flash - 512MB : RO-1, NP-1, XN-0 */
.RBAR = ARM_MPU_RBAR(0xA0000000, ARM_MPU_SH_NON, 1, 1, 0), .RBAR = ARM_MPU_RBAR(0xA0000000, ARM_MPU_SH_NON, 1, 1, 0),
.RLAR = ARM_MPU_RLAR(0xBFFFFFFF, MP_MPU_ATTR_INDEX_NORMAL_NON_CACHEABLE) .RLAR = ARM_MPU_RLAR(0xBFFFFFFF, MP_MPU_ATTR_NORMAL_NON_CACHEABLE)
}, },
}; };
void MPU_Load_Regions(void) { void MPU_Load_Regions(void) {
// Configure memory attributes. // Configure memory attributes.
ARM_MPU_SetMemAttr(MP_MPU_ATTR_INDEX_NORMAL_WT_RA_TRANSIENT, ARM_MPU_SetMemAttr(MP_MPU_ATTR_NORMAL_WT_RA_TRANSIENT,
ARM_MPU_ATTR(ARM_MPU_ATTR_MEMORY_(0, 0, 1, 0), ARM_MPU_ATTR_MEMORY_(0, 0, 1, 0))); ARM_MPU_ATTR(ARM_MPU_ATTR_MEMORY_(0, 0, 1, 0), ARM_MPU_ATTR_MEMORY_(0, 0, 1, 0)));
ARM_MPU_SetMemAttr(MP_MPU_ATTR_INDEX_DEVICE_nGnRE, ARM_MPU_SetMemAttr(MP_MPU_ATTR_DEVICE_nGnRE,
ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE, ARM_MPU_ATTR_DEVICE_nGnRE)); ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE, ARM_MPU_ATTR_DEVICE_nGnRE));
ARM_MPU_SetMemAttr(MP_MPU_ATTR_INDEX_NORMAL_WB_RA_WA, ARM_MPU_SetMemAttr(MP_MPU_ATTR_NORMAL_WB_RA_WA,
ARM_MPU_ATTR(ARM_MPU_ATTR_MEMORY_(1, 1, 1, 1), ARM_MPU_ATTR_MEMORY_(1, 1, 1, 1))); ARM_MPU_ATTR(ARM_MPU_ATTR_MEMORY_(1, 1, 1, 1), ARM_MPU_ATTR_MEMORY_(1, 1, 1, 1)));
ARM_MPU_SetMemAttr(MP_MPU_ATTR_INDEX_NORMAL_WT_RA, ARM_MPU_SetMemAttr(MP_MPU_ATTR_NORMAL_WT_RA,
ARM_MPU_ATTR(ARM_MPU_ATTR_MEMORY_(1, 0, 1, 0), ARM_MPU_ATTR_MEMORY_(1, 0, 1, 0))); ARM_MPU_ATTR(ARM_MPU_ATTR_MEMORY_(1, 0, 1, 0), ARM_MPU_ATTR_MEMORY_(1, 0, 1, 0)));
ARM_MPU_SetMemAttr(MP_MPU_ATTR_INDEX_NORMAL_NON_CACHEABLE, ARM_MPU_SetMemAttr(MP_MPU_ATTR_NORMAL_NON_CACHEABLE,
ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE)); ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE));
// Load the MPU regions from the table. // Load the MPU regions from the table.

17
ports/alif/mpu.h
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@@ -24,8 +24,15 @@
* THE SOFTWARE. * THE SOFTWARE.
*/ */
#define MP_MPU_ATTR_INDEX_NORMAL_WT_RA_TRANSIENT (0) #define MP_MPU_ATTR_NORMAL_WT_RA_TRANSIENT (0)
#define MP_MPU_ATTR_INDEX_DEVICE_nGnRE (1) #define MP_MPU_ATTR_DEVICE_nGnRE (1)
#define MP_MPU_ATTR_INDEX_NORMAL_WB_RA_WA (2) #define MP_MPU_ATTR_NORMAL_WB_RA_WA (2)
#define MP_MPU_ATTR_INDEX_NORMAL_WT_RA (3) #define MP_MPU_ATTR_NORMAL_WT_RA (3)
#define MP_MPU_ATTR_INDEX_NORMAL_NON_CACHEABLE (4) #define MP_MPU_ATTR_NORMAL_NON_CACHEABLE (4)
#define MP_MPU_REGION_SRAM0 (0)
#define MP_MPU_REGION_SRAM1 (1)
#define MP_MPU_REGION_HOST_PERIPHERALS (2)
#define MP_MPU_REGION_MRAM (3)
#define MP_MPU_REGION_OSPI_REGISTERS (4)
#define MP_MPU_REGION_OSPI0_XIP (5)