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stm32: Add support for G4 MCUs, and add NUCLEO_G474RE board defn.

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This commit adds support for the STM32G4 series of MCUs, and a board
definition for NUCLEO_G474RE.  This board has the REPL on LPUART1 which is
connected to the on-board ST-link USB-UART.
This commit is contained in:
Herwin Grobben
2021-01-26 14:49:56 +01:00
committed by Damien George
parent 60e05ae84e
commit 8f68e26f79
32 changed files with 1050 additions and 91 deletions
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62
ports/stm32/system_stm32.c
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@@ -78,7 +78,7 @@
#include "py/mphal.h"
#include "powerctrl.h"
#if defined(STM32F4) || defined(STM32F7) || defined(STM32H7) || defined(STM32L4)
#if defined(STM32F4) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32L4)
void __fatal_error(const char *msg);
@@ -171,10 +171,10 @@ void SystemClock_Config(void) {
RCC->DCKCFGR2 = 0;
#endif
RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_OscInitTypeDef RCC_OscInitStruct;
#if defined(STM32H7)
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
#if defined(STM32G4) || defined(STM32H7)
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
#endif
#if defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
@@ -192,6 +192,10 @@ void SystemClock_Config(void) {
clocked below the maximum system frequency, to update the voltage scaling value
regarding system frequency refer to product datasheet. */
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
#elif defined(STM32G4)
// Configure the main internal regulator output voltage
HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST);
#elif defined(STM32L4)
// Configure LSE Drive Capability
__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
@@ -204,7 +208,7 @@ void SystemClock_Config(void) {
#endif
/* Enable HSE Oscillator and activate PLL with HSE as source */
#if defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
#if defined(STM32F4) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7)
RCC_OscInitStruct.OscillatorType = MICROPY_HW_RCC_OSCILLATOR_TYPE;
RCC_OscInitStruct.HSEState = MICROPY_HW_RCC_HSE_STATE;
RCC_OscInitStruct.HSIState = MICROPY_HW_RCC_HSI_STATE;
@@ -240,6 +244,27 @@ void SystemClock_Config(void) {
#endif
#endif
#if defined(STM32G4)
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
#if MICROPY_HW_CLK_USE_HSI && MICROPY_HW_CLK_USE_HSI48
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
#else
RCC_OscInitStruct.OscillatorType = MICROPY_HW_RCC_OSCILLATOR_TYPE;
RCC_OscInitStruct.HSEState = MICROPY_HW_RCC_HSE_STATE;
RCC_OscInitStruct.HSIState = MICROPY_HW_RCC_HSI_STATE;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
#endif
RCC_OscInitStruct.PLL.PLLM = MICROPY_HW_CLK_PLLM;
RCC_OscInitStruct.PLL.PLLN = MICROPY_HW_CLK_PLLN;
RCC_OscInitStruct.PLL.PLLP = MICROPY_HW_CLK_PLLP;
RCC_OscInitStruct.PLL.PLLQ = MICROPY_HW_CLK_PLLQ;
RCC_OscInitStruct.PLL.PLLR = MICROPY_HW_CLK_PLLR;
#endif
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
clocks dividers */
@@ -295,7 +320,7 @@ void SystemClock_Config(void) {
RCC_OscInitStruct.PLL.PLLN = MICROPY_HW_CLK_PLLN;
RCC_OscInitStruct.PLL.PLLP = MICROPY_HW_CLK_PLLP;
RCC_OscInitStruct.PLL.PLLQ = MICROPY_HW_CLK_PLLQ;
#if defined(STM32L4) || defined(STM32H7)
#if defined(STM32G4) || defined(STM32H7) || defined(STM32L4)
RCC_OscInitStruct.PLL.PLLR = MICROPY_HW_CLK_PLLR;
#endif
@@ -309,6 +334,11 @@ void SystemClock_Config(void) {
RCC_ClkInitStruct.AHBCLKDivider = MICROPY_HW_CLK_AHB_DIV;
RCC_ClkInitStruct.APB1CLKDivider = MICROPY_HW_CLK_APB1_DIV;
RCC_ClkInitStruct.APB2CLKDivider = MICROPY_HW_CLK_APB2_DIV;
#elif defined(STM32G4)
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = MICROPY_HW_CLK_AHB_DIV;
RCC_ClkInitStruct.APB1CLKDivider = MICROPY_HW_CLK_APB1_DIV;
RCC_ClkInitStruct.APB2CLKDivider = MICROPY_HW_CLK_APB2_DIV;
#elif defined(STM32L4)
RCC_ClkInitStruct.AHBCLKDivider = MICROPY_HW_CLK_AHB_DIV;
RCC_ClkInitStruct.APB1CLKDivider = MICROPY_HW_CLK_APB1_DIV;
@@ -351,12 +381,30 @@ void SystemClock_Config(void) {
}
#endif
#if defined(STM32G4)
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_8) != HAL_OK) {
__fatal_error("HAL_RCC_ClockConfig");
}
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_LPUART1
| RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC12
| RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_USB;
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1;
PeriphClkInitStruct.FdcanClockSelection = RCC_FDCANCLKSOURCE_HSE;
PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_HSI48;
PeriphClkInitStruct.Adc12ClockSelection = RCC_ADC12CLKSOURCE_SYSCLK;
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
__fatal_error("HAL_RCCEx_PeriphCLKConfig");
}
#else
uint32_t vco_out = RCC_OscInitStruct.PLL.PLLN * (MICROPY_HW_CLK_VALUE / 1000000) / RCC_OscInitStruct.PLL.PLLM;
uint32_t sysclk_mhz = vco_out / RCC_OscInitStruct.PLL.PLLP;
bool need_pll48 = vco_out % 48 != 0;
if (powerctrl_rcc_clock_config_pll(&RCC_ClkInitStruct, sysclk_mhz, need_pll48) != 0) {
__fatal_error("HAL_RCC_ClockConfig");
}
#endif
#if defined(STM32H7)
/* Activate CSI clock mandatory for I/O Compensation Cell*/