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rp2/rp2_flash: Add MICROPY_HW_FLASH_MAX_FREQ to replace fixed max freq.

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Assuming a 133MHz capable flash in 91cff8e4f1
caused `rp2_flash_set_timing_internal` to set out of range dividers for
some boards (anything with value of 4 and flash that doesn't tolerate
higher speeds).

This affected (at least) the XIAO RP2350 board, making it non-bootable.

Since Pico SDK's `PICO_FLASH_SPI_CLKDIV` is entirely unreliable on a system
with a variable system clock (users can change it at runtime) then use it
only to work out a default `MICROPY_HW_FLASH_MAX_FREQ`.

This value can be overridden in board config.

Note that RP2350's default clock is 150MHz, RP2040's is 125MHz and it has
been certified at 200MHz so it's quite possible that
`PICO_FLASH_SPI_CLKDIV` is unreliable even at standard RP2 clocks.

(If flash timings are marginal then this can manifest as instability rather
than outright failure.)

Fixes issue #17375.

Signed-off-by: Phil Howard <github@gadgetoid.com>
This commit is contained in:
Phil Howard
2025-05-29 13:46:05 +01:00
committed by Damien George
parent c1196cadb1
commit b725c26b4e
1 changed files with 10 additions and 3 deletions
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13
ports/rp2/rp2_flash.c
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@@ -49,6 +49,14 @@
static_assert(MICROPY_HW_ROMFS_BYTES % 4096 == 0, "ROMFS size must be a multiple of 4K"); static_assert(MICROPY_HW_ROMFS_BYTES % 4096 == 0, "ROMFS size must be a multiple of 4K");
static_assert(MICROPY_HW_FLASH_STORAGE_BYTES % 4096 == 0, "Flash storage size must be a multiple of 4K"); static_assert(MICROPY_HW_FLASH_STORAGE_BYTES % 4096 == 0, "Flash storage size must be a multiple of 4K");
#ifndef MICROPY_HW_FLASH_MAX_FREQ
// Emulate Pico SDK's SYS_CLK_HZ / PICO_FLASH_SPI_CLKDIV behaviour by default.
// On RP2040 if PICO_USE_FASTEST_SUPPORTED_CLOCK is set then SYS_CLK_HZ can be
// 200MHz, potentially putting timings derived from PICO_FLASH_SPI_CLKDIV
// out of range.
#define MICROPY_HW_FLASH_MAX_FREQ (SYS_CLK_HZ / PICO_FLASH_SPI_CLKDIV)
#endif
#ifndef MICROPY_HW_FLASH_STORAGE_BASE #ifndef MICROPY_HW_FLASH_STORAGE_BASE
#define MICROPY_HW_FLASH_STORAGE_BASE (PICO_FLASH_SIZE_BYTES - MICROPY_HW_FLASH_STORAGE_BYTES) #define MICROPY_HW_FLASH_STORAGE_BASE (PICO_FLASH_SIZE_BYTES - MICROPY_HW_FLASH_STORAGE_BYTES)
#endif #endif
@@ -104,9 +112,8 @@ static bool use_multicore_lockout(void) {
// and core1 locked out if relevant. // and core1 locked out if relevant.
static void __no_inline_not_in_flash_func(rp2_flash_set_timing_internal)(int clock_hz) { static void __no_inline_not_in_flash_func(rp2_flash_set_timing_internal)(int clock_hz) {
// Use the minimum divisor assuming a 133MHz flash. // Use the minimum divisor based upon our target MICROPY_HW_FLASH_MAX_FREQ
const int max_flash_freq = 133000000; int divisor = (clock_hz + MICROPY_HW_FLASH_MAX_FREQ - 1) / MICROPY_HW_FLASH_MAX_FREQ;
int divisor = (clock_hz + max_flash_freq - 1) / max_flash_freq;
#if PICO_RP2350 #if PICO_RP2350
// Make sure flash is deselected - QMI doesn't appear to have a busy flag(!) // Make sure flash is deselected - QMI doesn't appear to have a busy flag(!)