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stm32/boards/stm32f4x9_af.csv: Fix DCMI_VSYNC.

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This incorrectly had a `(1)` on the end.

Signed-off-by: Jim Mussared <jim.mussared@gmail.com>
This commit is contained in:
Jim Mussared
2023-11-04 09:00:33 +11:00
parent 841422817e
commit c028f956fc
2 changed files with 340 additions and 340 deletions
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2
ports/stm32/boards/stm32f429_af.csv
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@@ -105,7 +105,7 @@ PortG,PG5 , , , , , ,
PortG,PG6 , , , , , , , , , , , , ,FMC_INT2 ,DCMI_D12 ,LCD_R7 ,EVENTOUT,
PortG,PG7 , , , , , , , , ,USART6_CK , , , ,FMC_INT3 ,DCMI_D13 ,LCD_CLK ,EVENTOUT,
PortG,PG8 , , , , , ,SPI6_NSS , , ,USART6_RTS , , ,ETH_PPS_OUT ,FMC_SDCLK , , ,EVENTOUT,
PortG,PG9 , , , , , , , , ,USART6_RX , , , ,FMC_NE2/FMC_NCE3 ,DCMI_VSYNC(1), ,EVENTOUT,
PortG,PG9 , , , , , , , , ,USART6_RX , , , ,FMC_NE2/FMC_NCE3 ,DCMI_VSYNC , ,EVENTOUT,
PortG,PG10, , , , , , , , , ,LCD_G3 , , ,FMC_NCE4_1/FMC_NE3,DCMI_D2 ,LCD_B2 ,EVENTOUT,
PortG,PG11, , , , , , , , , , , ,ETH_MII_TX_EN/ETH_RMII_TX_EN ,FMC_NCE4_2 ,DCMI_D3 ,LCD_B3 ,EVENTOUT,
PortG,PG12, , , , , ,SPI6_MISO , , ,USART6_RTS ,LCD_B4 , , ,FMC_NE4 , ,LCD_B1 ,EVENTOUT,
1 Port Pin AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF13 AF14 AF15 ADC
105 PortG PG6 FMC_INT2 DCMI_D12 DCMI_D12 LCD_R7 EVENTOUT
106 PortG PG7 USART6_CK FMC_INT3 DCMI_D13 DCMI_D13 LCD_CLK EVENTOUT
107 PortG PG8 SPI6_NSS USART6_RTS ETH_PPS_OUT FMC_SDCLK EVENTOUT
108 PortG PG9 USART6_RX FMC_NE2/FMC_NCE3 DCMI_VSYNC(1) DCMI_VSYNC EVENTOUT
109 PortG PG10 LCD_G3 FMC_NCE4_1/FMC_NE3 DCMI_D2 DCMI_D2 LCD_B2 EVENTOUT
110 PortG PG11 ETH_MII_TX_EN/ETH_RMII_TX_EN FMC_NCE4_2 DCMI_D3 DCMI_D3 LCD_B3 EVENTOUT
111 PortG PG12 SPI6_MISO USART6_RTS LCD_B4 FMC_NE4 LCD_B1 EVENTOUT

2
ports/stm32/boards/stm32f439_af.csv
View File

@@ -105,7 +105,7 @@ PortG,PG5 , , , , , ,
PortG,PG6 , , , , , , , , , , , , ,FMC_INT2 ,DCMI_D12 ,LCD_R7 ,EVENTOUT,
PortG,PG7 , , , , , , , , ,USART6_CK , , , ,FMC_INT3 ,DCMI_D13 ,LCD_CLK ,EVENTOUT,
PortG,PG8 , , , , , ,SPI6_NSS , , ,USART6_RTS , , ,ETH_PPS_OUT ,FMC_SDCLK , , ,EVENTOUT,
PortG,PG9 , , , , , , , , ,USART6_RX , , , ,FMC_NE2/FMC_NCE3 ,DCMI_VSYNC(1), ,EVENTOUT,
PortG,PG9 , , , , , , , , ,USART6_RX , , , ,FMC_NE2/FMC_NCE3 ,DCMI_VSYNC , ,EVENTOUT,
PortG,PG10, , , , , , , , , ,LCD_G3 , , ,FMC_NCE4_1/FMC_NE3,DCMI_D2 ,LCD_B2 ,EVENTOUT,
PortG,PG11, , , , , , , , , , , ,ETH_MII_TX_EN/ETH_RMII_TX_EN ,FMC_NCE4_2 ,DCMI_D3 ,LCD_B3 ,EVENTOUT,
PortG,PG12, , , , , ,SPI6_MISO , , ,USART6_RTS ,LCD_B4 , , ,FMC_NE4 , ,LCD_B1 ,EVENTOUT,
1 Port Pin AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF13 AF14 AF15 ADC
105 PortG PG6 FMC_INT2 DCMI_D12 DCMI_D12 LCD_R7 EVENTOUT
106 PortG PG7 USART6_CK FMC_INT3 DCMI_D13 DCMI_D13 LCD_CLK EVENTOUT
107 PortG PG8 SPI6_NSS USART6_RTS ETH_PPS_OUT FMC_SDCLK EVENTOUT
108 PortG PG9 USART6_RX FMC_NE2/FMC_NCE3 DCMI_VSYNC(1) DCMI_VSYNC EVENTOUT
109 PortG PG10 LCD_G3 FMC_NCE4_1/FMC_NE3 DCMI_D2 DCMI_D2 LCD_B2 EVENTOUT
110 PortG PG11 ETH_MII_TX_EN/ETH_RMII_TX_EN FMC_NCE4_2 DCMI_D3 DCMI_D3 LCD_B3 EVENTOUT
111 PortG PG12 SPI6_MISO USART6_RTS LCD_B4 FMC_NE4 LCD_B1 EVENTOUT