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rp2/modmachine: Do not use deprecated XOSC_MHZ and XOSC_KHZ.

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XOSC_MHZ and XOSC_KHZ may not be defined if we use a custom XIN clock
by defining PLL_SYS_REFDIV etc. calculated by vcocalc.py.

Signed-off-by: Christian Lang <lang.chr86@gmail.com>
This commit is contained in:
Christian Lang
2025-07-22 21:23:12 +02:00
committed by Damien George
parent ab620f4084
commit ebc9525c95
2 changed files with 6 additions and 8 deletions
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4
ports/rp2/clocks_extra.c
View File

@@ -83,8 +83,8 @@ void runtime_init_clocks_optional_usb(bool init_usb) {
clock_configure(clk_ref, clock_configure(clk_ref,
CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC, CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC,
0, // No aux mux 0, // No aux mux
XOSC_KHZ * KHZ, XOSC_HZ,
XOSC_KHZ * KHZ); XOSC_HZ);
/// \tag::configure_clk_sys[] /// \tag::configure_clk_sys[]
// CLK SYS = PLL SYS (usually) 125MHz / 1 = 125MHz // CLK SYS = PLL SYS (usually) 125MHz / 1 = 125MHz

10
ports/rp2/modmachine.c
View File

@@ -163,8 +163,6 @@ static void mp_machine_lightsleep(size_t n_args, const mp_obj_t *args) {
} }
} }
const uint32_t xosc_hz = XOSC_MHZ * 1000000;
uint32_t my_interrupts = MICROPY_BEGIN_ATOMIC_SECTION(); uint32_t my_interrupts = MICROPY_BEGIN_ATOMIC_SECTION();
#if MICROPY_PY_NETWORK_CYW43 #if MICROPY_PY_NETWORK_CYW43
if (cyw43_poll_is_pending()) { if (cyw43_poll_is_pending()) {
@@ -200,18 +198,18 @@ static void mp_machine_lightsleep(size_t n_args, const mp_obj_t *args) {
#endif #endif
// CLK_REF = XOSC // CLK_REF = XOSC
clock_configure(clk_ref, CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC, 0, xosc_hz, xosc_hz); clock_configure(clk_ref, CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC, 0, XOSC_HZ, XOSC_HZ);
// CLK_SYS = CLK_REF // CLK_SYS = CLK_REF
clock_configure(clk_sys, CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLK_REF, 0, xosc_hz, xosc_hz); clock_configure(clk_sys, CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLK_REF, 0, XOSC_HZ, XOSC_HZ);
// CLK_RTC = XOSC / 256 // CLK_RTC = XOSC / 256
#if PICO_RP2040 #if PICO_RP2040
clock_configure(clk_rtc, 0, CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_XOSC_CLKSRC, xosc_hz, xosc_hz / 256); clock_configure(clk_rtc, 0, CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_XOSC_CLKSRC, XOSC_HZ, XOSC_HZ / 256);
#endif #endif
// CLK_PERI = CLK_SYS // CLK_PERI = CLK_SYS
clock_configure(clk_peri, 0, CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLK_SYS, xosc_hz, xosc_hz); clock_configure(clk_peri, 0, CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLK_SYS, XOSC_HZ, XOSC_HZ);
// Disable PLLs. // Disable PLLs.
pll_deinit(pll_sys); pll_deinit(pll_sys);