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micropython/ports/stm32/boards/stm32l072_af.csv
Jim Mussared 286b1b3ed9 stm32/boards: Format stm32 alternate function csv files. 
Changes are:
- Pad all cells to make them easier to read.
- Ensure all files have exactly 19 columns (Port,Pin,AF0-15,ADC)

This work was funded through GitHub Sponsors.

Signed-off-by: Jim Mussared <jim.mussared@gmail.com>
2023-11-03 14:08:39 +11:00

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1Port Pin AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 ADC
2SPI1/SPI2/I2S2/USART1/2/LPUART1/USB/LPTIM1/TSC/TIM2/21/22/EVENTOUT/SYS_AFSPI1/SPI2/I2S2/I2C1/TIM2/21SPI1/SPI2/I2S2/LPUART1/USART5/USB/LPTIM1/TIM2/3/EVENTOUT/SYS_AFI2C1/TSC/EVENTOUTI2C1/USART1/2/LPUART1/TIM3/22/EVENTOUTSPI2/I2S2/I2C2/USART1/TIM2/21/22I2C1/2/LPUART1/USART4/UASRT5/TIM21/EVENTOUTI2C3/LPUART1/COMP1/2/TIM3ADC
3PortAPA0 TIM2_CH1 TSC_G1_IO1 USART2_CTS TIM2_ETR USART4_TX COMP1_OUT ADC1_IN0
4PortAPA1 EVENTOUT TIM2_CH2 TSC_G1_IO2 USART2_RTS/USART2_DE TIM21_ETR USART4_RX ADC1_IN1
5PortAPA2 TIM21_CH1 TIM2_CH3 TSC_G1_IO3 USART2_TX LPUART1_TX COMP2_OUT ADC1_IN2
6PortAPA3 TIM21_CH2 TIM2_CH4 TSC_G1_IO4 USART2_RX LPUART1_RX ADC1_IN3
7PortAPA4 SPI1_NSS TSC_G2_IO1 USART2_CK TIM22_ETR ADC1_IN4
8PortAPA5 SPI1_SCK TIM2_ETR TSC_G2_IO2 TIM2_CH1 ADC1_IN5
9PortAPA6 SPI1_MISO TIM3_CH1 TSC_G2_IO3 LPUART1_CTS TIM22_CH1 EVENTOUT COMP1_OUT ADC1_IN6
10PortAPA7 SPI1_MOSI TIM3_CH2 TSC_G2_IO4 TIM22_CH2 EVENTOUT COMP2_OUT ADC1_IN7
11PortAPA8 MCO USB_CRS_SYNC EVENTOUT USART1_CK I2C3_SCL
12PortAPA9 MCO TSC_G4_IO1 USART1_TX I2C1_SCL I2C3_SMBA
13PortAPA10TSC_G4_IO2 USART1_RX I2C1_SDA
14PortAPA11SPI1_MISO EVENTOUT TSC_G4_IO3 USART1_CTS COMP1_OUT
15PortAPA12SPI1_MOSI EVENTOUT TSC_G4_IO4 USART1_RTS/USART1_DE COMP2_OUT
16PortAPA13SWDIO USB_NOE LPUART1_RX
17PortAPA14SWCLK USART2_TX LPUART1_TX
18PortAPA15SPI1_NSS TIM2_ETR EVENTOUT USART2_RX TIM2_CH1 USART4_RTS/USART4_DE
19PortBPB0 EVENTOUT TIM3_CH3 TSC_G3_IO2 ADC1_IN8
20PortBPB1 TIM3_CH4 TSC_G3_IO3 LPUART1_RTS/LPUART1_DE ADC1_IN9
21PortBPB2 LPTIM1_OUT TSC_G3_IO4 I2C3_SMBA
22PortBPB3 SPI1_SCK TIM2_CH2 TSC_G5_IO1 EVENTOUT USART1_RTS/USART1_DE USART5_TX
23PortBPB4 SPI1_MISO TIM3_CH1 TSC_G5_IO2 TIM22_CH1 USART1_CTS USART5_RX I2C3_SDA
24PortBPB5 SPI1_MOSI LPTIM1_IN1 I2C1_SMBA TIM3_CH2/TIM22_CH2 USART1_CK USART5_CK/USART5_RTS/USART5_DE
25PortBPB6 USART1_TX I2C1_SCL LPTIM1_ETR TSC_G5_IO3
26PortBPB7 USART1_RX I2C1_SDA LPTIM1_IN2 TSC_G5_IO4 USART4_CTS
27PortBPB8 TSC_SYNC I2C1_SCL
28PortBPB9 EVENTOUT I2C1_SDA SPI2_NSS/I2S2_WS
29PortBPB10TIM2_CH3 TSC_SYNC LPUART1_TX SPI2_SCK I2C2_SCL LPUART1_RX
30PortBPB11EVENTOUT TIM2_CH4 TSC_G6_IO1 LPUART1_RX I2C2_SDA LPUART1_TX
31PortBPB12SPI2_NSS/I2S2_WS LPUART1_RTS/LPUART1_DE TSC_G6_IO2 I2C2_SMBA EVENTOUT
32PortBPB13SPI2_SCK/I2S2_CK MCO TSC_G6_IO3 LPUART1_CTS I2C2_SCL TIM21_CH1
33PortBPB14SPI2_MISO/I2S2_MCK RTC_OUT TSC_G6_IO4 LPUART1_RTS/LPUART1_DE I2C2_SDA TIM21_CH2
34PortBPB15SPI2_MOSI/I2S2_SD RTC_REFIN
35PortCPC0 LPTIM1_IN1 EVENTOUT TSC_G7_IO1 LPUART1_RX I2C3_SCL ADC1_IN10
36PortCPC1 LPTIM1_OUT EVENTOUT TSC_G7_IO2 LPUART1_TX I2C3_SDA ADC1_IN11
37PortCPC2 LPTIM1_IN2 SPI2_MISO/I2S2_MCK TSC_G7_IO3 ADC1_IN12
38PortCPC3 LPTIM1_ETR SPI2_MOSI/I2S2_SD TSC_G7_IO4 ADC1_IN13
39PortCPC4 EVENTOUT LPUART1_TX ADC1_IN14
40PortCPC5 LPUART1_RX TSC_G3_IO1 ADC1_IN15
41PortCPC6 TIM22_CH1 TIM3_CH1 TSC_G8_IO1
42PortCPC7 TIM22_CH2 TIM3_CH2 TSC_G8_IO2
43PortCPC8 TIM22_ETR TIM3_CH3 TSC_G8_IO3
44PortCPC9 TIM21_ETR USB_NOE/TIM3_CH4 TSC_G8_IO4 I2C3_SDA
45PortCPC10LPUART1_TX USART4_TX
46PortCPC11LPUART1_RX USART4_RX
47PortCPC12USART5_TX USART4_CK
48PortCPC13
49PortCPC14
50PortCPC15
51PortDPD0 TIM21_CH1 SPI2_NSS/I2S2_WS
52PortDPD1 SPI2_SCK/I2S2_CK
53PortDPD2 LPUART1_RTS/LPUART1_DE TIM3_ETR USART5_RX
54PortDPD3 USART2_CTS SPI2_MISO/I2S2_MCK
55PortDPD4 USART2_RTS/USART2_DE SPI2_MOSI/I2S2_SD
56PortDPD5 USART2_TX
57PortDPD6 USART2_RX
58PortDPD7 USART2_CK TIM21_CH2
59PortDPD8 LPUART1_TX
60PortDPD9 LPUART1_RX
61PortDPD10
62PortDPD11LPUART1_CTS
63PortDPD12LPUART1_RTS/LPUART1_DE
64PortDPD13
65PortDPD14
66PortDPD15USB_CRS_SYNC
67PortEPE0 EVENTOUT
68PortEPE1 EVENTOUT
69PortEPE2 TIM3_ETR
70PortEPE3 TIM22_CH1 TIM3_CH1
71PortEPE4 TIM22_CH2 TIM3_CH2
72PortEPE5 TIM21_CH1 TIM3_CH3
73PortEPE6 TIM21_CH2 TIM3_CH4
74PortEPE7 USART5_CK/USART5_RTS/USART5_DE
75PortEPE8 USART4_TX
76PortEPE9 TIM2_CH1 TIM2_ETR USART4_RX
77PortEPE10TIM2_CH2 USART5_TX
78PortEPE11TIM2_CH3 USART5_RX
79PortEPE12TIM2_CH4 SPI1_NSS
80PortEPE13SPI1_SCK
81PortEPE14SPI1_MISO
82PortEPE15SPI1_MOSI
83PortHPH0 USB_CRS_SYNC
84PortHPH1
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