1006ed69f0
This commit expands the Xtensa inline assembler to support most if not all opcodes available on the ESP8266 and LX3 Xtensa cores. This is meant as a stepping stone to add inline assembler support for the ESP32 and its LX6 core, along to windowed-specific opcodes and additional opcodes that are present only on the LX7 core (ESP32-S3 and later). New opcodes being added are covered by tests, and the provided tests were expanded to also include opcodes available in the existing implementation. Given that the ESP8266 space requirements are tighter than ESP32's, certain opcodes that won't be commonly used have been put behind a define to save some space in the general use case. Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
138 lines
1.6 KiB
Python
138 lines
1.6 KiB
Python
@micropython.asm_xtensa
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def lsl1(a2):
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slli(a2, a2, 1)
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print(hex(lsl1(0x123)))
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@micropython.asm_xtensa
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def lsl23(a2):
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slli(a2, a2, 23)
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print(hex(lsl23(1)))
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@micropython.asm_xtensa
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def lsr1(a2):
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srli(a2, a2, 1)
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print(hex(lsr1(0x123)))
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@micropython.asm_xtensa
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def lsr15(a2):
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srli(a2, a2, 15)
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print(hex(lsr15(0x80000000)))
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@micropython.asm_xtensa
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def asr1(a2):
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srai(a2, a2, 1)
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print(hex(asr1(0x123)))
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@micropython.asm_xtensa
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def asr31(a2):
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srai(a2, a2, 31)
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print(hex(asr31(0x80000000)))
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@micropython.asm_xtensa
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def lsl1r(a2):
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movi(a3, 1)
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ssl(a3)
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sll(a2, a2)
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print(hex(lsl1r(0x123)))
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@micropython.asm_xtensa
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def lsr1r(a2):
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movi(a3, 1)
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ssr(a3)
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srl(a2, a2)
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print(hex(lsr1r(0x123)))
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@micropython.asm_xtensa
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def asr1r(a2):
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movi(a3, 1)
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ssr(a3)
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sra(a2, a2)
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print(hex(asr1r(0x123)))
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@micropython.asm_xtensa
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def sll9(a2):
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ssai(9)
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sll(a2, a2)
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print(hex(sll9(1)))
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@micropython.asm_xtensa
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def srlr(a2, a3):
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ssa8l(a3)
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srl(a2, a2)
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print(hex(srlr(0x12340000, 2)))
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@micropython.asm_xtensa
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def sllr(a2, a3):
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ssa8b(a3)
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sll(a2, a2)
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print(hex(sllr(0x1234, 2)))
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@micropython.asm_xtensa
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def srcr(a2, a3, a4):
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ssr(a4)
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src(a2, a2, a3)
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print(hex(srcr(0x00000001, 0x80000000, 2)))
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@micropython.asm_xtensa
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def srai24(a2):
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srai(a2, a2, 24)
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print(hex(srai24(0x12345678)))
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@micropython.asm_xtensa
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def nsar(a2, a3):
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nsa(a2, a3)
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print(nsar(0x12345678, 0))
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print(nsar(0x12345678, -1))
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@micropython.asm_xtensa
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def nsaur(a2, a3):
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nsau(a2, a3)
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print(nsaur(0x12345678, 0))
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