1866ed7e2e
This commit implements 10/100 Mbit Ethernet support in the mimxrt port. The following boards are configured without ETH network: - MIMXRT1010_EVK - Teensy 4.0 The following boards are configured with ETH network: - MIMXRT1020_EVK - MIMXRT1050_EVK - MIMXRT1060_EVK - MIMXRT1064_EVK - Teensy 4.1 Ethernet support tested with TEENSY 4.1, MIMRTX1020_EVK and MIMXRT1050_EVK. Build tested with Teensy 4.0 and MIMXRT1010_EVK to be still working. Compiles and builds properly for MIMXRT1060_EVK and MIMXRT1064_EVK, but not tested lacking suitable boards. Tested functions are: - ping works bothway - simple UDP transfer works bothway - ntptime works - the ftp server works - secure socker works - telnet and webrepl works The MAC address is 0x02 plus 5 bytes from the manifacturing info field, which can be considered as unique per device. Some boards do not wire the RESET and INT pin of the PHY transceiver. For operation, these are not required. If they are defined, they will be used.
282 lines
11 KiB
C
282 lines
11 KiB
C
/*
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* Copyright 2020 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_phydp83825.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*! @brief Defines the PHY PD83825 vendor defined registers. */
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#define PHY_PHYSTS_REG 0x10U // Phy status register
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#define PHY_BISCR_REG 0x16U // RMII Config register.
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#define PHY_RCSR_REG 0x17U // RMII Config register.
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#define PHY_CONTROL2_REG 0x1FU /*!< The PHY control register 2. */
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/*! @brief Defines the PHY DP82825 ID number. */
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#define PHY_CONTROL_ID1 0x2000U /*!< The PHY ID1 */
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/*! @brief Defines the mask flag of operation mode in control registers */
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#define PHY_PHYSTS_100FULLDUPLEX_MASK 0x0006U /*!< The PHY 100M full duplex mask. */
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#define PHY_PHYSTS_DUPLEX_MASK 0x0004U /*!< The PHY full duplex mask. */
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#define PHY_PHYSTS_100M_MASK 0x0002U /*!< The PHY 100M mask. */
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#define PHY_PHYSTS_LINK_MASK 0x0001U /*!< The PHY link up mask. */
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#define PYH_RMII_CLOCK_SELECT 0x80 // Select 50MHz clock
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#define PHY_BISCR_REMOTELOOP_MASK 0x1FU // !< The PHY remote loopback mask.
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#define PHY_BISCR_REMOTELOOP_MODE 0x08U // !< The PHY remote loopback mode.
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/*! @brief Defines the timeout macro. */
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#define PHY_READID_TIMEOUT_COUNT 1000U
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*******************************************************************************
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* Variables
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******************************************************************************/
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const phy_operations_t phydp83825_ops = {.phyInit = PHY_DP83825_Init,
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.phyWrite = PHY_DP83825_Write,
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.phyRead = PHY_DP83825_Read,
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.getAutoNegoStatus = PHY_DP83825_GetAutoNegotiationStatus,
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.getLinkStatus = PHY_DP83825_GetLinkStatus,
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.getLinkSpeedDuplex = PHY_DP83825_GetLinkSpeedDuplex,
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.setLinkSpeedDuplex = PHY_DP83825_SetLinkSpeedDuplex,
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.enableLoopback = PHY_DP83825_EnableLoopback};
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/*******************************************************************************
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* Code
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******************************************************************************/
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status_t PHY_DP83825_Init(phy_handle_t *handle, const phy_config_t *config) {
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uint32_t counter = PHY_READID_TIMEOUT_COUNT;
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status_t result = kStatus_Success;
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uint32_t regValue = 0;
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/* Init MDIO interface. */
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MDIO_Init(handle->mdioHandle);
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/* Assign phy address. */
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handle->phyAddr = config->phyAddr;
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/* Check PHY ID. */
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do
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{
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result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_ID1_REG, ®Value);
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if (result != kStatus_Success) {
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return result;
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}
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counter--;
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} while ((regValue != PHY_CONTROL_ID1) && (counter != 0U));
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if (counter == 0U) {
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return kStatus_Fail;
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}
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/* Reset PHY. */
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result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK);
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if (result == kStatus_Success) {
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result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_RCSR_REG, ®Value);
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if (result != kStatus_Success) {
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return result;
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}
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result =
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MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_RCSR_REG, (regValue | PYH_RMII_CLOCK_SELECT));
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if (result != kStatus_Success) {
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return result;
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}
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if (config->autoNeg) {
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/* Set the auto-negotiation then start it. */
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result =
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MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_AUTONEG_ADVERTISE_REG,
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(PHY_100BASETX_FULLDUPLEX_MASK | PHY_100BASETX_HALFDUPLEX_MASK |
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PHY_10BASETX_FULLDUPLEX_MASK | PHY_10BASETX_HALFDUPLEX_MASK | PHY_IEEE802_3_SELECTOR_MASK));
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if (result == kStatus_Success) {
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result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG,
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(PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK));
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}
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} else {
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/* This PHY only supports 10/100M speed. */
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assert(config->speed <= kPHY_Speed100M);
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/* Disable isolate mode */
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result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, ®Value);
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if (result != kStatus_Success) {
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return result;
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}
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regValue &= ~PHY_BCTL_ISOLATE_MASK;
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result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, regValue);
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if (result != kStatus_Success) {
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return result;
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}
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/* Disable the auto-negotiation and set user-defined speed/duplex configuration. */
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result = PHY_DP83825_SetLinkSpeedDuplex(handle, config->speed, config->duplex);
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}
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}
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return result;
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}
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status_t PHY_DP83825_Write(phy_handle_t *handle, uint32_t phyReg, uint32_t data) {
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return MDIO_Write(handle->mdioHandle, handle->phyAddr, phyReg, data);
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}
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status_t PHY_DP83825_Read(phy_handle_t *handle, uint32_t phyReg, uint32_t *dataPtr) {
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return MDIO_Read(handle->mdioHandle, handle->phyAddr, phyReg, dataPtr);
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}
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status_t PHY_DP83825_GetAutoNegotiationStatus(phy_handle_t *handle, bool *status) {
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assert(status);
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status_t result;
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uint32_t regValue;
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*status = false;
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/* Check auto negotiation complete. */
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result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_BASICSTATUS_REG, ®Value);
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if (result == kStatus_Success) {
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if ((regValue & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0U) {
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*status = true;
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}
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}
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return result;
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}
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status_t PHY_DP83825_GetLinkStatus(phy_handle_t *handle, bool *status) {
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assert(status);
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status_t result;
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uint32_t regValue;
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/* Read the basic status register. */
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result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_BASICSTATUS_REG, ®Value);
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if (result == kStatus_Success) {
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if ((PHY_BSTATUS_LINKSTATUS_MASK & regValue) != 0U) {
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/* Link up. */
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*status = true;
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} else {
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/* Link down. */
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*status = false;
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}
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}
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return result;
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}
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status_t PHY_DP83825_GetLinkSpeedDuplex(phy_handle_t *handle, phy_speed_t *speed, phy_duplex_t *duplex) {
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assert(!((speed == NULL) && (duplex == NULL)));
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status_t result;
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uint32_t regValue;
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uint32_t flag;
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/* Read the control register. */
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result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_PHYSTS_REG, ®Value);
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if (result == kStatus_Success) {
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if (speed != NULL) {
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flag = regValue & PHY_PHYSTS_100M_MASK;
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if (flag) {
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*speed = kPHY_Speed10M;
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} else {
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*speed = kPHY_Speed100M;
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}
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}
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if (duplex != NULL) {
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flag = regValue & PHY_PHYSTS_DUPLEX_MASK;
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if (flag) {
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*duplex = kPHY_FullDuplex;
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} else {
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*duplex = kPHY_HalfDuplex;
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}
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}
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}
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return result;
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}
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status_t PHY_DP83825_SetLinkSpeedDuplex(phy_handle_t *handle, phy_speed_t speed, phy_duplex_t duplex) {
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/* This PHY only supports 10/100M speed. */
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assert(speed <= kPHY_Speed100M);
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status_t result;
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uint32_t regValue;
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result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, ®Value);
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if (result == kStatus_Success) {
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/* Disable the auto-negotiation and set according to user-defined configuration. */
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regValue &= ~PHY_BCTL_AUTONEG_MASK;
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if (speed == kPHY_Speed100M) {
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regValue |= PHY_BCTL_SPEED0_MASK;
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} else {
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regValue &= ~PHY_BCTL_SPEED0_MASK;
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}
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if (duplex == kPHY_FullDuplex) {
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regValue |= PHY_BCTL_DUPLEX_MASK;
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} else {
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regValue &= ~PHY_BCTL_DUPLEX_MASK;
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}
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result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, regValue);
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}
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return result;
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}
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status_t PHY_DP83825_EnableLoopback(phy_handle_t *handle, phy_loop_t mode, phy_speed_t speed, bool enable) {
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/* This PHY only supports local/remote loopback and 10/100M speed. */
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assert(mode <= kPHY_RemoteLoop);
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assert(speed <= kPHY_Speed100M);
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status_t result = kStatus_Success;
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uint32_t regValue;
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/* Set the loop mode. */
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if (enable) {
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if (mode == kPHY_LocalLoop) {
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if (speed == kPHY_Speed100M) {
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regValue = PHY_BCTL_SPEED0_MASK | PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK;
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} else {
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regValue = PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK;
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}
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return MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, regValue);
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} else {
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/* Remote loopback only supports 100M full-duplex. */
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assert(speed == kPHY_Speed100M);
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regValue = PHY_BCTL_SPEED0_MASK | PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK;
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result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, regValue);
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if (result != kStatus_Success) {
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return result;
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}
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/* Set the remote loopback bit. */
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result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_BISCR_REG, ®Value);
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if (result == kStatus_Success) {
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return MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_BISCR_REG,
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(regValue & ~PHY_BISCR_REMOTELOOP_MASK) | PHY_BISCR_REMOTELOOP_MODE);
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}
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}
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} else {
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/* Disable the loop mode. */
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if (mode != kPHY_LocalLoop) {
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/* First read the current status in control one register. */
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result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_BISCR_REG, ®Value);
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if (result == kStatus_Success) {
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return MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_BISCR_REG,
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(regValue & ~PHY_BISCR_REMOTELOOP_MASK));
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}
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}
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/* First read the current status in control register. */
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result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, ®Value);
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if (result == kStatus_Success) {
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regValue &= ~PHY_BCTL_LOOP_MASK;
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return MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG,
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(regValue | PHY_BCTL_RESTART_AUTONEG_MASK));
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}
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}
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return result;
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}
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