5e990cc27f
The RT1176 has two cores, but the actual firmware supports only the CM7. There are currently no good plans on how to use the CM4. The actual MIMXRT1170_EVK board is on par with the existing MIMXRT boards, with the following extensions: - Use 64 MB RAM for the heap. - Support both LAN interfaces as LAN(0) and LAN(1), with LAN(1) being the 1GB interface. The dual LAN port interface can eventually be adapted as well for the RT1062 MCU. This work was done in collaboration with @alphaFred.
388 lines
15 KiB
C
388 lines
15 KiB
C
/*
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* Copyright 2020 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_phyrtl8211f.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*! @brief Defines the PHY RTL8211F vendor defined registers. */
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#define PHY_SPECIFIC_STATUS_REG 0x1AU /*!< The PHY specific status register. */
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#define PHY_PAGE_SELECT_REG 0x1FU /*!< The PHY page select register. */
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/*! @brief Defines the PHY RTL8211F ID number. */
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#define PHY_CONTROL_ID1 0x001CU /*!< The PHY ID1 . */
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/*! @brief Defines the mask flag in specific status register. */
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#define PHY_SSTATUS_LINKSTATUS_MASK 0x04U /*!< The PHY link status mask. */
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#define PHY_SSTATUS_LINKSPEED_MASK 0x30U /*!< The PHY link speed mask. */
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#define PHY_SSTATUS_LINKDUPLEX_MASK 0x08U /*!< The PHY link duplex mask. */
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#define PHY_SSTATUS_LINKSPEED_SHIFT 4U /*!< The link speed shift */
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/*! @brief Defines the PHY RTL8211F extra page and the registers in specified page. */
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#define PHY_PAGE_RGMII_TXRX_DELAY_ADDR 0xD08U /*!< The register page including RGMII TX/RX delay setting. */
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#define PHY_RGMII_TX_DELAY_REG 0x11U /*!< The RGMII TXC delay register. */
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#define PHY_RGMII_RX_DELAY_REG 0x15U /*!< The RGMII RXC delay register. */
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#define PHY_RGMII_TX_DELAY_MASK 0x100U /*!< The RGMII TXC delay mask. */
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#define PHY_RGMII_RX_DELAY_MASK 0x8U /*!< The RGMII RXC delay mask. */
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/*! @brief MDIO MMD Devices .*/
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#define PHY_MDIO_MMD_PCS 3U
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#define PHY_MDIO_MMD_AN 7U
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/*! @brief MDIO MMD Physical Coding layer device registers .*/
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#define PHY_MDIO_PCS_EEE_CAP 0x14U /* EEE capability */
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/*! @brief MDIO MMD AutoNegotiation device registers .*/
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#define PHY_MDIO_AN_EEE_ADV 0x3CU /* EEE advertisement */
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/*! @brief MDIO MMD EEE mask flags. (common for adv and cap) */
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#define PHY_MDIO_EEE_100TX 0x2U
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#define PHY_MDIO_EEE_1000T 0x4U
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/*! @brief Defines the timeout macro. */
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#define PHY_READID_TIMEOUT_COUNT 1000U
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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static status_t PHY_RTL8211F_MMD_SetDevice(phy_handle_t *handle,
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uint8_t device,
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uint16_t addr,
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phy_mmd_access_mode_t mode);
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static inline status_t PHY_RTL8211F_MMD_ReadData(phy_handle_t *handle, uint32_t *data);
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static inline status_t PHY_RTL8211F_MMD_WriteData(phy_handle_t *handle, uint32_t data);
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static status_t PHY_RTL8211F_MMD_Read(phy_handle_t *handle, uint8_t device, uint16_t addr, uint32_t *data);
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static status_t PHY_RTL8211F_MMD_Write(phy_handle_t *handle, uint8_t device, uint16_t addr, uint32_t data);
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/*******************************************************************************
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* Variables
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******************************************************************************/
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const phy_operations_t phyrtl8211f_ops = {.phyInit = PHY_RTL8211F_Init,
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.phyWrite = PHY_RTL8211F_Write,
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.phyRead = PHY_RTL8211F_Read,
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.getAutoNegoStatus = PHY_RTL8211F_GetAutoNegotiationStatus,
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.getLinkStatus = PHY_RTL8211F_GetLinkStatus,
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.getLinkSpeedDuplex = PHY_RTL8211F_GetLinkSpeedDuplex,
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.setLinkSpeedDuplex = PHY_RTL8211F_SetLinkSpeedDuplex,
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.enableLoopback = PHY_RTL8211F_EnableLoopback};
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/*******************************************************************************
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* Code
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******************************************************************************/
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status_t PHY_RTL8211F_Init(phy_handle_t *handle, const phy_config_t *config) {
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uint32_t counter = PHY_READID_TIMEOUT_COUNT;
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status_t result;
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uint32_t regValue = 0U;
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/* Init MDIO interface. */
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MDIO_Init(handle->mdioHandle);
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/* Assign phy address. */
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handle->phyAddr = config->phyAddr;
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/* Check PHY ID. */
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do
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{
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result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_ID1_REG, ®Value);
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if (result != kStatus_Success) {
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return result;
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}
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counter--;
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} while ((regValue != PHY_CONTROL_ID1) && (counter != 0U));
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if (counter == 0U) {
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return kStatus_Fail;
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}
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/* Reset PHY. */
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result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK);
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if (result != kStatus_Success) {
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return result;
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}
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/* The RGMII specifies output TXC/RXC and TXD/RXD without any clock skew. Need to add skew on clock line
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to make sure the other side sample right data. This can also be done in PCB traces. */
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result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_PAGE_SELECT_REG, PHY_PAGE_RGMII_TXRX_DELAY_ADDR);
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if (result != kStatus_Success) {
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return result;
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}
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/* Set Tx Delay. */
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result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_RGMII_TX_DELAY_REG, ®Value);
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if (result == kStatus_Success) {
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regValue |= PHY_RGMII_TX_DELAY_MASK;
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result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_RGMII_TX_DELAY_REG, regValue);
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if (result != kStatus_Success) {
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return result;
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}
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} else {
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return result;
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}
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/* Set Rx Delay. */
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result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_RGMII_RX_DELAY_REG, ®Value);
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if (result == kStatus_Success) {
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regValue |= PHY_RGMII_RX_DELAY_MASK;
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result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_RGMII_RX_DELAY_REG, regValue);
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if (result != kStatus_Success) {
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return result;
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}
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} else {
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return result;
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}
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/* Restore to default page 0 */
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result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_PAGE_SELECT_REG, 0x0);
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if (result != kStatus_Success) {
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return result;
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}
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/* Energy Efficient Ethernet configuration */
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if (config->enableEEE) {
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/* Get capabilities */
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result = PHY_RTL8211F_MMD_Read(handle, PHY_MDIO_MMD_PCS, PHY_MDIO_PCS_EEE_CAP, ®Value);
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if (result == kStatus_Success) {
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/* Enable EEE for 100TX and 1000T */
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result = PHY_RTL8211F_MMD_Write(handle, PHY_MDIO_MMD_AN, PHY_MDIO_AN_EEE_ADV,
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regValue & (PHY_MDIO_EEE_1000T | PHY_MDIO_EEE_100TX));
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}
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} else {
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result = PHY_RTL8211F_MMD_Write(handle, PHY_MDIO_MMD_AN, PHY_MDIO_AN_EEE_ADV, 0);
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}
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if (result != kStatus_Success) {
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return result;
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}
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if (config->autoNeg) {
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/* Set the auto-negotiation. */
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result =
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MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_AUTONEG_ADVERTISE_REG,
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PHY_100BASETX_FULLDUPLEX_MASK | PHY_100BASETX_HALFDUPLEX_MASK | PHY_10BASETX_FULLDUPLEX_MASK |
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PHY_10BASETX_HALFDUPLEX_MASK | PHY_IEEE802_3_SELECTOR_MASK);
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if (result == kStatus_Success) {
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result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_1000BASET_CONTROL_REG,
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PHY_1000BASET_FULLDUPLEX_MASK);
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if (result == kStatus_Success) {
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result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, ®Value);
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if (result == kStatus_Success) {
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result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG,
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(regValue | PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK));
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}
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}
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}
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} else {
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/* Disable isolate mode */
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result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, ®Value);
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if (result != kStatus_Success) {
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return result;
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}
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regValue &= PHY_BCTL_ISOLATE_MASK;
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result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, regValue);
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if (result != kStatus_Success) {
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return result;
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}
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/* Disable the auto-negotiation and set user-defined speed/duplex configuration. */
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result = PHY_RTL8211F_SetLinkSpeedDuplex(handle, config->speed, config->duplex);
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}
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return result;
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}
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status_t PHY_RTL8211F_Write(phy_handle_t *handle, uint32_t phyReg, uint32_t data) {
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return MDIO_Write(handle->mdioHandle, handle->phyAddr, phyReg, data);
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}
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status_t PHY_RTL8211F_Read(phy_handle_t *handle, uint32_t phyReg, uint32_t *dataPtr) {
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return MDIO_Read(handle->mdioHandle, handle->phyAddr, phyReg, dataPtr);
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}
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status_t PHY_RTL8211F_GetAutoNegotiationStatus(phy_handle_t *handle, bool *status) {
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assert(status);
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status_t result;
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uint32_t regValue;
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*status = false;
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/* Check auto negotiation complete. */
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result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_BASICSTATUS_REG, ®Value);
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if (result == kStatus_Success) {
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if ((regValue & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0U) {
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*status = true;
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}
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}
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return result;
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}
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status_t PHY_RTL8211F_GetLinkStatus(phy_handle_t *handle, bool *status) {
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assert(status);
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status_t result;
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uint32_t regValue;
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/* Read the basic status register. */
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result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_SPECIFIC_STATUS_REG, ®Value);
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if (result == kStatus_Success) {
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if ((PHY_SSTATUS_LINKSTATUS_MASK & regValue) != 0U) {
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/* Link up. */
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*status = true;
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} else {
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/* Link down. */
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*status = false;
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}
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}
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return result;
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}
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status_t PHY_RTL8211F_GetLinkSpeedDuplex(phy_handle_t *handle, phy_speed_t *speed, phy_duplex_t *duplex) {
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assert(!((speed == NULL) && (duplex == NULL)));
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status_t result;
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uint32_t regValue;
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/* Read the status register. */
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result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_SPECIFIC_STATUS_REG, ®Value);
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if (result == kStatus_Success) {
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if (speed != NULL) {
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switch ((regValue & PHY_SSTATUS_LINKSPEED_MASK) >> PHY_SSTATUS_LINKSPEED_SHIFT)
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{
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case (uint32_t)kPHY_Speed10M:
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*speed = kPHY_Speed10M;
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break;
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case (uint32_t)kPHY_Speed100M:
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*speed = kPHY_Speed100M;
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break;
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case (uint32_t)kPHY_Speed1000M:
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*speed = kPHY_Speed1000M;
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break;
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default:
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*speed = kPHY_Speed10M;
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break;
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}
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}
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if (duplex != NULL) {
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if ((regValue & PHY_SSTATUS_LINKDUPLEX_MASK) != 0U) {
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*duplex = kPHY_FullDuplex;
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} else {
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*duplex = kPHY_HalfDuplex;
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}
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}
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}
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return result;
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}
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status_t PHY_RTL8211F_SetLinkSpeedDuplex(phy_handle_t *handle, phy_speed_t speed, phy_duplex_t duplex) {
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status_t result;
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uint32_t regValue;
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result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, ®Value);
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if (result == kStatus_Success) {
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/* Disable the auto-negotiation and set according to user-defined configuration. */
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regValue &= ~PHY_BCTL_AUTONEG_MASK;
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if (speed == kPHY_Speed1000M) {
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regValue &= PHY_BCTL_SPEED0_MASK;
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regValue |= PHY_BCTL_SPEED1_MASK;
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} else if (speed == kPHY_Speed100M) {
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regValue |= PHY_BCTL_SPEED0_MASK;
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regValue &= ~PHY_BCTL_SPEED1_MASK;
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} else {
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regValue &= ~PHY_BCTL_SPEED0_MASK;
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regValue &= ~PHY_BCTL_SPEED1_MASK;
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}
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if (duplex == kPHY_FullDuplex) {
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regValue |= PHY_BCTL_DUPLEX_MASK;
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} else {
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regValue &= ~PHY_BCTL_DUPLEX_MASK;
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}
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result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, regValue);
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}
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return result;
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}
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status_t PHY_RTL8211F_EnableLoopback(phy_handle_t *handle, phy_loop_t mode, phy_speed_t speed, bool enable) {
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/* This PHY only supports local loopback. */
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assert(mode == kPHY_LocalLoop);
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status_t result;
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uint32_t regValue;
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/* Set the loop mode. */
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if (enable) {
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if (speed == kPHY_Speed1000M) {
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regValue = PHY_BCTL_SPEED1_MASK | PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK;
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} else if (speed == kPHY_Speed100M) {
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regValue = PHY_BCTL_SPEED0_MASK | PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK;
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} else {
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regValue = PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK;
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}
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result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, regValue);
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} else {
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/* First read the current status in control register. */
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result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, ®Value);
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if (result == kStatus_Success) {
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regValue &= ~PHY_BCTL_LOOP_MASK;
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result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG,
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(regValue | PHY_BCTL_RESTART_AUTONEG_MASK));
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}
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}
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return result;
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}
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static status_t PHY_RTL8211F_MMD_SetDevice(phy_handle_t *handle,
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uint8_t device,
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uint16_t addr,
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phy_mmd_access_mode_t mode) {
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status_t result = kStatus_Success;
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/* Set Function mode of address access(b00) and device address. */
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result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_MMD_ACCESS_CONTROL_REG, device);
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if (result != kStatus_Success) {
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return result;
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}
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/* Set register address. */
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result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_MMD_ACCESS_DATA_REG, addr);
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if (result != kStatus_Success) {
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return result;
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}
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/* Set Function mode of data access(b01~11) and device address. */
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result =
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MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_MMD_ACCESS_CONTROL_REG, (uint32_t)mode | (uint32_t)device);
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return result;
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}
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static inline status_t PHY_RTL8211F_MMD_ReadData(phy_handle_t *handle, uint32_t *data) {
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return MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_MMD_ACCESS_DATA_REG, data);
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}
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static inline status_t PHY_RTL8211F_MMD_WriteData(phy_handle_t *handle, uint32_t data) {
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return MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_MMD_ACCESS_DATA_REG, data);
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}
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static status_t PHY_RTL8211F_MMD_Read(phy_handle_t *handle, uint8_t device, uint16_t addr, uint32_t *data) {
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status_t result = kStatus_Success;
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result = PHY_RTL8211F_MMD_SetDevice(handle, device, addr, kPHY_MMDAccessNoPostIncrement);
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if (result == kStatus_Success) {
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result = PHY_RTL8211F_MMD_ReadData(handle, data);
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}
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return result;
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}
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static status_t PHY_RTL8211F_MMD_Write(phy_handle_t *handle, uint8_t device, uint16_t addr, uint32_t data) {
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status_t result = kStatus_Success;
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result = PHY_RTL8211F_MMD_SetDevice(handle, device, addr, kPHY_MMDAccessNoPostIncrement);
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if (result == kStatus_Success) {
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result = PHY_RTL8211F_MMD_WriteData(handle, data);
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}
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return result;
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}
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