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hwconfig: Fix pad config for SD SPI, move clockrate to hwconfig #42

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matthias merged 0 commits from fix-sd-spi-hwconfig into main 2025-10-31 13:20:34 +00:00
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matthias commented 2025-10-13 21:23:19 +00:00
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The code snippet in hwconfig to adjust the drive strength was incorrect:
It was adjusting the wrong pins. This was probably not updated during
some pin shuffling in the breadboard phase.

Fix this by adjusting the correct pins. Experimentation shows that both
setting the slew rate to fast or setting the drive strength to 8 mA
(default: slow and 4 mA) is sufficient to make SD SPI work at 25 MHz on
the Rev1 PCB. For now, the combination 8 mA and slow is chosen (slow
slew rate should result in less high frequency EMI).

Also make the SD clock rate adjustable in hwconfig, and set it to 25 MHz
for Rev1 and 15 MHz for the breadboard setup.

The code snippet in hwconfig to adjust the drive strength was incorrect: It was adjusting the wrong pins. This was probably not updated during some pin shuffling in the breadboard phase. Fix this by adjusting the correct pins. Experimentation shows that both setting the slew rate to fast or setting the drive strength to 8 mA (default: slow and 4 mA) is sufficient to make SD SPI work at 25 MHz on the Rev1 PCB. For now, the combination 8 mA and slow is chosen (slow slew rate should result in less high frequency EMI). Also make the SD clock rate adjustable in hwconfig, and set it to 25 MHz for Rev1 and 15 MHz for the breadboard setup.
matthias self-assigned this 2025-10-13 21:23:19 +00:00
matthias added 1 commit 2025-10-13 21:23:20 +00:00
hwconfig: Fix pad config for SD SPI, move clockrate to hwconfig
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06777cb362 
The code snippet in hwconfig to adjust the drive strength was incorrect:
It was adjusting the wrong pins. This was probably not updated during
some pin shuffling in the breadboard phase.

Fix this by adjusting the correct pins. Experimentation shows that both
setting the slew rate to fast or setting the drive strength to 8 mA
(default: slow and 4 mA) is sufficient to make SD SPI work at 25 MHz on
the Rev1 PCB. For now, the combination 8 mA and slow is chosen (slow
slew rate should result in less high frequency EMI).

Also make the SD clock rate adjustable in hwconfig, and set it to 25 MHz
for Rev1 and 15 MHz for the breadboard setup.

Signed-off-by: Matthias Blankertz <matthias@blankertz.org>
matthias requested review from stefank 2025-10-13 21:23:20 +00:00
matthias added 2 commits 2025-10-13 21:38:39 +00:00
hwconfig: Fix pad config for SD SPI, move clockrate to hwconfig
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06777cb362 
The code snippet in hwconfig to adjust the drive strength was incorrect:
It was adjusting the wrong pins. This was probably not updated during
some pin shuffling in the breadboard phase.

Fix this by adjusting the correct pins. Experimentation shows that both
setting the slew rate to fast or setting the drive strength to 8 mA
(default: slow and 4 mA) is sufficient to make SD SPI work at 25 MHz on
the Rev1 PCB. For now, the combination 8 mA and slow is chosen (slow
slew rate should result in less high frequency EMI).

Also make the SD clock rate adjustable in hwconfig, and set it to 25 MHz
for Rev1 and 15 MHz for the breadboard setup.

Signed-off-by: Matthias Blankertz <matthias@blankertz.org>
hwconfig: Fix pad config for SD SPI, move clockrate to hwconfig
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502805e2e8 
The code snippet in hwconfig to adjust the drive strength was incorrect:
It was adjusting the wrong pins. This was probably not updated during
some pin shuffling in the breadboard phase.

Fix this by adjusting the correct pins. Experimentation shows that both
setting the slew rate to fast or setting the drive strength to 8 mA
(default: slow and 4 mA) is sufficient to make SD SPI work at 25 MHz on
the Rev1 PCB. For now, the combination 8 mA and slow is chosen (slow
slew rate should result in less high frequency EMI).

Also make the SD clock rate adjustable in hwconfig, and set it to 25 MHz
for Rev1 and 15 MHz for the breadboard setup.

Signed-off-by: Matthias Blankertz <matthias@blankertz.org>
stefank reviewed 2025-10-14 16:49:23 +00:00
software/src/hwconfig_Rev1.py
@@ -9,6 +9,7 @@ SD_DI = Pin.board.GP3
SD_DO = Pin.board.GP4
SD_SCK = Pin.board.GP2
SD_CS = Pin.board.GP5
SD_CLOCKRATE = 25000000
stefank commented 2025-10-14 16:49:23 +00:00
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Still causes issues with my 'SanDisk Ultra 32 GB' card. Reducing this back to 15000000 works, but 20000000 already yields a 'RuntimeError: sd_init() failed'

Still causes issues with my 'SanDisk Ultra 32 GB' card. Reducing this back to 15000000 works, but 20000000 already yields a 'RuntimeError: sd_init() failed'
matthias commented 2025-10-19 15:03:22 +00:00
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I think I have found the underlying issue and solved it in rp2_sd: Disable input synchronizer for MISO pin. Please re-test.

I think I have found the underlying issue and solved it in [rp2_sd: Disable input synchronizer for MISO pin](https://git.ka.blankertz.org/TonBERRY/tonberry-pico/commit/9357b4d24355b1ab4dc43c74842ce6dc3af9ca52). Please re-test.
matthias marked this conversation as resolved
matthias added 3 commits 2025-10-19 14:58:19 +00:00
rp2_sd: Disable input synchronizer for MISO pin 9357b4d243 
The PIO has an internal synchronizer on each GPIO input which adds two
cycles of delay. This prevents metastabilities in the PIO logic (see
RP2040 datasheet p. 374f). For high speed synchronous interfaces such as
SPI this needs to be disabled to reduce input delay.

Signed-off-by: Matthias Blankertz <matthias@blankertz.org>
rp2_sd: Improve error handling 7df6af09f1 
* In sd_cmd_read_complete, check read token and report appropriate error
  _before_ performing CRC check.
* In sd_read_csd, correctly handle the sd_cmd_read() failing.
* In sd_init, deinit the lower level sd_spi driver correctly on failure.

Signed-off-by: Matthias Blankertz <matthias@blankertz.org>
tools: standalone_mp3: Add read test, increase speed to 25 MHz
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c8d4ee3bd5 
Add a read test to the SD tests in standalone_mp3, and also apply the
drive strength setup and higher clockrate from board_Rev1.py.

Signed-off-by: Matthias Blankertz <matthias@blankertz.org>
matthias added 2 commits 2025-10-19 15:02:59 +00:00
tools: standalone_mp3: Add read test, increase speed to 25 MHz
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c8d4ee3bd5 
Add a read test to the SD tests in standalone_mp3, and also apply the
drive strength setup and higher clockrate from board_Rev1.py.

Signed-off-by: Matthias Blankertz <matthias@blankertz.org>
tools: standalone_mp3: Add read test, increase speed to 25 MHz
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2809d3f6e7 
Add a read test to the SD tests in standalone_mp3, and also apply the
drive strength setup and higher clockrate from board_Rev1.py.

Signed-off-by: Matthias Blankertz <matthias@blankertz.org>
matthias commented 2025-10-27 19:32:45 +00:00
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For further reference, screenshots of the SD SPI clock signal with different drive strength. (Taken with a passive 500 MHz / 10 MOhm / 11 pF probe).

2 mA drive strength

scope_2.png

4 mA drive strength

scope_3.png

8 mA drive strength

scope_4.png

12 mA drive strength

scope_5.png

For further reference, screenshots of the SD SPI clock signal with different drive strength. (Taken with a passive 500 MHz / 10 MOhm / 11 pF probe). ### 2 mA drive strength ![scope_2.png](/attachments/947e715b-4d61-47c9-8aae-b7b48493995e) ### 4 mA drive strength ![scope_3.png](/attachments/88d9faa1-d29d-41bb-ba47-6f5d4acb44cb) ### 8 mA drive strength ![scope_4.png](/attachments/1bff96bd-f40a-4bf7-b160-3dec79037d03) ### 12 mA drive strength ![scope_5.png](/attachments/fb5a4897-e901-415c-ae71-56200c143fd9)
scope_2.png
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scope_3.png
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scope_5.png
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stefank approved these changes 2025-10-29 15:22:15 +00:00
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Validated on my setup, works with SanDisk Ultra 32 GB card.

Validated on my setup, works with SanDisk Ultra 32 GB card.
matthias manually merged commit 4512b91763 into main 2025-10-31 13:20:34 +00:00
matthias deleted branch fix-sd-spi-hwconfig 2025-10-31 13:20:53 +00:00
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Reference: TonBERRY/tonberry-pico#42
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