Matthias Blankertz
9357b4d243
The PIO has an internal synchronizer on each GPIO input which adds two cycles of delay. This prevents metastabilities in the PIO logic (see RP2040 datasheet p. 374f). For high speed synchronous interfaces such as SPI this needs to be disabled to reduce input delay. Signed-off-by: Matthias Blankertz <matthias@blankertz.org>
64 lines
1.9 KiB
Plaintext
64 lines
1.9 KiB
Plaintext
// SPDX-License-Identifier: MIT
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// Copyright (c) 2024 Matthias Blankertz <matthias@blankertz.org>
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.program sd_spi_pio
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.side_set 1
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// data - MISO MOSI
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// sideset - SCK
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// normal SPI
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normal:
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.wrap_target
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out pins, 1 side 0 [1]
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in pins, 1 side 1 [1]
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.wrap
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// Special "wait for token" repeated read SPI
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wait_loop:
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pull block side 0 [0]
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mov osr, x side 0 [0]
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set y, 8 side 0 [0]
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read_loop:
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out pins, 1 side 0 [1]
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in pins, 1 side 1 [0]
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jmp y--, read_loop side 1 [0]
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mov isr, y side 0 [0]
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jmp x != y, wait_done side 0 [0]
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set y, 0 side 0 [0]
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mov y, isr side 0 [0]
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jmp wait_loop side 0 [0]
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wait_done:
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push block side 0 [0]
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jmp normal side 0 [0]
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% c-sdk {
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#include "hardware/clocks.h"
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#include <stdio.h>
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#include <math.h>
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static inline void sd_spi_pio_program_init(PIO pio, uint sm, uint offset, uint mosi, uint miso, uint sck, uint bitrate) {
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pio_gpio_init(pio, mosi);
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pio_gpio_init(pio, miso);
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pio_gpio_init(pio, sck);
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pio_sm_set_consecutive_pindirs(pio, sm, mosi, 1, true);
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pio_sm_set_consecutive_pindirs(pio, sm, miso, 1, false);
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pio_sm_set_consecutive_pindirs(pio, sm, sck, 1, true);
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pio_sm_config c = sd_spi_pio_program_get_default_config(offset);
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sm_config_set_out_pins(&c, mosi, 1);
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sm_config_set_in_pins(&c, miso);
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sm_config_set_sideset_pins(&c, sck);
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sm_config_set_out_shift(&c, false, true, 8);
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sm_config_set_in_shift(&c, false, true, 8);
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// high speed SPI needs to bypass the input synchronizers on the MISO pin
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hw_set_bits(&pio->input_sync_bypass, 1u << miso);
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const unsigned pio_freq = bitrate*4;
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const float div = clock_get_hz(clk_sys) / (float)pio_freq;
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sm_config_set_clkdiv(&c, div);
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pio_sm_init(pio, sm, offset, &c);
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}
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%}
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