diff --git a/rasterizer_l_tb.wcfg b/rasterizer_l_tb.wcfg
index 0e23e2c..1e3e15c 100644
--- a/rasterizer_l_tb.wcfg
+++ b/rasterizer_l_tb.wcfg
@@ -195,18 +195,22 @@
x0[15:0]
x0[15:0]
+ UNSIGNEDDECRADIX
x1[15:0]
x1[15:0]
+ UNSIGNEDDECRADIX
i0[15:0]
i0[15:0]
+ UNSIGNEDDECRADIX
i1[15:0]
i1[15:0]
+ UNSIGNEDDECRADIX
load_dx
@@ -235,26 +239,32 @@
i[15:0]
i[15:0]
+ UNSIGNEDDECRADIX
x[15:0]
x[15:0]
+ UNSIGNEDDECRADIX
ch[1:0]
ch[1:0]
+ UNSIGNEDDECRADIX
neg_dx[15:0]
neg_dx[15:0]
+ SIGNEDDECRADIX
x1_int[15:0]
x1_int[15:0]
+ UNSIGNEDDECRADIX
di[3:0]
di[3:0]
+ SIGNEDDECRADIX
si[3:0]
@@ -263,34 +273,42 @@
d_sub_1[15:0]
d_sub_1[15:0]
+ UNSIGNEDDECRADIX
d_sub_2[15:0]
d_sub_2[15:0]
+ UNSIGNEDDECRADIX
d_sub[15:0]
d_sub[15:0]
+ SIGNEDDECRADIX
d_sub_abs[15:0]
d_sub_abs[15:0]
+ SIGNEDDECRADIX
err[3:0]
err[3:0]
+ SIGNEDDECRADIX
err_next[15:0]
err_next[15:0]
+ SIGNEDDECRADIX
err_add_1[15:0]
err_add_1[15:0]
+ SIGNEDDECRADIX
err_add_2[15:0]
err_add_2[15:0]
+ SIGNEDDECRADIX
looping
@@ -307,18 +325,22 @@
i_int[3:0]
i_int[3:0]
+ UNSIGNEDDECRADIX
i_next[15:0]
i_next[15:0]
+ UNSIGNEDDECRADIX
i_add[15:0]
i_add[15:0]
+ UNSIGNEDDECRADIX
x_int[15:0]
x_int[15:0]
+ UNSIGNEDDECRADIX
step_done_next[3:0]
@@ -331,6 +353,7 @@
channel[1:0]
channel[1:0]
+ UNSIGNEDDECRADIX
next_step
diff --git a/src/bresenham_dp.vhd b/src/bresenham_dp.vhd
index 5468385..3c88723 100644
--- a/src/bresenham_dp.vhd
+++ b/src/bresenham_dp.vhd
@@ -35,12 +35,14 @@ entity bresenham_dp is
generic (
channels : integer := 5;
channels_ln2 : integer := 3;
- preinc_x : boolean := true);
+ preinc_x : boolean := true;
+ width : integer := 16);
port(
clk : in STD_LOGIC;
+ pause : in std_logic;
- x0, x1 : in unsigned(15 downto 0);
- i0, i1 : in unsigned(15 downto 0);
+ x0, x1 : in unsigned(width-1 downto 0);
+ i0, i1 : in unsigned(width-1 downto 0);
load_dx : in std_logic;
load_di : in std_logic;
@@ -49,34 +51,34 @@ entity bresenham_dp is
i_valid : out std_logic;
done : out std_logic;
- i : out unsigned(15 downto 0);
- x : out unsigned(15 downto 0);
+ i : out unsigned(width-1 downto 0);
+ x : out unsigned(width-1 downto 0);
ch : out unsigned(channels_ln2-1 downto 0));
end bresenham_dp;
architecture Behavioral of bresenham_dp is
- signal neg_dx : signed(15 downto 0) := to_signed(0, 16);
- signal x1_int : unsigned(15 downto 0) := to_unsigned(0, 16);
- type di_a is array(channels-1 downto 0) of signed(15 downto 0);
- signal di : di_a := (others => to_signed(0, 16));
+ signal neg_dx : signed(width-1 downto 0) := to_signed(0, width);
+ signal x1_int : unsigned(width-1 downto 0) := to_unsigned(0, width);
+ type di_a is array(channels-1 downto 0) of signed(width-1 downto 0);
+ signal di : di_a := (others => to_signed(0, width));
signal si : std_logic_vector(channels-1 downto 0) := (others => '0');
- signal d_sub_1, d_sub_2 : unsigned(15 downto 0) := to_unsigned(0, 16);
- signal d_sub, d_sub_abs : signed(15 downto 0) := to_signed(0, 16);
+ signal d_sub_1, d_sub_2 : unsigned(width-1 downto 0) := to_unsigned(0, width);
+ signal d_sub, d_sub_abs : signed(width-1 downto 0) := to_signed(0, width);
- type err_a is array(channels-1 downto 0) of signed(15 downto 0);
- signal err : err_a := (others => to_signed(0, 16));
- signal err_next : signed(15 downto 0) := to_signed(0, 16);
- signal err_add_1, err_add_2 : signed(15 downto 0) := to_signed(0, 16);
+ type err_a is array(channels-1 downto 0) of signed(width-1 downto 0);
+ signal err : err_a := (others => to_signed(0, width));
+ signal err_next : signed(width-1 downto 0) := to_signed(0, width);
+ signal err_add_1, err_add_2 : signed(width-1 downto 0) := to_signed(0, width);
signal looping : std_logic := '0';
signal err_gt_negdx, err_ge_di : std_logic := '0';
- type i_a is array(channels-1 downto 0) of unsigned(15 downto 0);
- signal i_int : i_a := (others => to_unsigned(0, 16));
- signal i_next, i_add : unsigned(15 downto 0) := to_unsigned(0, 16);
+ type i_a is array(channels-1 downto 0) of unsigned(width-1 downto 0);
+ signal i_int : i_a := (others => to_unsigned(0, width));
+ signal i_next, i_add : unsigned(width-1 downto 0) := to_unsigned(0, width);
- signal x_int : unsigned(15 downto 0) := to_unsigned(0, 16);
+ signal x_int : unsigned(width-1 downto 0) := to_unsigned(0, width);
signal step_done_next, step_done : std_logic_vector(channels-1 downto 0) := (others => '0');
@@ -90,7 +92,7 @@ architecture Behavioral of bresenham_dp is
begin
x_reg : process(clk)
begin
- if rising_edge(clk) then
+ if rising_edge(clk) and pause = '0' then
if load_dx = '1' then
neg_dx <= d_sub;
x1_int <= x1;
@@ -100,7 +102,7 @@ begin
di_reg : process(clk)
begin
- if rising_edge(clk) then
+ if rising_edge(clk) and pause = '0' then
if load_di = '1' then
di <= di(channels-2 downto 0) & d_sub_abs;
else
@@ -111,7 +113,7 @@ begin
si_reg : process(clk)
begin
- if rising_edge(clk) then
+ if rising_edge(clk) and pause = '0' then
if load_di = '1' then
si <= si(channels-2 downto 0) & d_sub(d_sub'left);
else
@@ -133,7 +135,7 @@ begin
err_reg : process(clk)
begin
- if rising_edge(clk) then
+ if rising_edge(clk) and pause = '0' then
err <= err(channels-2 downto 0) & err_next;
end if;
end process err_reg;
@@ -144,7 +146,7 @@ begin
err_add_2 <= di(channels-1) when init = '1' else
err(channels-1);
- err_next <= err(channels-1) when step_done(to_integer(channel)) = '1' else
+ err_next <= err(channels-1) when step_done(to_integer(channel)) = '1' and init = '0' else
err_add_1 + err_add_2;
err_gt_negdx <= '1' when (err(channels-1) & "0") > neg_dx else
@@ -157,7 +159,7 @@ begin
i_reg : process(clk)
begin
- if rising_edge(clk) then
+ if rising_edge(clk) and pause = '0' then
if load_di = '1' or init = '0' then
i_int <= i_int(channels-2 downto 0) & i_next;
end if;
@@ -173,7 +175,7 @@ begin
step_done_reg : process(clk)
begin
- if rising_edge(clk) then
+ if rising_edge(clk) and pause = '0' then
step_done <= step_done_next;
next_step <= next_step_next;
end if;
@@ -190,7 +192,7 @@ begin
channel_ctr : process(clk)
begin
- if rising_edge(clk) then
+ if rising_edge(clk) and pause = '0' then
if init = '1' then
channel <= to_unsigned(0, channels_ln2);
else
@@ -201,14 +203,14 @@ begin
init_dly_reg : process(clk)
begin
- if rising_edge(clk) then
+ if rising_edge(clk) and pause = '0' then
init_dly <= init;
end if;
end process init_dly_reg;
x_ctr : process(clk)
begin
- if rising_edge(clk) then
+ if rising_edge(clk) and pause = '0' then
done <= '0';
if load_di = '1' then
x_int <= x0;
diff --git a/src/rasterizer.vhd b/src/rasterizer.vhd
new file mode 100644
index 0000000..e9fbf89
--- /dev/null
+++ b/src/rasterizer.vhd
@@ -0,0 +1,333 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 03/22/2013 05:49:49 PM
+-- Design Name:
+-- Module Name: rasterizer - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool Versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity rasterizer is
+ generic (
+ dontcare : std_logic := '-';
+ width : integer := 12);
+ port (
+ clk : in std_logic;
+ pause : in std_logic;
+
+ x0, y0 : in unsigned(width-1 downto 0);
+ x1, y1 : in unsigned(width-1 downto 0);
+ x2, y2 : in unsigned(width-1 downto 0);
+
+ a0, a1, a2 : in unsigned(width-1 downto 0);
+ b0, b1, b2 : in unsigned(width-1 downto 0);
+ c0, c1, c2 : in unsigned(width-1 downto 0);
+ z0, z1, z2 : in unsigned(width-1 downto 0);
+ in_valid : in std_logic;
+ in_ready : out std_logic);
+end rasterizer;
+
+architecture mixed of rasterizer is
+ signal x0_reg, y0_reg, x1_reg, y1_reg, x2_reg, y2_reg : unsigned(width-1 downto 0);
+ signal a0_reg, a1_reg, a2_reg, b0_reg, b1_reg, b2_reg : unsigned(width-1 downto 0);
+ signal c0_reg, c1_reg, c2_reg, z0_reg, z1_reg, z2_reg : unsigned(width-1 downto 0);
+ signal inregs_full : std_logic := '0';
+
+ signal t_in_valid, t_in_ack : std_logic := '0';
+
+ signal t_pause : std_logic;
+
+ -- Gather output of t rasterizer
+ signal g_y_valid : std_logic := '0';
+ signal g_xl_valid, g_al_valid, g_bl_valid, g_cl_valid, g_zl_valid : std_logic := '0';
+ signal g_xr_valid, g_ar_valid, g_br_valid, g_cr_valid, g_zr_valid : std_logic := '0';
+ signal g_y : unsigned(width-1 downto 0);
+ signal g_xl, g_al, g_bl, g_cl, g_zl : unsigned(width-1 downto 0);
+ signal g_xr, g_ar, g_br, g_cr, g_zr : unsigned(width-1 downto 0);
+ signal g_all_valid, g_move : std_logic := '0';
+
+ -- Inputs for l rasterizer
+ signal l_y, l_x0, l_x1, l_a0, l_a1, l_b0, l_b1, l_c0, l_c1, l_z0, l_z1 : unsigned(width-1 downto 0);
+ signal lregs_full : std_logic := '0';
+
+ signal l_in_valid, l_in_ack : std_logic := '0';
+
+ signal l_pause : std_logic;
+
+begin
+
+ inregs : process(clk)
+ begin
+ if rising_edge(clk) then
+ if inregs_full = '0' and in_valid = '1' then
+ inregs_full <= '1';
+ y0_reg <= y0;
+ y1_reg <= y1;
+ y2_reg <= y2;
+ x0_reg <= x0;
+ x1_reg <= x1;
+ x2_reg <= x2;
+ a0_reg <= a0;
+ a1_reg <= a1;
+ a2_reg <= a2;
+ b0_reg <= b0;
+ b1_reg <= b1;
+ b2_reg <= b2;
+ c0_reg <= c0;
+ c1_reg <= c1;
+ c2_reg <= c2;
+ z0_reg <= z0;
+ z1_reg <= z1;
+ z2_reg <= z2;
+ elsif inregs_full = '1' and t_in_ack = '1' then
+ inregs_full <= '0';
+ end if;
+ end if;
+ end process inregs;
+
+ in_ready <= not inregs_full;
+ t_in_valid <= inregs_full;
+
+ rasterizer_t_1: entity work.rasterizer_t
+ generic map (
+ dontcare => dontcare,
+ width => width)
+ port map (
+ clk => clk,
+ pause => t_pause,
+ x0 => x0_reg,
+ y0 => y0_reg,
+ x1 => x1_reg,
+ y1 => y1_reg,
+ x2 => x2_reg,
+ y2 => y2_reg,
+ a0 => a0_reg,
+ a1 => a1_reg,
+ a2 => a2_reg,
+ b0 => b0_reg,
+ b1 => b1_reg,
+ b2 => b2_reg,
+ c0 => c0_reg,
+ c1 => c1_reg,
+ c2 => c2_reg,
+ z0 => z0_reg,
+ z1 => z1_reg,
+ z2 => z2_reg,
+ in_valid => t_in_valid,
+ in_ack => t_in_ack,
+ y => y,
+ xl => xl,
+ al => al,
+ bl => bl,
+ cl => cl,
+ zl => zl,
+ xr => xr,
+ ar => ar,
+ br => br,
+ cr => cr,
+ zr => zr,
+ y_valid => y_valid,
+ xl_valid => xl_valid,
+ al_valid => al_valid,
+ bl_valid => bl_valid,
+ cl_valid => cl_valid,
+ zl_valid => zl_valid,
+ xr_valid => xr_valid,
+ ar_valid => ar_valid,
+ br_valid => br_valid,
+ cr_valid => cr_valid,
+ zr_valid => zr_valid);
+
+ g_y_reg : process(clk)
+ begin
+ if rising_edge(clk) then
+ if y_valid = '1' then
+ g_y_valid <= '1';
+ g_y <= y;
+ elsif g_move = '1' then
+ g_y_valid <= '0';
+ end if;
+ end if;
+ end process g_y_reg;
+
+ g_xl_reg : process(clk)
+ begin
+ if rising_edge(clk) then
+ if xl_valid = '1' then
+ g_xl_valid <= '1';
+ g_xl <= xl;
+ elsif g_move = '1' then
+ g_xl_valid <= '0';
+ end if;
+ end if;
+ end process g_xl_reg;
+
+ g_al_reg : process(clk)
+ begin
+ if rising_edge(clk) then
+ if al_valid = '1' then
+ g_al_valid <= '1';
+ g_al <= al;
+ elsif g_move = '1' then
+ g_al_valid <= '0';
+ end if;
+ end if;
+ end process g_al_reg;
+
+ g_bl_reg : process(clk)
+ begin
+ if rising_edge(clk) then
+ if bl_valid = '1' then
+ g_bl_valid <= '1';
+ g_bl <= bl;
+ elsif g_move = '1' then
+ g_bl_valid <= '0';
+ end if;
+ end if;
+ end process g_bl_reg;
+
+ g_cl_reg : process(clk)
+ begin
+ if rising_edge(clk) then
+ if cl_valid = '1' then
+ g_cl_valid <= '1';
+ g_cl <= cl;
+ elsif g_move = '1' then
+ g_cl_valid <= '0';
+ end if;
+ end if;
+ end process g_cl_reg;
+
+ g_zl_reg : process(clk)
+ begin
+ if rising_edge(clk) then
+ if zl_valid = '1' then
+ g_zl_valid <= '1';
+ g_zl <= zl;
+ elsif g_move = '1' then
+ g_zl_valid <= '0';
+ end if;
+ end if;
+ end process g_zl_reg;
+
+ g_xr_reg : process(clk)
+ begin
+ if rising_edge(clk) then
+ if xr_valid = '1' then
+ g_xr_valid <= '1';
+ g_xr <= xr;
+ elsif g_move = '1' then
+ g_xr_valid <= '0';
+ end if;
+ end if;
+ end process g_xr_reg;
+
+ g_ar_reg : process(clk)
+ begin
+ if rising_edge(clk) then
+ if ar_valid = '1' then
+ g_ar_valid <= '1';
+ g_ar <= ar;
+ elsif g_move = '1' then
+ g_ar_valid <= '0';
+ end if;
+ end if;
+ end process g_ar_reg;
+
+ g_br_reg : process(clk)
+ begin
+ if rising_edge(clk) then
+ if br_valid = '1' then
+ g_br_valid <= '1';
+ g_br <= br;
+ elsif g_move = '1' then
+ g_br_valid <= '0';
+ end if;
+ end if;
+ end process g_br_reg;
+
+ g_cr_reg : process(clk)
+ begin
+ if rising_edge(clk) then
+ if cr_valid = '1' then
+ g_cr_valid <= '1';
+ g_cr <= cl;
+ elsif g_move = '1' then
+ g_cr_valid <= '0';
+ end if;
+ end if;
+ end process g_cr_reg;
+
+ g_zr_reg : process(clk)
+ begin
+ if rising_edge(clk) then
+ if zr_valid = '1' then
+ g_zr_valid <= '1';
+ g_zr <= zr;
+ elsif g_move = '1' then
+ g_zr_valid <= '0';
+ end if;
+ end if;
+ end process g_zr_reg;
+
+ t_pause <= (g_y_valid and y_valid) or (g_xl_valid and xl_valid) or (g_al_valid and al_valid) or
+ (g_bl_valid and bl_valid) or (g_cl_valid and cl_valid) or (g_zl_valid and tl_valid);
+
+ g_all_valid <= g_y_valid and g_xl_valid and g_al_valid and g_bl_valid and g_cl_valid and g_zl_valid and
+ g_xr_valid and g_ar_valid and g_br_valid and g_cr_valid and g_zr_valid;
+
+ rasterizer_l_1: entity work.rasterizer_l
+ generic map (
+ dontcare => dontcare,
+ width => width)
+ port map (
+ clk => clk,
+ pause => t_pause,
+ x0 => l_x0,
+ x1 => l_x1,
+ a0 => l_a0,
+ a1 => l_a1,
+ b0 => l_b0,
+ b1 => l_b1,
+ c0 => l_c0,
+ c1 => l_c1,
+ z0 => l_z0,
+ z1 => l_z1,
+ in_valid => l_in_valid,
+ in_ack => l_in_ack,
+ x => x,
+ a => a,
+ b => b,
+ c => c,
+ z => z,
+ x_valid => x_valid,
+ a_valid => a_valid,
+ b_valid => b_valid,
+ c_valid => c_valid,
+ z_valid => z_valid);
+
+end mixed;
diff --git a/src/rasterizer_l.vhd b/src/rasterizer_l.vhd
index 5fa906f..bf3869b 100644
--- a/src/rasterizer_l.vhd
+++ b/src/rasterizer_l.vhd
@@ -33,25 +33,27 @@ use IEEE.NUMERIC_STD.ALL;
entity rasterizer_l is
generic (
- dontcare : std_logic := '-');
+ dontcare : std_logic := '-';
+ width : integer := 12);
port (
clk : in std_logic;
+ pause : in std_logic;
- x0, x1 : in unsigned(15 downto 0);
- a0, a1 : in unsigned(15 downto 0);
- b0, b1 : in unsigned(15 downto 0);
- c0, c1 : in unsigned(15 downto 0);
- z0, z1 : in unsigned(15 downto 0);
+ x0, x1 : in unsigned(width-1 downto 0);
+ a0, a1 : in unsigned(width-1 downto 0);
+ b0, b1 : in unsigned(width-1 downto 0);
+ c0, c1 : in unsigned(width-1 downto 0);
+ z0, z1 : in unsigned(width-1 downto 0);
in_valid : in std_logic;
in_ack : out std_logic;
- x, a, b,c, z : out unsigned(15 downto 0);
+ x, a, b,c, z : out unsigned(width-1 downto 0);
x_valid, a_valid, b_valid, c_valid, z_valid : out std_logic);
end rasterizer_l;
architecture mixed of rasterizer_l is
- signal bh_x: unsigned(15 downto 0);
- signal bh_i, bh_i0, bh_i1 : unsigned(15 downto 0);
+ signal bh_x: unsigned(width-1 downto 0);
+ signal bh_i, bh_i0, bh_i1 : unsigned(width-1 downto 0);
signal bh_load_dx, bh_load_di, bh_init, bh_valid, bh_next_x, bh_done, bh_out_en : std_logic;
signal bh_ch, load_ch : unsigned(1 downto 0);
@@ -72,6 +74,7 @@ begin
dontcare => dontcare)
port map (
clk => clk,
+ pause => pause,
in_valid => in_valid,
bh_done => bh_done,
bh_load_dx => bh_load_dx,
@@ -87,9 +90,11 @@ begin
generic map (
channels => 4,
channels_ln2 => 2,
- preinc_x => false)
+ preinc_x => false,
+ width => width)
port map (
clk => clk,
+ pause => pause,
x0 => x0,
x1 => x1,
i0 => bh_i0,
diff --git a/src/rasterizer_l_fsm.vhd b/src/rasterizer_l_fsm.vhd
index 00c50e7..9bdb19b 100644
--- a/src/rasterizer_l_fsm.vhd
+++ b/src/rasterizer_l_fsm.vhd
@@ -36,6 +36,7 @@ entity rasterizer_l_fsm is
dontcare : std_logic := '-');
port (
clk : in std_logic;
+ pause : in std_logic;
in_valid : in std_logic;
bh_done : in std_logic;
@@ -59,7 +60,7 @@ begin
fsm : process(clk)
begin
- if rising_edge(clk) then
+ if rising_edge(clk) and pause = '0' then
bh_load_dx <= '0';
bh_load_di <= '0';
bh_init <= '0';
diff --git a/src/rasterizer_t.vhd b/src/rasterizer_t.vhd
new file mode 100644
index 0000000..228069c
--- /dev/null
+++ b/src/rasterizer_t.vhd
@@ -0,0 +1,303 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 03/22/2013 05:49:49 PM
+-- Design Name:
+-- Module Name: rasterizer_t - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool Versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity rasterizer_t is
+ generic (
+ dontcare : std_logic := '-';
+ width : integer := 12);
+ port (
+ clk : in std_logic;
+ pause : in std_logic;
+
+ x0, y0 : in unsigned(width-1 downto 0);
+ x1, y1 : in unsigned(width-1 downto 0);
+ x2, y2 : in unsigned(width-1 downto 0);
+
+ a0, a1, a2 : in unsigned(width-1 downto 0);
+ b0, b1, b2 : in unsigned(width-1 downto 0);
+ c0, c1, c2 : in unsigned(width-1 downto 0);
+ z0, z1, z2 : in unsigned(width-1 downto 0);
+ in_valid : in std_logic;
+ in_ack : out std_logic;
+
+ y : out unsigned(width-1 downto 0);
+ xl, al, bl, cl, zl : out unsigned(width-1 downto 0);
+ xr, ar, br, cr, zr : out unsigned(width-1 downto 0);
+ y_valid : out std_logic;
+ xl_valid, al_valid, bl_valid, cl_valid, zl_valid : out std_logic;
+ xr_valid, ar_valid, br_valid, cr_valid, zr_valid : out std_logic);
+end rasterizer_t;
+
+architecture mixed of rasterizer_t is
+ signal l_sel0, l_sel1, r_sel0, r_sel1 : unsigned(1 downto 0) := to_unsigned(0, 2);
+ signal load_ch : unsigned(2 downto 0) := to_unsigned(0, 3);
+ signal outl_end, outr_end : std_logic;
+ signal bhl_out_en, bhr_out_en : std_logic;
+
+ signal x0l, a0l, b0l, c0l, z0l : unsigned(width-1 downto 0);
+ signal x1l, a1l, b1l, c1l, z1l : unsigned(width-1 downto 0);
+ signal x0r, a0r, b0r, c0r, z0r : unsigned(width-1 downto 0);
+ signal x1r, a1r, b1r, c1r, z1r : unsigned(width-1 downto 0);
+
+ signal bhl_y0, bhl_y1, bhr_y0, bhr_y1 : unsigned(width-1 downto 0);
+ signal bhl_i0, bhl_i1, bhr_i0, bhr_i1 : unsigned(width-1 downto 0);
+
+ signal bhl_i, bhl_y, bhr_i, bhr_y : unsigned(width-1 downto 0);
+ signal bhl_load_dy, bhl_load_di, bhl_init, bhl_next_y, bhl_i_valid, bhl_done : std_logic;
+ signal bhr_load_dy, bhr_load_di, bhr_init, bhr_next_y, bhr_i_valid, bhr_done : std_logic;
+ signal bhl_ch, bhr_ch : unsigned(2 downto 0);
+begin
+
+ rasterizer_t_fsm_1: entity work.rasterizer_t_fsm
+ generic map (
+ dontcare => dontcare)
+ port map (
+ clk => clk,
+ pause => pause,
+ in_valid => in_valid,
+ in_ack => in_ack,
+ l_sel0 => l_sel0,
+ l_sel1 => l_sel1,
+ r_sel0 => r_sel0,
+ r_sel1 => r_sel1,
+ load_ch => load_ch,
+ outl_end => outl_end,
+ outr_end => outr_end,
+ bhl_out_en => bhl_out_en,
+ bhr_out_en => bhr_out_en,
+ bhl_load_dy => bhl_load_dy,
+ bhl_load_di => bhl_load_di,
+ bhl_init => bhl_init,
+ bhl_next_y => bhl_next_y,
+ bhl_i_valid => bhl_i_valid,
+ bhl_done => bhl_done,
+ bhr_load_dy => bhr_load_dy,
+ bhr_load_di => bhr_load_di,
+ bhr_init => bhr_init,
+ bhr_next_y => bhr_next_y,
+ bhr_i_valid => bhr_i_valid,
+ bhr_done => bhr_done);
+
+ bhl_y0 <= y0 when l_sel0 = 0 else
+ y1;-- when l_sel0 = 1 else (others => dontcare);
+
+ bhl_y1 <= y1 when l_sel1 = 1 else
+ y2;-- when l_sel1 = 2 else (others => dontcare);
+
+ bhr_y0 <= y0 when r_sel0 = 0 else
+ y1;-- when r_sel0 = 1 else (others => dontcare);
+
+ bhr_y1 <= y1 when r_sel1 = 1 else
+ y2;-- when r_sel1 = 2 else (others => dontcare);
+
+ x0l <= x0 when l_sel0 = 0 else
+ x1;
+ a0l <= a0 when l_sel0 = 0 else
+ a1;
+ b0l <= b0 when l_sel0 = 0 else
+ b1;
+ c0l <= c0 when l_sel0 = 0 else
+ c1;
+ z0l <= z0 when l_sel0 = 0 else
+ z1;
+ bhl_i0 <= x0l when load_ch = 0 else
+ a0l when load_ch = 1 else
+ b0l when load_ch = 2 else
+ c0l when load_ch = 3 else
+ z0l;-- when load_ch = 4 else (others => dontcare);
+
+ x1l <= x1 when l_sel1 = 1 else
+ x2;
+ a1l <= a1 when l_sel1 = 1 else
+ a2;
+ b1l <= b1 when l_sel1 = 1 else
+ b2;
+ c1l <= c1 when l_sel1 = 1 else
+ c2;
+ z1l <= z1 when l_sel1 = 1 else
+ z2;
+ bhl_i1 <= x1l when load_ch = 0 else
+ a1l when load_ch = 1 else
+ b1l when load_ch = 2 else
+ c1l when load_ch = 3 else
+ z1l;-- when load_ch = 4 else (others => dontcare);
+
+ x0r <= x0 when r_sel0 = 0 else
+ x1;
+ a0r <= a0 when r_sel0 = 0 else
+ a1;
+ b0r <= b0 when r_sel0 = 0 else
+ b1;
+ c0r <= c0 when r_sel0 = 0 else
+ c1;
+ z0r <= z0 when r_sel0 = 0 else
+ z1;
+ bhr_i0 <= x0r when load_ch = 0 else
+ a0r when load_ch = 1 else
+ b0r when load_ch = 2 else
+ c0r when load_ch = 3 else
+ z0r;-- when load_ch = 4 else (others => dontcare);
+
+ x1r <= x1 when r_sel1 = 1 else
+ x2;
+ a1r <= a1 when r_sel1 = 1 else
+ a2;
+ b1r <= b1 when r_sel1 = 1 else
+ b2;
+ c1r <= c1 when r_sel1 = 1 else
+ c2;
+ z1r <= z1 when r_sel1 = 1 else
+ z2;
+ bhr_i1 <= x1r when load_ch = 0 else
+ a1r when load_ch = 1 else
+ b1r when load_ch = 2 else
+ c1r when load_ch = 3 else
+ z1r;-- when load_ch = 4 else (others => dontcare);
+
+ bresenham_dp_l: entity work.bresenham_dp
+ generic map (
+ channels => 5,
+ channels_ln2 => 3,
+ preinc_x => false,
+ width => width)
+ port map (
+ clk => clk,
+ pause => pause,
+ x0 => bhl_y0,
+ x1 => bhl_y1,
+ i0 => bhl_i0,
+ i1 => bhl_i1,
+ load_dx => bhl_load_dy,
+ load_di => bhl_load_di,
+ init => bhl_init,
+ next_x => bhl_next_y,
+ i_valid => bhl_i_valid,
+ done => bhl_done,
+ i => bhl_i,
+ x => bhl_y,
+ ch => bhl_ch);
+
+ bresenham_dp_r: entity work.bresenham_dp
+ generic map (
+ channels => 5,
+ channels_ln2 => 3,
+ preinc_x => false,
+ width => width)
+ port map (
+ clk => clk,
+ pause => pause,
+ x0 => bhr_y0,
+ x1 => bhr_y1,
+ i0 => bhr_i0,
+ i1 => bhr_i1,
+ load_dx => bhr_load_dy,
+ load_di => bhr_load_di,
+ init => bhr_init,
+ next_x => bhr_next_y,
+ i_valid => bhr_i_valid,
+ done => bhr_done,
+ i => bhr_i,
+ x => bhr_y,
+ ch => bhr_ch);
+
+ y <= y1 when l_sel1 = 1 and outl_end = '1' else
+ y2 when l_sel1 = 2 and outl_end = '1' else
+ bhl_y;
+
+ xl <= x1 when l_sel1 = 1 and outl_end = '1' else
+ x2 when l_sel1 = 2 and outl_end = '1' else
+ bhl_i;
+ al <= a1 when l_sel1 = 1 and outl_end = '1' else
+ a2 when l_sel1 = 2 and outl_end = '1' else
+ bhl_i;
+ bl <= b1 when l_sel1 = 1 and outl_end = '1' else
+ b2 when l_sel1 = 2 and outl_end = '1' else
+ bhl_i;
+ cl <= c1 when l_sel1 = 1 and outl_end = '1' else
+ c2 when l_sel1 = 2 and outl_end = '1' else
+ bhl_i;
+ zl <= z1 when l_sel1 = 1 and outl_end = '1' else
+ z2 when l_sel1 = 2 and outl_end = '1' else
+ bhl_i;
+
+ xr <= x1 when r_sel1 = 1 and outr_end = '1' else
+ x2 when r_sel1 = 2 and outr_end = '1' else
+ bhr_i;
+ ar <= a1 when r_sel1 = 1 and outr_end = '1' else
+ a2 when r_sel1 = 2 and outr_end = '1' else
+ bhr_i;
+ br <= b1 when r_sel1 = 1 and outr_end = '1' else
+ b2 when r_sel1 = 2 and outr_end = '1' else
+ bhr_i;
+ cr <= c1 when r_sel1 = 1 and outr_end = '1' else
+ c2 when r_sel1 = 2 and outr_end = '1' else
+ bhr_i;
+ zr <= z1 when r_sel1 = 1 and outr_end = '1' else
+ z2 when r_sel1 = 2 and outr_end = '1' else
+ bhr_i;
+
+ y_valid <= outl_end or (bhl_next_y and bhl_out_en);
+
+ xl_valid <= '1' when outl_end = '1' else
+ bhl_i_valid and bhl_out_en when bhl_ch = 0 else
+ '0';
+ al_valid <= '1' when outl_end = '1' else
+ bhl_i_valid and bhl_out_en when bhl_ch = 1 else
+ '0';
+ bl_valid <= '1' when outl_end = '1' else
+ bhl_i_valid and bhl_out_en when bhl_ch = 2 else
+ '0';
+ cl_valid <= '1' when outl_end = '1' else
+ bhl_i_valid and bhl_out_en when bhl_ch = 3 else
+ '0';
+ zl_valid <= '1' when outl_end = '1' else
+ bhl_i_valid and bhl_out_en when bhl_ch = 4 else
+ '0';
+
+ xr_valid <= '1' when outr_end = '1' else
+ bhr_i_valid and bhr_out_en when bhr_ch = 0 else
+ '0';
+ ar_valid <= '1' when outr_end = '1' else
+ bhr_i_valid and bhr_out_en when bhr_ch = 1 else
+ '0';
+ br_valid <= '1' when outr_end = '1' else
+ bhr_i_valid and bhr_out_en when bhr_ch = 2 else
+ '0';
+ cr_valid <= '1' when outr_end = '1' else
+ bhr_i_valid and bhr_out_en when bhr_ch = 3 else
+ '0';
+ zr_valid <= '1' when outr_end = '1' else
+ bhr_i_valid and bhr_out_en when bhr_ch = 4 else
+ '0';
+
+end mixed;
diff --git a/src/rasterizer_t_fsm.vhd b/src/rasterizer_t_fsm.vhd
new file mode 100644
index 0000000..aebed8d
--- /dev/null
+++ b/src/rasterizer_t_fsm.vhd
@@ -0,0 +1,58 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 03/22/2013 05:49:49 PM
+-- Design Name:
+-- Module Name: rasterizer_t_fsm - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool Versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity rasterizer_t_fsm is
+ generic (
+ dontcare : std_logic := '-');
+ port (
+ clk : in std_logic;
+ pause : in std_logic;
+
+ in_valid : in std_logic;
+ in_ack : out std_logic;
+
+ l_sel0, l_sel1, r_sel0, r_sel1 : out unsigned(1 downto 0);
+ load_ch : out unsigned(2 downto 0);
+ outl_end, outr_end : out std_logic;
+ bhl_out_en, bhr_out_en : out std_logic;
+
+ bhl_load_dy, bhl_load_di, bhl_init : out std_logic;
+ bhl_next_y, bhl_i_valid, bhl_done : in std_logic;
+ bhr_load_dy, bhr_load_di, bhr_init : out std_logic;
+ bhr_next_y, bhr_i_valid, bhr_done : in std_logic);
+end rasterizer_t_fsm;
+
+architecture behavioral of rasterizer_t_fsm is
+begin
+
+end behavioral;
diff --git a/tb/rasterizer_l_tb.vhd b/tb/rasterizer_l_tb.vhd
index e1d857a..bce026e 100644
--- a/tb/rasterizer_l_tb.vhd
+++ b/tb/rasterizer_l_tb.vhd
@@ -6,7 +6,7 @@
-- Author : Matthias Blankertz
-- Company :
-- Created : 2013-03-26
--- Last update: 2013-03-26
+-- Last update: 2013-03-27
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
@@ -48,6 +48,8 @@ architecture testbench of rasterizer_l_tb is
signal x, a, b, c, z : unsigned(15 downto 0);
signal x_valid, a_valid, b_valid, c_valid, z_valid : std_logic;
+ signal sim_done : boolean := false;
+
begin -- architecture testbench
-- component instantiation
@@ -80,7 +82,8 @@ begin -- architecture testbench
z_valid => z_valid);
-- clock generation
- clk <= not clk after 10 ns;
+ clk <= not clk after 10 ns when not sim_done else
+ '0';
-- waveform generation
WaveGen_Proc: process
@@ -120,6 +123,13 @@ begin -- architecture testbench
in_valid <= '1';
wait until rising_edge(clk);
+ while in_ack = '0' loop
+ wait until rising_edge(clk);
+ end loop;
+ in_valid <= '0';
+ wait until rising_edge(clk);
+
+ sim_done <= true;
wait;
end process WaveGen_Proc;