From 95aa43b2d546961129eaa30215ffe5cefb365622 Mon Sep 17 00:00:00 2001 From: Matthias Blankertz Date: Thu, 28 Feb 2013 21:10:44 +0100 Subject: [PATCH] - Debugging wb_ddr_ctrl - Changed wb_ddr_ctrl_wb FIFO to 64 bit data width - Added write burst support to wb_ddr_ctrl_wb_sc --- Default.wcfg | 851 +++--- coregen/coregen.cgc | 3714 +++++++++++++-------------- coregen/wb_ddr_ctrl_wb_from_ddr.xco | 426 +-- coregen/wb_ddr_ctrl_wb_to_ddr.xco | 426 +-- src/wb_ddr_ctrl_wb.vhd | 48 +- src/wb_ddr_ctrl_wb_dc.vhd | 64 +- src/wb_ddr_ctrl_wb_dc_fsm.vhd | 63 +- src/wb_ddr_ctrl_wb_sc.vhd | 157 +- tb/wb_ddr_ctrl_tb.vhd | 47 +- 9 files changed, 2994 insertions(+), 2802 deletions(-) mode change 100755 => 100644 coregen/coregen.cgc mode change 100755 => 100644 coregen/wb_ddr_ctrl_wb_from_ddr.xco mode change 100755 => 100644 coregen/wb_ddr_ctrl_wb_to_ddr.xco diff --git a/Default.wcfg b/Default.wcfg index 4c550f7..4e02f6e 100755 --- a/Default.wcfg +++ b/Default.wcfg @@ -1,419 +1,432 @@ - - - - - - - - - - - - - - - - - - - - - - - - - toplevel - label - - ddr2_clock - ddr2_clock - - - ddr2_reset - ddr2_reset - - - ddr2_dq[15:0] - ddr2_dq[15:0] - HEXRADIX - - - ddr2_a[12:0] - ddr2_a[12:0] - - - ddr2_ba[1:0] - ddr2_ba[1:0] - - - ddr2_cke - ddr2_cke - - - ddr2_cs_n - ddr2_cs_n - - - ddr2_ras_n - ddr2_ras_n - - - ddr2_cas_n - ddr2_cas_n - - - ddr2_we_n - ddr2_we_n - - - ddr2_odt - ddr2_odt - - - ddr2_dm[1:0] - ddr2_dm[1:0] - - - rst_dqs_div_in - rst_dqs_div_in - - - rst_dqs_div_out - rst_dqs_div_out - - - ddr2_dqs[1:0] - ddr2_dqs[1:0] - - - ddr2_dqs_n[1:0] - ddr2_dqs_n[1:0] - - - ddr2_ck[0:0] - ddr2_ck[0:0] - - - ddr2_ck_n[0:0] - ddr2_ck_n[0:0] - - - clk_i - clk_i - - - rst_i - rst_i - - - dat_i[31:0] - dat_i[31:0] - - - dat_o[31:0] - dat_o[31:0] - - - ack_o - ack_o - - - adr_i[25:2] - adr_i[25:2] - - - cyc_i - cyc_i - - - sel_i[3:0] - sel_i[3:0] - - - stb_i - stb_i - - - we_i - we_i - - - cti_i[2:0] - cti_i[2:0] - - - bte_i[1:0] - bte_i[1:0] - - - - ddr_cd_inst - label - - ddr2_clk0 - ddr2_clk0 - - - ddr2_clk180 - ddr2_clk180 - - - ddr2_clk90 - ddr2_clk90 - - - ddr2_reset - ddr2_reset - - - ctrl_input_data[31:0] - ctrl_input_data[31:0] - HEXRADIX - - - ctrl_data_mask[3:0] - ctrl_data_mask[3:0] - - - ctrl_output_data[31:0] - ctrl_output_data[31:0] - HEXRADIX - - - ctrl_data_valid - ctrl_data_valid - - - ctrl_input_address[24:0] - ctrl_input_address[24:0] - HEXRADIX - - - ctrl_command_register[2:0] - ctrl_command_register[2:0] - - - ctrl_burst_done - ctrl_burst_done - - - ctrl_auto_ref_req - ctrl_auto_ref_req - - - ctrl_cmd_ack - ctrl_cmd_ack - - - ctrl_init_done - ctrl_init_done - - - ctrl_ar_done - ctrl_ar_done - - - din[31:0] - din[31:0] - HEXRADIX - - - dout[31:0] - dout[31:0] - HEXRADIX - - - adr[23:0] - adr[23:0] - HEXRADIX - - - we - we - - - be[3:0] - be[3:0] - - - fifo_to_sys_write - fifo_to_sys_write - - - fifo_from_sys_read - fifo_from_sys_read - - - fifo_to_sys_full - fifo_to_sys_full - - - fifo_from_sys_empty - fifo_from_sys_empty - - - ddr_address[23:0] - ddr_address[23:0] - HEXRADIX - - - ddr_address_en - ddr_address_en - - - ddr_dout[31:0] - ddr_dout[31:0] - HEXRADIX - - - ddr_dout_en - ddr_dout_en - - - ddr_dmask[3:0] - ddr_dmask[3:0] - - - ddr_dmask_rst - ddr_dmask_rst - - - ddr_dmask_en - ddr_dmask_en - - - ctrl_command_register_d[2:0] - ctrl_command_register_d[2:0] - - - ctrl_burst_done_d - ctrl_burst_done_d - - - ctrl_state - ctrl_state - - - burst_start_adr[12:0] - burst_start_adr[12:0] - - - fifo_pending - fifo_pending - - - fifo_from_sys_read_int - fifo_from_sys_read_int - - - fifo_from_sys_valid - fifo_from_sys_valid - - - - system_cd_inst - label - - clk_i - clk_i - - - rst_i - rst_i - - - dat_i[31:0] - dat_i[31:0] - HEXRADIX - - - dat_o[31:0] - dat_o[31:0] - HEXRADIX - - - ack_o - ack_o - - - adr_i[25:2] - adr_i[25:2] - HEXRADIX - - - cyc_i - cyc_i - - - sel_i[3:0] - sel_i[3:0] - - - stb_i - stb_i - - - we_i - we_i - - - cti_i[2:0] - cti_i[2:0] - - - bte_i[1:0] - bte_i[1:0] - - - ddr_din[31:0] - ddr_din[31:0] - HEXRADIX - - - ddr_dout[31:0] - ddr_dout[31:0] - HEXRADIX - - - ddr_adr[23:0] - ddr_adr[23:0] - HEXRADIX - - - ddr_we - ddr_we - - - ddr_be[3:0] - ddr_be[3:0] - - - fifo_to_ddr_write - fifo_to_ddr_write - - - fifo_from_ddr_read - fifo_from_ddr_read - - - fifo_to_ddr_full - fifo_to_ddr_full - - - fifo_from_ddr_empty - fifo_from_ddr_empty - - - state - state - - - fifo_from_ddr_read_int - fifo_from_ddr_read_int - - - fifo_from_ddr_valid - fifo_from_ddr_valid - - - + + + + + + + + + + + + + + + + + + + + + + + + + toplevel + label + + ddr2_clock + ddr2_clock + + + ddr2_reset + ddr2_reset + + + ddr2_dq[15:0] + ddr2_dq[15:0] + HEXRADIX + + + ddr2_a[12:0] + ddr2_a[12:0] + + + ddr2_ba[1:0] + ddr2_ba[1:0] + + + ddr2_cke + ddr2_cke + + + ddr2_cs_n + ddr2_cs_n + + + ddr2_ras_n + ddr2_ras_n + + + ddr2_cas_n + ddr2_cas_n + + + ddr2_we_n + ddr2_we_n + + + ddr2_odt + ddr2_odt + + + ddr2_dm[1:0] + ddr2_dm[1:0] + + + rst_dqs_div_in + rst_dqs_div_in + + + rst_dqs_div_out + rst_dqs_div_out + + + ddr2_dqs[1:0] + ddr2_dqs[1:0] + + + ddr2_dqs_n[1:0] + ddr2_dqs_n[1:0] + + + ddr2_ck[0:0] + ddr2_ck[0:0] + + + ddr2_ck_n[0:0] + ddr2_ck_n[0:0] + + + clk_i + clk_i + + + rst_i + rst_i + + + dat_i[31:0] + dat_i[31:0] + + + dat_o[31:0] + dat_o[31:0] + + + ack_o + ack_o + + + adr_i[25:2] + adr_i[25:2] + + + cyc_i + cyc_i + + + sel_i[3:0] + sel_i[3:0] + + + stb_i + stb_i + + + we_i + we_i + + + cti_i[2:0] + cti_i[2:0] + + + bte_i[1:0] + bte_i[1:0] + + + + ddr_cd_inst + label + + ddr2_clk0 + ddr2_clk0 + + + ddr2_clk180 + ddr2_clk180 + + + ddr2_clk90 + ddr2_clk90 + + + ddr2_reset + ddr2_reset + + + ctrl_input_data[31:0] + ctrl_input_data[31:0] + HEXRADIX + + + ctrl_data_mask[3:0] + ctrl_data_mask[3:0] + + + ctrl_output_data[31:0] + ctrl_output_data[31:0] + HEXRADIX + + + ctrl_data_valid + ctrl_data_valid + + + ctrl_input_address[24:0] + ctrl_input_address[24:0] + HEXRADIX + + + ctrl_command_register[2:0] + ctrl_command_register[2:0] + + + ctrl_burst_done + ctrl_burst_done + + + ctrl_auto_ref_req + ctrl_auto_ref_req + + + ctrl_cmd_ack + ctrl_cmd_ack + + + ctrl_init_done + ctrl_init_done + + + ctrl_ar_done + ctrl_ar_done + + + din[63:0] + din[63:0] + HEXRADIX + + + dout[63:0] + dout[63:0] + HEXRADIX + + + adr[22:0] + adr[22:0] + HEXRADIX + + + we + we + + + be[7:0] + be[7:0] + + + fifo_to_sys_write + fifo_to_sys_write + + + fifo_from_sys_read + fifo_from_sys_read + + + fifo_to_sys_full + fifo_to_sys_full + + + fifo_from_sys_empty + fifo_from_sys_empty + + + ddr_address[22:0] + ddr_address[22:0] + HEXRADIX + + + ddr_address_en + ddr_address_en + + + ddr_dout[31:0] + ddr_dout[31:0] + HEXRADIX + + + ddr_dout_en + ddr_dout_en + + + ddr_dout_high + ddr_dout_high + + + dout_low[31:0] + dout_low[31:0] + HEXRADIX + + + dout_low_en + dout_low_en + + + ddr_dmask[3:0] + ddr_dmask[3:0] + + + ddr_dmask_rst + ddr_dmask_rst + + + ddr_dmask_en + ddr_dmask_en + + + ctrl_command_register_d[2:0] + ctrl_command_register_d[2:0] + + + ctrl_burst_done_d + ctrl_burst_done_d + + + ctrl_state + ctrl_state + + + burst_start_adr[12:0] + burst_start_adr[12:0] + + + fifo_pending + fifo_pending + + + fifo_from_sys_read_int + fifo_from_sys_read_int + + + fifo_from_sys_valid + fifo_from_sys_valid + + + + system_cd_inst + label + + clk_i + clk_i + + + rst_i + rst_i + + + dat_i[31:0] + dat_i[31:0] + HEXRADIX + + + dat_o[31:0] + dat_o[31:0] + HEXRADIX + + + ack_o + ack_o + + + adr_i[25:2] + adr_i[25:2] + HEXRADIX + + + cyc_i + cyc_i + + + sel_i[3:0] + sel_i[3:0] + + + stb_i + stb_i + + + we_i + we_i + + + cti_i[2:0] + cti_i[2:0] + + + bte_i[1:0] + bte_i[1:0] + + + ddr_din[63:0] + ddr_din[63:0] + HEXRADIX + + + ddr_dout[63:0] + ddr_dout[63:0] + HEXRADIX + + + ddr_adr[22:0] + ddr_adr[22:0] + HEXRADIX + + + ddr_we + ddr_we + + + ddr_be[7:0] + ddr_be[7:0] + + + fifo_to_ddr_write + fifo_to_ddr_write + + + fifo_from_ddr_read + fifo_from_ddr_read + + + fifo_to_ddr_full + fifo_to_ddr_full + + + fifo_from_ddr_empty + fifo_from_ddr_empty + + + state + state + + + fifo_from_ddr_read_int + fifo_from_ddr_read_int + + + fifo_from_ddr_valid + fifo_from_ddr_valid + + + diff --git a/coregen/coregen.cgc b/coregen/coregen.cgc old mode 100755 new mode 100644 index e24e8c2..f5ba8ba --- a/coregen/coregen.cgc +++ b/coregen/coregen.cgc @@ -1,1864 +1,1850 @@ - - - xilinx.com - CoreGen - coregen - 1.0 - - - wb_ddr_ctrl_wb_from_ddr - - - wb_ddr_ctrl_wb_from_ddr - Independent_Clocks_Distributed_RAM - 2 - 2 - Native - Standard_FIFO - 32 - 16 - 32 - 16 - false - false - true - true - Asynchronous_Reset - 1 - true - 0 - false - false - false - Active_High - false - Active_High - false - Active_High - false - Active_High - false - false - false - false - 4 - false - 4 - false - 4 - true - 1 - 1 - No_Programmable_Full_Threshold - 13 - 12 - No_Programmable_Empty_Threshold - 2 - 3 - AXI4_Stream - Common_Clock - false - Slave_Interface_Clock_Enable - false - false - 4 - 32 - 64 - false - 1 - false - 1 - false - 1 - false - 1 - false - 1 - false - 64 - false - 8 - false - 4 - false - 4 - true - false - false - 4 - false - 4 - FIFO - Common_Clock_Block_RAM - Data_FIFO - false - false - false - 16 - false - No_Programmable_Full_Threshold - 1023 - No_Programmable_Empty_Threshold - 1022 - FIFO - Common_Clock_Block_RAM - Data_FIFO - false - false - false - 1024 - false - No_Programmable_Full_Threshold - 1023 - No_Programmable_Empty_Threshold - 1022 - FIFO - Common_Clock_Block_RAM - Data_FIFO - false - false - false - 16 - false - No_Programmable_Full_Threshold - 1023 - No_Programmable_Empty_Threshold - 1022 - FIFO - Common_Clock_Block_RAM - Data_FIFO - false - false - false - 16 - false - No_Programmable_Full_Threshold - 1023 - No_Programmable_Empty_Threshold - 1022 - FIFO - Common_Clock_Block_RAM - Data_FIFO - false - false - false - 1024 - false - No_Programmable_Full_Threshold - 1023 - No_Programmable_Empty_Threshold - 1022 - FIFO - Common_Clock_Block_RAM - Data_FIFO - false - false - false - 1024 - false - No_Programmable_Full_Threshold - 1023 - No_Programmable_Empty_Threshold - 1022 - Fully_Registered - Fully_Registered - Fully_Registered - Fully_Registered - Fully_Registered - Fully_Registered - false - Active_High - false - Active_High - false - false - false - false - false - 0 - 4 - 32 - 0 - 32 - spartan3 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 2 - 2 - 0 - 1 - 0 - 512x36 - 2 - 3 - 0 - 13 - 12 - 0 - 4 - 16 - 1 - 4 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 4 - 16 - 1 - 4 - 0 - 1 - 0 - 2 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 4 - 32 - 64 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 64 - 8 - 4 - 4 - 4 - 4 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 32 - 64 - 2 - 32 - 64 - 1 - 16 - 1024 - 16 - 16 - 1024 - 1024 - 4 - 10 - 4 - 4 - 10 - 10 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1023 - 1023 - 1023 - 1023 - 1023 - 1023 - 0 - 0 - 0 - 0 - 0 - 0 - 1022 - 1022 - 1022 - 1022 - 1022 - 1022 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - coregen - ./ - ./tmp/ - ./tmp/_cg/ - - - xc3s700an - spartan3a - fgg484 - -4 - - - BusFormatAngleBracketNotRipped - VHDL - true - Foundation_ISE - false - false - false - Ngc - false - - - Behavioral - VHDL - false - - - 2012-11-19+12:39 - - - - - apply_current_project_options_generator - - - customization_generator - - - model_parameter_resolution_generator - - - ip_xco_generator - - ./wb_ddr_ctrl_wb_from_ddr.xco - xco - Tue Feb 26 21:32:53 GMT 2013 - 0x54207A9F - generationID_706127423 - - - - associated_files_generator - - ./wb_ddr_ctrl_wb_from_ddr/doc/fifo_generator_v9_3_vinfo.html - ignore - unknown - Tue Dec 18 04:53:03 GMT 2012 - 0x9B56C5A6 - generationID_706127423 - - - ./wb_ddr_ctrl_wb_from_ddr/fifo_generator_v9_3_readme.txt - ignore - txt - Tue Dec 18 04:53:03 GMT 2012 - 0x4A0AA28D - generationID_706127423 - - - - ejava_generator - - ./wb_ddr_ctrl_wb_from_ddr/example_design/wb_ddr_ctrl_wb_from_ddr_exdes.ucf - ignore - ucf - Tue Feb 26 21:32:55 GMT 2013 - 0xB547BB7D - generationID_706127423 - - - ./wb_ddr_ctrl_wb_from_ddr/example_design/wb_ddr_ctrl_wb_from_ddr_exdes.vhd - ignore - vhdl - Tue Feb 26 21:32:55 GMT 2013 - 0x33BD3A8F - generationID_706127423 - - - ./wb_ddr_ctrl_wb_from_ddr/implement/implement.bat - ignore - unknown - Tue Feb 26 21:32:55 GMT 2013 - 0x192E0FAA - generationID_706127423 - - - ./wb_ddr_ctrl_wb_from_ddr/implement/implement.sh - ignore - unknown - Tue Feb 26 21:32:55 GMT 2013 - 0x20337A12 - generationID_706127423 - - - ./wb_ddr_ctrl_wb_from_ddr/implement/implement_synplify.bat - ignore - unknown - Tue Feb 26 21:32:55 GMT 2013 - 0xD919F981 - generationID_706127423 - - - ./wb_ddr_ctrl_wb_from_ddr/implement/implement_synplify.sh - ignore - unknown - Tue Feb 26 21:32:55 GMT 2013 - 0x43EA05DA - generationID_706127423 - - - ./wb_ddr_ctrl_wb_from_ddr/implement/planAhead_ise.bat - ignore - unknown - Tue Feb 26 21:32:56 GMT 2013 - 0xB958E3B7 - generationID_706127423 - - - ./wb_ddr_ctrl_wb_from_ddr/implement/planAhead_ise.sh - ignore - unknown - Tue Feb 26 21:32:56 GMT 2013 - 0xD7D40E1B - generationID_706127423 - - - ./wb_ddr_ctrl_wb_from_ddr/implement/planAhead_ise.tcl - ignore - tcl - Tue Feb 26 21:32:56 GMT 2013 - 0xA0C1ABF4 - generationID_706127423 - - - ./wb_ddr_ctrl_wb_from_ddr/implement/xst.prj - ignore - unknown - Tue Feb 26 21:32:55 GMT 2013 - 0x8573CCD5 - generationID_706127423 - - - ./wb_ddr_ctrl_wb_from_ddr/implement/xst.scr - ignore - unknown - Tue Feb 26 21:32:55 GMT 2013 - 0x236660A1 - generationID_706127423 - - - ./wb_ddr_ctrl_wb_from_ddr/simulation/functional/simulate_isim.bat - ignore - unknown - Tue Feb 26 21:32:56 GMT 2013 - 0xC83FD6FF - generationID_706127423 - - - ./wb_ddr_ctrl_wb_from_ddr/simulation/functional/simulate_isim.sh - ignore - unknown - Tue Feb 26 21:32:56 GMT 2013 - 0xFD3DE2A7 - generationID_706127423 - - - ./wb_ddr_ctrl_wb_from_ddr/simulation/functional/simulate_mti.bat - ignore - unknown - Tue Feb 26 21:32:55 GMT 2013 - 0x0C3CDB0C - generationID_706127423 - - - ./wb_ddr_ctrl_wb_from_ddr/simulation/functional/simulate_mti.do - ignore - unknown - Tue Feb 26 21:32:55 GMT 2013 - 0x444A03C1 - generationID_706127423 - - - ./wb_ddr_ctrl_wb_from_ddr/simulation/functional/simulate_mti.sh - ignore - unknown - Tue Feb 26 21:32:56 GMT 2013 - 0x5FDBD750 - generationID_706127423 - - - ./wb_ddr_ctrl_wb_from_ddr/simulation/functional/simulate_ncsim.bat - ignore - unknown - Tue Feb 26 21:32:56 GMT 2013 - 0x800BCE41 - generationID_706127423 - - - ./wb_ddr_ctrl_wb_from_ddr/simulation/functional/simulate_vcs.bat - ignore - unknown - Tue Feb 26 21:32:56 GMT 2013 - 0xBDC2FBED - generationID_706127423 - - - ./wb_ddr_ctrl_wb_from_ddr/simulation/functional/ucli_commands.key - ignore - unknown - Tue Feb 26 21:32:56 GMT 2013 - 0xF1BDBC27 - generationID_706127423 - - - ./wb_ddr_ctrl_wb_from_ddr/simulation/functional/vcs_session.tcl - ignore - tcl - Tue Feb 26 21:32:56 GMT 2013 - 0xC635497A - generationID_706127423 - - - ./wb_ddr_ctrl_wb_from_ddr/simulation/functional/wave_isim.tcl - ignore - tcl - Tue Feb 26 21:32:56 GMT 2013 - 0x7F420673 - generationID_706127423 - - - ./wb_ddr_ctrl_wb_from_ddr/simulation/functional/wave_mti.do - ignore - unknown - Tue Feb 26 21:32:56 GMT 2013 - 0xCA6B8089 - generationID_706127423 - - - ./wb_ddr_ctrl_wb_from_ddr/simulation/functional/wave_ncsim.sv - ignore - unknown - Tue Feb 26 21:32:56 GMT 2013 - 0x9EEEF980 - generationID_706127423 - - - ./wb_ddr_ctrl_wb_from_ddr/simulation/timing/simulate_isim.bat - ignore - unknown - Tue Feb 26 21:32:56 GMT 2013 - 0x52E8AF77 - generationID_706127423 - - - ./wb_ddr_ctrl_wb_from_ddr/simulation/timing/simulate_isim.sh - ignore - unknown - Tue Feb 26 21:32:56 GMT 2013 - 0xBEF17236 - generationID_706127423 - - - ./wb_ddr_ctrl_wb_from_ddr/simulation/timing/simulate_mti.bat - ignore - unknown - Tue Feb 26 21:32:56 GMT 2013 - 0x0C3CDB0C - generationID_706127423 - - - ./wb_ddr_ctrl_wb_from_ddr/simulation/timing/simulate_mti.do - ignore - unknown - Tue Feb 26 21:32:55 GMT 2013 - 0x38ACA586 - generationID_706127423 - - - ./wb_ddr_ctrl_wb_from_ddr/simulation/timing/simulate_mti.sh - ignore - unknown - Tue Feb 26 21:32:56 GMT 2013 - 0x5FDBD750 - generationID_706127423 - - - ./wb_ddr_ctrl_wb_from_ddr/simulation/timing/simulate_ncsim.bat - ignore - unknown - Tue Feb 26 21:32:56 GMT 2013 - 0xD155C416 - generationID_706127423 - - - ./wb_ddr_ctrl_wb_from_ddr/simulation/timing/simulate_vcs.bat - ignore - unknown - Tue Feb 26 21:32:56 GMT 2013 - 0x5E628E74 - generationID_706127423 - - - ./wb_ddr_ctrl_wb_from_ddr/simulation/timing/ucli_commands.key - ignore - unknown - Tue Feb 26 21:32:56 GMT 2013 - 0xF1BDBC27 - generationID_706127423 - - - ./wb_ddr_ctrl_wb_from_ddr/simulation/timing/vcs_session.tcl - ignore - tcl - Tue Feb 26 21:32:56 GMT 2013 - 0x33F51969 - generationID_706127423 - - - ./wb_ddr_ctrl_wb_from_ddr/simulation/timing/wave_isim.tcl - ignore - tcl - Tue Feb 26 21:32:56 GMT 2013 - 0x7F420673 - generationID_706127423 - - - ./wb_ddr_ctrl_wb_from_ddr/simulation/timing/wave_mti.do - ignore - unknown - Tue Feb 26 21:32:56 GMT 2013 - 0xCA6B8089 - generationID_706127423 - - - ./wb_ddr_ctrl_wb_from_ddr/simulation/timing/wave_ncsim.sv - ignore - unknown - Tue Feb 26 21:32:56 GMT 2013 - 0x9EEEF980 - generationID_706127423 - - - ./wb_ddr_ctrl_wb_from_ddr/simulation/wb_ddr_ctrl_wb_from_ddr_dgen.vhd - ignore - vhdl - Tue Feb 26 21:32:54 GMT 2013 - 0xDA66D5F8 - generationID_706127423 - - - ./wb_ddr_ctrl_wb_from_ddr/simulation/wb_ddr_ctrl_wb_from_ddr_dverif.vhd - ignore - vhdl - Tue Feb 26 21:32:54 GMT 2013 - 0x4C32772D - generationID_706127423 - - - ./wb_ddr_ctrl_wb_from_ddr/simulation/wb_ddr_ctrl_wb_from_ddr_pctrl.vhd - ignore - vhdl - Tue Feb 26 21:32:54 GMT 2013 - 0xFFBBEB74 - generationID_706127423 - - - ./wb_ddr_ctrl_wb_from_ddr/simulation/wb_ddr_ctrl_wb_from_ddr_pkg.vhd - ignore - vhdl - Tue Feb 26 21:32:54 GMT 2013 - 0xB21F08E3 - generationID_706127423 - - - ./wb_ddr_ctrl_wb_from_ddr/simulation/wb_ddr_ctrl_wb_from_ddr_rng.vhd - ignore - vhdl - Tue Feb 26 21:32:54 GMT 2013 - 0x299D093D - generationID_706127423 - - - ./wb_ddr_ctrl_wb_from_ddr/simulation/wb_ddr_ctrl_wb_from_ddr_synth.vhd - ignore - vhdl - Tue Feb 26 21:32:55 GMT 2013 - 0xCB7F7405 - generationID_706127423 - - - ./wb_ddr_ctrl_wb_from_ddr/simulation/wb_ddr_ctrl_wb_from_ddr_tb.vhd - ignore - vhdl - Tue Feb 26 21:32:55 GMT 2013 - 0x4EF48B27 - generationID_706127423 - - - - ngc_netlist_generator - - ./wb_ddr_ctrl_wb_from_ddr.ngc - ignore - ngc - Tue Feb 26 21:36:27 GMT 2013 - 0xE35932F1 - generationID_706127423 - - - - obfuscate_netlist_generator - - - padded_implementation_netlist_generator - - - instantiation_template_generator - - ./wb_ddr_ctrl_wb_from_ddr.vho - vho - Tue Feb 26 21:36:33 GMT 2013 - 0xB664F613 - generationID_706127423 - - - - structural_simulation_model_generator - - ./wb_ddr_ctrl_wb_from_ddr.vhd - ignore - vhdl - Tue Feb 26 21:36:34 GMT 2013 - 0x25718BAF - generationID_706127423 - - - - all_documents_generator - - ./wb_ddr_ctrl_wb_from_ddr/doc/fifo_generator_v9_3_readme.txt - ignore - txt - Tue Feb 26 21:36:33 GMT 2013 - 0x4A0AA28D - generationID_706127423 - - - ./wb_ddr_ctrl_wb_from_ddr/doc/fifo_generator_v9_3_vinfo.html - ignore - unknown - Tue Feb 26 21:36:33 GMT 2013 - 0x9B56C5A6 - generationID_706127423 - - - ./wb_ddr_ctrl_wb_from_ddr/doc/pg057-fifo-generator.pdf - ignore - pdf - Tue Feb 26 21:36:33 GMT 2013 - 0x1E7EB5CF - generationID_706127423 - - - - readme_documents_generator - - ./wb_ddr_ctrl_wb_from_ddr/doc/fifo_generator_v9_3_readme.txt - ignore - txt - Tue Feb 26 21:36:35 GMT 2013 - 0x4A0AA28D - generationID_706127423 - - - - asy_generator - - ./wb_ddr_ctrl_wb_from_ddr.asy - ignore - asy - Tue Feb 26 21:36:40 GMT 2013 - 0x2CD1BEF9 - generationID_706127423 - - - - xmdf_generator - - ./wb_ddr_ctrl_wb_from_ddr_xmdf.tcl - ignore - tclXmdf - tcl - Tue Feb 26 21:36:42 GMT 2013 - 0x746D5987 - generationID_706127423 - - - - synthesis_ise_generator - - ./wb_ddr_ctrl_wb_from_ddr.gise - ignore - gise - Tue Feb 26 21:36:56 GMT 2013 - 0x10DE92DE - generationID_706127423 - - - ./wb_ddr_ctrl_wb_from_ddr.xise - ignore - xise - Tue Feb 26 21:36:56 GMT 2013 - 0x4DDA291E - generationID_706127423 - - - - ise_generator - - ./wb_ddr_ctrl_wb_from_ddr.gise - ignore - gise - Tue Feb 26 21:37:03 GMT 2013 - 0x84F72A77 - generationID_706127423 - - - ./wb_ddr_ctrl_wb_from_ddr.xise - ignore - xise - Tue Feb 26 21:37:03 GMT 2013 - 0x6D68CEC8 - generationID_706127423 - - - - deliver_readme_generator - - - flist_generator - - ./wb_ddr_ctrl_wb_from_ddr_flist.txt - ignore - txtFlist - txt - Tue Feb 26 21:37:06 GMT 2013 - 0x4EDB508E - generationID_706127423 - - - - view_readme_generator - - - - - - wb_ddr_ctrl_wb_to_ddr - - - wb_ddr_ctrl_wb_to_ddr - Independent_Clocks_Distributed_RAM - 2 - 2 - Native - Standard_FIFO - 61 - 16 - 61 - 16 - false - false - true - true - Asynchronous_Reset - 1 - true - 0 - false - false - false - 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./wb_ddr_ctrl_wb_to_ddr/doc/fifo_generator_v9_3_vinfo.html - ignore - unknown - Tue Dec 18 04:53:03 GMT 2012 - 0x9B56C5A6 - generationID_152152107 - - - ./wb_ddr_ctrl_wb_to_ddr/fifo_generator_v9_3_readme.txt - ignore - txt - Tue Dec 18 04:53:03 GMT 2012 - 0x4A0AA28D - generationID_152152107 - - - - ejava_generator - - ./wb_ddr_ctrl_wb_to_ddr/example_design/wb_ddr_ctrl_wb_to_ddr_exdes.ucf - ignore - ucf - Tue Feb 26 21:38:23 GMT 2013 - 0xB547BB7D - generationID_152152107 - - - ./wb_ddr_ctrl_wb_to_ddr/example_design/wb_ddr_ctrl_wb_to_ddr_exdes.vhd - ignore - vhdl - Tue Feb 26 21:38:23 GMT 2013 - 0x8B38503C - generationID_152152107 - - - ./wb_ddr_ctrl_wb_to_ddr/implement/implement.bat - ignore - unknown - Tue Feb 26 21:38:23 GMT 2013 - 0x618F0487 - generationID_152152107 - - - ./wb_ddr_ctrl_wb_to_ddr/implement/implement.sh - ignore - unknown - Tue Feb 26 21:38:23 GMT 2013 - 0x41A64983 - generationID_152152107 - - - ./wb_ddr_ctrl_wb_to_ddr/implement/implement_synplify.bat - ignore - unknown - Tue Feb 26 21:38:23 GMT 2013 - 0xADC01C64 - generationID_152152107 - - - ./wb_ddr_ctrl_wb_to_ddr/implement/implement_synplify.sh - ignore - unknown - Tue Feb 26 21:38:23 GMT 2013 - 0x0D228AAD - generationID_152152107 - - - ./wb_ddr_ctrl_wb_to_ddr/implement/planAhead_ise.bat - ignore - unknown - Tue Feb 26 21:38:24 GMT 2013 - 0xB9AD0E43 - generationID_152152107 - - - ./wb_ddr_ctrl_wb_to_ddr/implement/planAhead_ise.sh - ignore - unknown - Tue Feb 26 21:38:24 GMT 2013 - 0xA94EC195 - generationID_152152107 - - - ./wb_ddr_ctrl_wb_to_ddr/implement/planAhead_ise.tcl - ignore - tcl - Tue Feb 26 21:38:24 GMT 2013 - 0xEB8CDEED - generationID_152152107 - - - ./wb_ddr_ctrl_wb_to_ddr/implement/xst.prj - ignore - unknown - Tue Feb 26 21:38:23 GMT 2013 - 0x8D205C47 - generationID_152152107 - - - ./wb_ddr_ctrl_wb_to_ddr/implement/xst.scr - ignore - unknown - Tue Feb 26 21:38:23 GMT 2013 - 0x22741F1E - generationID_152152107 - - - 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./wb_ddr_ctrl_wb_to_ddr/simulation/functional/simulate_vcs.bat - ignore - unknown - Tue Feb 26 21:38:24 GMT 2013 - 0x953B09D5 - generationID_152152107 - - - ./wb_ddr_ctrl_wb_to_ddr/simulation/functional/ucli_commands.key - ignore - unknown - Tue Feb 26 21:38:24 GMT 2013 - 0x32508805 - generationID_152152107 - - - ./wb_ddr_ctrl_wb_to_ddr/simulation/functional/vcs_session.tcl - ignore - tcl - Tue Feb 26 21:38:24 GMT 2013 - 0xC160568F - generationID_152152107 - - - ./wb_ddr_ctrl_wb_to_ddr/simulation/functional/wave_isim.tcl - ignore - tcl - Tue Feb 26 21:38:24 GMT 2013 - 0x546AFE24 - generationID_152152107 - - - ./wb_ddr_ctrl_wb_to_ddr/simulation/functional/wave_mti.do - ignore - unknown - Tue Feb 26 21:38:23 GMT 2013 - 0xE1168216 - generationID_152152107 - - - ./wb_ddr_ctrl_wb_to_ddr/simulation/functional/wave_ncsim.sv - ignore - unknown - Tue Feb 26 21:38:24 GMT 2013 - 0x7F129823 - generationID_152152107 - - - ./wb_ddr_ctrl_wb_to_ddr/simulation/timing/simulate_isim.bat - ignore - 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./wb_ddr_ctrl_wb_to_ddr/simulation/timing/ucli_commands.key - ignore - unknown - Tue Feb 26 21:38:24 GMT 2013 - 0x32508805 - generationID_152152107 - - - ./wb_ddr_ctrl_wb_to_ddr/simulation/timing/vcs_session.tcl - ignore - tcl - Tue Feb 26 21:38:24 GMT 2013 - 0xF61C74F1 - generationID_152152107 - - - ./wb_ddr_ctrl_wb_to_ddr/simulation/timing/wave_isim.tcl - ignore - tcl - Tue Feb 26 21:38:24 GMT 2013 - 0x546AFE24 - generationID_152152107 - - - ./wb_ddr_ctrl_wb_to_ddr/simulation/timing/wave_mti.do - ignore - unknown - Tue Feb 26 21:38:24 GMT 2013 - 0xE1168216 - generationID_152152107 - - - ./wb_ddr_ctrl_wb_to_ddr/simulation/timing/wave_ncsim.sv - ignore - unknown - Tue Feb 26 21:38:24 GMT 2013 - 0x7F129823 - generationID_152152107 - - - ./wb_ddr_ctrl_wb_to_ddr/simulation/wb_ddr_ctrl_wb_to_ddr_dgen.vhd - ignore - vhdl - Tue Feb 26 21:38:23 GMT 2013 - 0xA74A0617 - generationID_152152107 - - - ./wb_ddr_ctrl_wb_to_ddr/simulation/wb_ddr_ctrl_wb_to_ddr_dverif.vhd - ignore - vhdl - Tue Feb 26 21:38:23 GMT 2013 - 0xEB31B197 - generationID_152152107 - - - ./wb_ddr_ctrl_wb_to_ddr/simulation/wb_ddr_ctrl_wb_to_ddr_pctrl.vhd - ignore - vhdl - Tue Feb 26 21:38:23 GMT 2013 - 0x87DAAA4D - generationID_152152107 - - - ./wb_ddr_ctrl_wb_to_ddr/simulation/wb_ddr_ctrl_wb_to_ddr_pkg.vhd - ignore - vhdl - Tue Feb 26 21:38:23 GMT 2013 - 0x8583070E - generationID_152152107 - - - ./wb_ddr_ctrl_wb_to_ddr/simulation/wb_ddr_ctrl_wb_to_ddr_rng.vhd - ignore - vhdl - Tue Feb 26 21:38:23 GMT 2013 - 0x408CD90A - generationID_152152107 - - - ./wb_ddr_ctrl_wb_to_ddr/simulation/wb_ddr_ctrl_wb_to_ddr_synth.vhd - ignore - vhdl - Tue Feb 26 21:38:23 GMT 2013 - 0x4C3E60BD - generationID_152152107 - - - ./wb_ddr_ctrl_wb_to_ddr/simulation/wb_ddr_ctrl_wb_to_ddr_tb.vhd - ignore - vhdl - Tue Feb 26 21:38:23 GMT 2013 - 0x1908B094 - generationID_152152107 - - - - ngc_netlist_generator - - ./wb_ddr_ctrl_wb_to_ddr.ngc - ignore - ngc - Tue Feb 26 21:42:12 GMT 2013 - 0x8D735EEA - generationID_152152107 - - - - obfuscate_netlist_generator - - - padded_implementation_netlist_generator - - - instantiation_template_generator - - ./wb_ddr_ctrl_wb_to_ddr.vho - vho - Tue Feb 26 21:42:17 GMT 2013 - 0x0CC2998A - generationID_152152107 - - - - structural_simulation_model_generator - - ./wb_ddr_ctrl_wb_to_ddr.vhd - ignore - vhdl - Tue Feb 26 21:42:18 GMT 2013 - 0x427677AB - generationID_152152107 - - - - all_documents_generator - - ./wb_ddr_ctrl_wb_to_ddr/doc/fifo_generator_v9_3_readme.txt - ignore - txt - Tue Feb 26 21:42:17 GMT 2013 - 0x4A0AA28D - generationID_152152107 - - - ./wb_ddr_ctrl_wb_to_ddr/doc/fifo_generator_v9_3_vinfo.html - ignore - unknown - Tue Feb 26 21:42:17 GMT 2013 - 0x9B56C5A6 - generationID_152152107 - - - ./wb_ddr_ctrl_wb_to_ddr/doc/pg057-fifo-generator.pdf - ignore - pdf - Tue Feb 26 21:42:17 GMT 2013 - 0x1E7EB5CF - generationID_152152107 - - - - readme_documents_generator - - ./wb_ddr_ctrl_wb_to_ddr/doc/fifo_generator_v9_3_readme.txt - ignore - txt - Tue Feb 26 21:42:18 GMT 2013 - 0x4A0AA28D - generationID_152152107 - - - - asy_generator - - ./wb_ddr_ctrl_wb_to_ddr.asy - ignore - asy - Tue Feb 26 21:42:24 GMT 2013 - 0xA641A565 - generationID_152152107 - - - - xmdf_generator - - ./wb_ddr_ctrl_wb_to_ddr_xmdf.tcl - ignore - tclXmdf - tcl - Tue Feb 26 21:42:25 GMT 2013 - 0x373655CE - generationID_152152107 - - - - synthesis_ise_generator - - ./wb_ddr_ctrl_wb_to_ddr.gise - ignore - gise - Tue Feb 26 21:42:38 GMT 2013 - 0x92BF8E11 - generationID_152152107 - - - ./wb_ddr_ctrl_wb_to_ddr.xise - ignore - xise - Tue Feb 26 21:42:38 GMT 2013 - 0xC80C80EA - generationID_152152107 - - - - ise_generator - - ./wb_ddr_ctrl_wb_to_ddr.gise - ignore - gise - Tue Feb 26 21:42:46 GMT 2013 - 0xA30A284B - generationID_152152107 - - - ./wb_ddr_ctrl_wb_to_ddr.xise - ignore - xise - Tue Feb 26 21:42:46 GMT 2013 - 0xE70A410E - generationID_152152107 - - - - deliver_readme_generator - - - flist_generator - - ./wb_ddr_ctrl_wb_to_ddr_flist.txt - ignore - txtFlist - txt - Tue Feb 26 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generationID_1879581046 + + + ./wb_ddr_ctrl_wb_from_ddr/example_design/wb_ddr_ctrl_wb_from_ddr_exdes.vhd + ignore + vhdl + Thu Feb 28 16:17:28 GMT 2013 + 0xAE49BED3 + generationID_1879581046 + + + ./wb_ddr_ctrl_wb_from_ddr/example_design/wb_ddr_ctrl_wb_from_ddr_exdes.xdc + ignore + xdc + Thu Feb 28 16:17:28 GMT 2013 + 0x77D89547 + generationID_1879581046 + + + ./wb_ddr_ctrl_wb_from_ddr/implement/implement.bat + ignore + unknown + Thu Feb 28 16:17:28 GMT 2013 + 0x192E0FAA + generationID_1879581046 + + + ./wb_ddr_ctrl_wb_from_ddr/implement/implement.sh + ignore + unknown + Thu Feb 28 16:17:28 GMT 2013 + 0x20337A12 + generationID_1879581046 + + + ./wb_ddr_ctrl_wb_from_ddr/implement/implement_synplify.bat + ignore + unknown + Thu Feb 28 16:17:28 GMT 2013 + 0xD919F981 + generationID_1879581046 + + + ./wb_ddr_ctrl_wb_from_ddr/implement/implement_synplify.sh + ignore + unknown + Thu Feb 28 16:17:28 GMT 2013 + 0x43EA05DA + generationID_1879581046 + + + ./wb_ddr_ctrl_wb_from_ddr/implement/planAhead_ise.bat + ignore + unknown + Thu Feb 28 16:17:28 GMT 2013 + 0xB958E3B7 + generationID_1879581046 + + + ./wb_ddr_ctrl_wb_from_ddr/implement/planAhead_ise.sh + ignore + unknown + Thu Feb 28 16:17:28 GMT 2013 + 0xD7D40E1B + generationID_1879581046 + + + ./wb_ddr_ctrl_wb_from_ddr/implement/planAhead_ise.tcl + ignore + tcl + Thu Feb 28 16:17:28 GMT 2013 + 0xA0C1ABF4 + generationID_1879581046 + + + ./wb_ddr_ctrl_wb_from_ddr/implement/xst.prj + ignore + unknown + Thu Feb 28 16:17:28 GMT 2013 + 0x8573CCD5 + generationID_1879581046 + + + ./wb_ddr_ctrl_wb_from_ddr/implement/xst.scr + ignore + unknown + Thu Feb 28 16:17:28 GMT 2013 + 0x236660A1 + generationID_1879581046 + + + ./wb_ddr_ctrl_wb_from_ddr/simulation/functional/simulate_isim.bat + ignore + unknown + Thu Feb 28 16:17:28 GMT 2013 + 0xC83FD6FF + generationID_1879581046 + + + ./wb_ddr_ctrl_wb_from_ddr/simulation/functional/simulate_isim.sh + ignore + unknown + Thu Feb 28 16:17:28 GMT 2013 + 0xFD3DE2A7 + generationID_1879581046 + + + ./wb_ddr_ctrl_wb_from_ddr/simulation/functional/simulate_mti.bat + ignore + unknown + Thu Feb 28 16:17:28 GMT 2013 + 0x0C3CDB0C + generationID_1879581046 + + + ./wb_ddr_ctrl_wb_from_ddr/simulation/functional/simulate_mti.do + ignore + unknown + Thu Feb 28 16:17:28 GMT 2013 + 0x444A03C1 + generationID_1879581046 + + + ./wb_ddr_ctrl_wb_from_ddr/simulation/functional/simulate_mti.sh + ignore + unknown + Thu Feb 28 16:17:28 GMT 2013 + 0x5FDBD750 + generationID_1879581046 + + + ./wb_ddr_ctrl_wb_from_ddr/simulation/functional/simulate_ncsim.sh + ignore + unknown + Thu Feb 28 16:17:28 GMT 2013 + 0xD08A592E + generationID_1879581046 + + + ./wb_ddr_ctrl_wb_from_ddr/simulation/functional/simulate_vcs.sh + ignore + unknown + Thu Feb 28 16:17:28 GMT 2013 + 0x104A8D56 + generationID_1879581046 + + + ./wb_ddr_ctrl_wb_from_ddr/simulation/functional/ucli_commands.key + ignore + unknown + Thu Feb 28 16:17:28 GMT 2013 + 0xF1BDBC27 + generationID_1879581046 + + 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ignore + unknown + Thu Feb 28 16:17:28 GMT 2013 + 0x0C3CDB0C + generationID_1879581046 + + + ./wb_ddr_ctrl_wb_from_ddr/simulation/timing/simulate_mti.do + ignore + unknown + Thu Feb 28 16:17:28 GMT 2013 + 0x38ACA586 + generationID_1879581046 + + + ./wb_ddr_ctrl_wb_from_ddr/simulation/timing/simulate_mti.sh + ignore + unknown + Thu Feb 28 16:17:28 GMT 2013 + 0x5FDBD750 + generationID_1879581046 + + + ./wb_ddr_ctrl_wb_from_ddr/simulation/timing/simulate_ncsim.sh + ignore + unknown + Thu Feb 28 16:17:28 GMT 2013 + 0x6DB6900E + generationID_1879581046 + + + ./wb_ddr_ctrl_wb_from_ddr/simulation/timing/simulate_vcs.sh + ignore + unknown + Thu Feb 28 16:17:28 GMT 2013 + 0x9611AE74 + generationID_1879581046 + + + ./wb_ddr_ctrl_wb_from_ddr/simulation/timing/ucli_commands.key + ignore + unknown + Thu Feb 28 16:17:28 GMT 2013 + 0xF1BDBC27 + generationID_1879581046 + + + ./wb_ddr_ctrl_wb_from_ddr/simulation/timing/vcs_session.tcl + ignore + tcl + Thu Feb 28 16:17:28 GMT 2013 + 0x33F51969 + generationID_1879581046 + + + ./wb_ddr_ctrl_wb_from_ddr/simulation/timing/wave_isim.tcl + ignore + tcl + Thu Feb 28 16:17:28 GMT 2013 + 0x7F420673 + generationID_1879581046 + + + ./wb_ddr_ctrl_wb_from_ddr/simulation/timing/wave_mti.do + ignore + unknown + Thu Feb 28 16:17:28 GMT 2013 + 0xCA6B8089 + generationID_1879581046 + + + ./wb_ddr_ctrl_wb_from_ddr/simulation/timing/wave_ncsim.sv + ignore + unknown + Thu Feb 28 16:17:28 GMT 2013 + 0x9EEEF980 + generationID_1879581046 + + + ./wb_ddr_ctrl_wb_from_ddr/simulation/wb_ddr_ctrl_wb_from_ddr_dgen.vhd + ignore + vhdl + Thu Feb 28 16:17:28 GMT 2013 + 0xDA66D5F8 + generationID_1879581046 + + + ./wb_ddr_ctrl_wb_from_ddr/simulation/wb_ddr_ctrl_wb_from_ddr_dverif.vhd + ignore + vhdl + Thu Feb 28 16:17:28 GMT 2013 + 0x4C32772D + generationID_1879581046 + + + ./wb_ddr_ctrl_wb_from_ddr/simulation/wb_ddr_ctrl_wb_from_ddr_pctrl.vhd + ignore + vhdl + Thu Feb 28 16:17:28 GMT 2013 + 0xFFBBEB74 + generationID_1879581046 + + + ./wb_ddr_ctrl_wb_from_ddr/simulation/wb_ddr_ctrl_wb_from_ddr_pkg.vhd + ignore + vhdl + Thu Feb 28 16:17:28 GMT 2013 + 0xFBB69C5D + generationID_1879581046 + + + ./wb_ddr_ctrl_wb_from_ddr/simulation/wb_ddr_ctrl_wb_from_ddr_rng.vhd + ignore + vhdl + Thu Feb 28 16:17:28 GMT 2013 + 0x299D093D + generationID_1879581046 + + + ./wb_ddr_ctrl_wb_from_ddr/simulation/wb_ddr_ctrl_wb_from_ddr_synth.vhd + ignore + vhdl + Thu Feb 28 16:17:28 GMT 2013 + 0xDF2FC875 + generationID_1879581046 + + + ./wb_ddr_ctrl_wb_from_ddr/simulation/wb_ddr_ctrl_wb_from_ddr_tb.vhd + ignore + vhdl + Thu Feb 28 16:17:28 GMT 2013 + 0xD8614F37 + generationID_1879581046 + + + + ngc_netlist_generator + + ./wb_ddr_ctrl_wb_from_ddr.ngc + ngc + Thu Feb 28 16:19:15 GMT 2013 + 0x56235A14 + generationID_1879581046 + + + + obfuscate_netlist_generator + + + padded_implementation_netlist_generator + + + instantiation_template_generator + + ./wb_ddr_ctrl_wb_from_ddr.vho + vho + Thu Feb 28 16:19:15 GMT 2013 + 0x9FFEE5EE + generationID_1879581046 + + + + structural_simulation_model_generator + + ./wb_ddr_ctrl_wb_from_ddr.vhd + vhdl + Thu Feb 28 16:19:16 GMT 2013 + 0x1C032013 + generationID_1879581046 + + + + all_documents_generator + + ./wb_ddr_ctrl_wb_from_ddr/doc/fifo_generator_v9_3_readme.txt + ignore + txt + Thu Feb 28 16:19:16 GMT 2013 + 0xD700FB89 + generationID_1879581046 + + + ./wb_ddr_ctrl_wb_from_ddr/doc/fifo_generator_v9_3_vinfo.html + ignore + unknown + Thu Feb 28 16:19:16 GMT 2013 + 0x5A766369 + generationID_1879581046 + + + ./wb_ddr_ctrl_wb_from_ddr/doc/pg057-fifo-generator.pdf + ignore + pdf + Thu Feb 28 16:19:16 GMT 2013 + 0x90F23916 + generationID_1879581046 + + + + readme_documents_generator + + + asy_generator + + ./wb_ddr_ctrl_wb_from_ddr.asy + asy + Thu Feb 28 16:19:20 GMT 2013 + 0xCE751C06 + generationID_1879581046 + + + + xmdf_generator + + ./wb_ddr_ctrl_wb_from_ddr_xmdf.tcl + tclXmdf + tcl + Thu Feb 28 16:19:20 GMT 2013 + 0xC757466F + generationID_1879581046 + + + + synthesis_ise_generator + + ./wb_ddr_ctrl_wb_from_ddr.gise + ignore + gise + Thu Feb 28 16:19:25 GMT 2013 + 0x10DE92DE + generationID_1879581046 + + + ./wb_ddr_ctrl_wb_from_ddr.xise + ignore + xise + Thu Feb 28 16:19:25 GMT 2013 + 0x36CA1504 + generationID_1879581046 + + + + ise_generator + + ./wb_ddr_ctrl_wb_from_ddr.gise + ignore + gise + Thu Feb 28 16:19:31 GMT 2013 + 0x84F72A77 + generationID_1879581046 + + + ./wb_ddr_ctrl_wb_from_ddr.xise + ignore + xise + Thu Feb 28 16:19:31 GMT 2013 + 0x3F9D0432 + generationID_1879581046 + + + + deliver_readme_generator + + + flist_generator + + ./wb_ddr_ctrl_wb_from_ddr_flist.txt + ignore + txtFlist + txt + Thu Feb 28 16:19:31 GMT 2013 + 0x21E1AF65 + generationID_1879581046 + + + + view_readme_generator + + + + + + wb_ddr_ctrl_wb_to_ddr + + + wb_ddr_ctrl_wb_to_ddr + Independent_Clocks_Distributed_RAM + 2 + 2 + Native + Standard_FIFO + 96 + 16 + 96 + 16 + false + false + true + true + Asynchronous_Reset + 1 + true + 0 + false + false + false + Active_High + false + Active_High + false + Active_High + false + Active_High + false + false + false + false + 4 + false + 4 + false + 4 + true + 1 + 1 + No_Programmable_Full_Threshold + 13 + 12 + No_Programmable_Empty_Threshold + 2 + 3 + AXI4_Stream + Common_Clock + false + Slave_Interface_Clock_Enable + false + false + 4 + 32 + 64 + false + 1 + false + 1 + false + 1 + false + 1 + false + 1 + false + 64 + false + 8 + false + 4 + false + 4 + true + false + false + 4 + false + 4 + FIFO + Common_Clock_Block_RAM + Data_FIFO + false + false + false + 16 + false + No_Programmable_Full_Threshold + 1023 + No_Programmable_Empty_Threshold + 1022 + FIFO + Common_Clock_Block_RAM + Data_FIFO + false + false + false + 1024 + false + No_Programmable_Full_Threshold + 1023 + No_Programmable_Empty_Threshold + 1022 + FIFO + Common_Clock_Block_RAM + Data_FIFO + false + false + false + 16 + false + No_Programmable_Full_Threshold + 1023 + No_Programmable_Empty_Threshold + 1022 + FIFO + Common_Clock_Block_RAM + Data_FIFO + false + false + false + 16 + false + No_Programmable_Full_Threshold + 1023 + No_Programmable_Empty_Threshold + 1022 + FIFO + Common_Clock_Block_RAM + Data_FIFO + false + false + false + 1024 + false + No_Programmable_Full_Threshold + 1023 + No_Programmable_Empty_Threshold + 1022 + FIFO + Common_Clock_Block_RAM + Data_FIFO + false + false + false + 1024 + false + No_Programmable_Full_Threshold + 1023 + No_Programmable_Empty_Threshold + 1022 + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + false + Active_High + false + Active_High + false + false + false + false + false + 0 + 4 + 96 + 0 + 96 + spartan3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 0 + 1 + 0 + 512x72 + 2 + 3 + 0 + 13 + 12 + 0 + 4 + 16 + 1 + 4 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 4 + 16 + 1 + 4 + 0 + 1 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + 32 + 64 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 64 + 8 + 4 + 4 + 4 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 32 + 64 + 2 + 32 + 64 + 1 + 16 + 1024 + 16 + 16 + 1024 + 1024 + 4 + 10 + 4 + 4 + 10 + 10 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 0 + 0 + 0 + 0 + 0 + 0 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + coregen + ./ + ./tmp/ + ./tmp/_cg/ + + + xc3s700an + spartan3a + fgg484 + -4 + + + BusFormatAngleBracketNotRipped + VHDL + true + Foundation_ISE + false + false + false + Ngc + false + + + Behavioral + VHDL + false + + + 2012-07-25+18:11 + + + + + customization_generator + + + model_parameter_resolution_generator + + + ip_xco_generator + + ./wb_ddr_ctrl_wb_to_ddr.xco + xco + Thu Feb 28 16:33:31 GMT 2013 + 0x53466DD4 + generationID_706127423 + + + + associated_files_generator + + ./wb_ddr_ctrl_wb_to_ddr/doc/fifo_generator_v9_3_vinfo.html + ignore + unknown + Sat Oct 13 03:01:40 GMT 2012 + 0x5A766369 + generationID_706127423 + + + ./wb_ddr_ctrl_wb_to_ddr/fifo_generator_v9_3_readme.txt + ignore + txt + Sat Oct 13 03:01:40 GMT 2012 + 0xD700FB89 + generationID_706127423 + + + + ejava_generator + + ./wb_ddr_ctrl_wb_to_ddr/example_design/wb_ddr_ctrl_wb_to_ddr_exdes.ucf + ignore + ucf + Thu Feb 28 16:33:32 GMT 2013 + 0xB547BB7D + generationID_706127423 + + + ./wb_ddr_ctrl_wb_to_ddr/example_design/wb_ddr_ctrl_wb_to_ddr_exdes.vhd + ignore + vhdl + Thu Feb 28 16:33:32 GMT 2013 + 0x12B20726 + generationID_706127423 + + + ./wb_ddr_ctrl_wb_to_ddr/example_design/wb_ddr_ctrl_wb_to_ddr_exdes.xdc + ignore + xdc + Thu Feb 28 16:33:32 GMT 2013 + 0x77D89547 + generationID_706127423 + + + ./wb_ddr_ctrl_wb_to_ddr/implement/implement.bat + ignore + unknown + Thu Feb 28 16:33:32 GMT 2013 + 0x618F0487 + generationID_706127423 + + + ./wb_ddr_ctrl_wb_to_ddr/implement/implement.sh + ignore + unknown + Thu Feb 28 16:33:32 GMT 2013 + 0x41A64983 + generationID_706127423 + + + ./wb_ddr_ctrl_wb_to_ddr/implement/implement_synplify.bat + ignore + unknown + Thu Feb 28 16:33:32 GMT 2013 + 0xADC01C64 + generationID_706127423 + + + ./wb_ddr_ctrl_wb_to_ddr/implement/implement_synplify.sh + ignore + unknown + Thu Feb 28 16:33:32 GMT 2013 + 0x0D228AAD + generationID_706127423 + + + ./wb_ddr_ctrl_wb_to_ddr/implement/planAhead_ise.bat + ignore + unknown + Thu Feb 28 16:33:32 GMT 2013 + 0xB9AD0E43 + generationID_706127423 + + + ./wb_ddr_ctrl_wb_to_ddr/implement/planAhead_ise.sh + ignore + unknown + Thu Feb 28 16:33:32 GMT 2013 + 0xA94EC195 + generationID_706127423 + + + ./wb_ddr_ctrl_wb_to_ddr/implement/planAhead_ise.tcl + ignore + tcl + Thu Feb 28 16:33:32 GMT 2013 + 0xEB8CDEED + generationID_706127423 + + + ./wb_ddr_ctrl_wb_to_ddr/implement/xst.prj + ignore + unknown + Thu Feb 28 16:33:32 GMT 2013 + 0x8D205C47 + generationID_706127423 + + + ./wb_ddr_ctrl_wb_to_ddr/implement/xst.scr + ignore + unknown + Thu Feb 28 16:33:32 GMT 2013 + 0x22741F1E + generationID_706127423 + + + ./wb_ddr_ctrl_wb_to_ddr/simulation/functional/simulate_isim.bat + ignore + unknown + Thu Feb 28 16:33:32 GMT 2013 + 0x1F7F07BB + generationID_706127423 + + + ./wb_ddr_ctrl_wb_to_ddr/simulation/functional/simulate_isim.sh + ignore + unknown + Thu Feb 28 16:33:32 GMT 2013 + 0x38E533B0 + generationID_706127423 + + + ./wb_ddr_ctrl_wb_to_ddr/simulation/functional/simulate_mti.bat + ignore + unknown + Thu Feb 28 16:33:32 GMT 2013 + 0x0C3CDB0C + generationID_706127423 + + + ./wb_ddr_ctrl_wb_to_ddr/simulation/functional/simulate_mti.do + ignore + unknown + Thu Feb 28 16:33:32 GMT 2013 + 0x98C3788B + generationID_706127423 + + + ./wb_ddr_ctrl_wb_to_ddr/simulation/functional/simulate_mti.sh + ignore + unknown + Thu Feb 28 16:33:32 GMT 2013 + 0x5FDBD750 + generationID_706127423 + + + ./wb_ddr_ctrl_wb_to_ddr/simulation/functional/simulate_ncsim.sh + ignore + unknown + Thu Feb 28 16:33:32 GMT 2013 + 0x27AF2605 + generationID_706127423 + + + ./wb_ddr_ctrl_wb_to_ddr/simulation/functional/simulate_vcs.sh + ignore + unknown + Thu Feb 28 16:33:32 GMT 2013 + 0xC26A70F5 + generationID_706127423 + + + ./wb_ddr_ctrl_wb_to_ddr/simulation/functional/ucli_commands.key + ignore + unknown + Thu Feb 28 16:33:32 GMT 2013 + 0x32508805 + generationID_706127423 + + + ./wb_ddr_ctrl_wb_to_ddr/simulation/functional/vcs_session.tcl + ignore + tcl + Thu Feb 28 16:33:32 GMT 2013 + 0xC160568F + generationID_706127423 + + + ./wb_ddr_ctrl_wb_to_ddr/simulation/functional/wave_isim.tcl + ignore + tcl + Thu Feb 28 16:33:32 GMT 2013 + 0x546AFE24 + generationID_706127423 + + + ./wb_ddr_ctrl_wb_to_ddr/simulation/functional/wave_mti.do + ignore + unknown + Thu Feb 28 16:33:32 GMT 2013 + 0xE1168216 + generationID_706127423 + + + ./wb_ddr_ctrl_wb_to_ddr/simulation/functional/wave_ncsim.sv + ignore + unknown + Thu Feb 28 16:33:32 GMT 2013 + 0x7F129823 + generationID_706127423 + + + ./wb_ddr_ctrl_wb_to_ddr/simulation/timing/simulate_isim.bat + ignore + unknown + Thu Feb 28 16:33:32 GMT 2013 + 0x0E99F9F4 + generationID_706127423 + + + ./wb_ddr_ctrl_wb_to_ddr/simulation/timing/simulate_isim.sh + ignore + unknown + Thu Feb 28 16:33:32 GMT 2013 + 0xC342CFF2 + generationID_706127423 + + + ./wb_ddr_ctrl_wb_to_ddr/simulation/timing/simulate_mti.bat + ignore + unknown + Thu Feb 28 16:33:32 GMT 2013 + 0x0C3CDB0C + generationID_706127423 + + + ./wb_ddr_ctrl_wb_to_ddr/simulation/timing/simulate_mti.do + ignore + unknown + Thu Feb 28 16:33:32 GMT 2013 + 0xD9164D7B + generationID_706127423 + + + ./wb_ddr_ctrl_wb_to_ddr/simulation/timing/simulate_mti.sh + ignore + unknown + Thu Feb 28 16:33:32 GMT 2013 + 0x5FDBD750 + generationID_706127423 + + + ./wb_ddr_ctrl_wb_to_ddr/simulation/timing/simulate_ncsim.sh + ignore + unknown + Thu Feb 28 16:33:32 GMT 2013 + 0x885E0CCA + generationID_706127423 + + + ./wb_ddr_ctrl_wb_to_ddr/simulation/timing/simulate_vcs.sh + ignore + unknown + Thu Feb 28 16:33:32 GMT 2013 + 0x0AC98A7E + generationID_706127423 + + + ./wb_ddr_ctrl_wb_to_ddr/simulation/timing/ucli_commands.key + ignore + unknown + Thu Feb 28 16:33:32 GMT 2013 + 0x32508805 + generationID_706127423 + + + ./wb_ddr_ctrl_wb_to_ddr/simulation/timing/vcs_session.tcl + ignore + tcl + Thu Feb 28 16:33:32 GMT 2013 + 0xF61C74F1 + generationID_706127423 + + + ./wb_ddr_ctrl_wb_to_ddr/simulation/timing/wave_isim.tcl + ignore + tcl + Thu Feb 28 16:33:32 GMT 2013 + 0x546AFE24 + generationID_706127423 + + + ./wb_ddr_ctrl_wb_to_ddr/simulation/timing/wave_mti.do + ignore + unknown + Thu Feb 28 16:33:32 GMT 2013 + 0xE1168216 + generationID_706127423 + + + ./wb_ddr_ctrl_wb_to_ddr/simulation/timing/wave_ncsim.sv + ignore + unknown + Thu Feb 28 16:33:32 GMT 2013 + 0x7F129823 + generationID_706127423 + + + ./wb_ddr_ctrl_wb_to_ddr/simulation/wb_ddr_ctrl_wb_to_ddr_dgen.vhd + ignore + vhdl + Thu Feb 28 16:33:32 GMT 2013 + 0x619FAB48 + generationID_706127423 + + + ./wb_ddr_ctrl_wb_to_ddr/simulation/wb_ddr_ctrl_wb_to_ddr_dverif.vhd + ignore + vhdl + Thu Feb 28 16:33:32 GMT 2013 + 0xEB31B197 + generationID_706127423 + + + ./wb_ddr_ctrl_wb_to_ddr/simulation/wb_ddr_ctrl_wb_to_ddr_pctrl.vhd + ignore + vhdl + Thu Feb 28 16:33:32 GMT 2013 + 0xC7914329 + generationID_706127423 + + + ./wb_ddr_ctrl_wb_to_ddr/simulation/wb_ddr_ctrl_wb_to_ddr_pkg.vhd + ignore + vhdl + Thu Feb 28 16:33:32 GMT 2013 + 0x6D7C979C + generationID_706127423 + + + ./wb_ddr_ctrl_wb_to_ddr/simulation/wb_ddr_ctrl_wb_to_ddr_rng.vhd + ignore + vhdl + Thu Feb 28 16:33:32 GMT 2013 + 0x408CD90A + generationID_706127423 + + + ./wb_ddr_ctrl_wb_to_ddr/simulation/wb_ddr_ctrl_wb_to_ddr_synth.vhd + ignore + vhdl + Thu Feb 28 16:33:32 GMT 2013 + 0x6BFB0E43 + generationID_706127423 + + + ./wb_ddr_ctrl_wb_to_ddr/simulation/wb_ddr_ctrl_wb_to_ddr_tb.vhd + ignore + vhdl + Thu Feb 28 16:33:32 GMT 2013 + 0x2FFEFA4B + generationID_706127423 + + + + ngc_netlist_generator + + ./wb_ddr_ctrl_wb_to_ddr.ngc + ngc + Thu Feb 28 16:35:19 GMT 2013 + 0xB83139EA + generationID_706127423 + + + + obfuscate_netlist_generator + + + padded_implementation_netlist_generator + + + instantiation_template_generator + + ./wb_ddr_ctrl_wb_to_ddr.vho + vho + Thu Feb 28 16:35:20 GMT 2013 + 0xF6240833 + generationID_706127423 + + + + structural_simulation_model_generator + + ./wb_ddr_ctrl_wb_to_ddr.vhd + vhdl + Thu Feb 28 16:35:20 GMT 2013 + 0x794C0CCB + generationID_706127423 + + + + all_documents_generator + + ./wb_ddr_ctrl_wb_to_ddr/doc/fifo_generator_v9_3_readme.txt + ignore + txt + Thu Feb 28 16:35:20 GMT 2013 + 0xD700FB89 + generationID_706127423 + + + ./wb_ddr_ctrl_wb_to_ddr/doc/fifo_generator_v9_3_vinfo.html + ignore + unknown + Thu Feb 28 16:35:20 GMT 2013 + 0x5A766369 + generationID_706127423 + + + ./wb_ddr_ctrl_wb_to_ddr/doc/pg057-fifo-generator.pdf + ignore + pdf + Thu Feb 28 16:35:20 GMT 2013 + 0x90F23916 + generationID_706127423 + + + + readme_documents_generator + + + asy_generator + + ./wb_ddr_ctrl_wb_to_ddr.asy + asy + Thu Feb 28 16:35:24 GMT 2013 + 0x86F96EB1 + generationID_706127423 + + + + xmdf_generator + + ./wb_ddr_ctrl_wb_to_ddr_xmdf.tcl + tclXmdf + tcl + Thu Feb 28 16:35:24 GMT 2013 + 0x8A876748 + generationID_706127423 + + + + synthesis_ise_generator + + ./wb_ddr_ctrl_wb_to_ddr.gise + ignore + gise + Thu Feb 28 16:35:30 GMT 2013 + 0x92BF8E11 + generationID_706127423 + + + ./wb_ddr_ctrl_wb_to_ddr.xise + ignore + xise + Thu Feb 28 16:35:30 GMT 2013 + 0x7F741210 + generationID_706127423 + + + + ise_generator + + ./wb_ddr_ctrl_wb_to_ddr.gise + ignore + gise + Thu Feb 28 16:35:35 GMT 2013 + 0xA30A284B + generationID_706127423 + + + ./wb_ddr_ctrl_wb_to_ddr.xise + ignore + xise + Thu Feb 28 16:35:35 GMT 2013 + 0xDBD30B52 + generationID_706127423 + + + + deliver_readme_generator + + + flist_generator + + ./wb_ddr_ctrl_wb_to_ddr_flist.txt + ignore + txtFlist + txt + Thu Feb 28 16:35:35 GMT 2013 + 0xB430E71D + generationID_706127423 + + + + view_readme_generator + + + + + + + + + coregen + ./ + ./tmp/ + ./tmp/_cg/ + + + xc3s700an + spartan3a + fgg484 + -4 + + + BusFormatAngleBracketNotRipped + VHDL + true + Foundation_ISE + false + false + false + Ngc + false + + + Behavioral + VHDL + false + + + + + diff --git a/coregen/wb_ddr_ctrl_wb_from_ddr.xco b/coregen/wb_ddr_ctrl_wb_from_ddr.xco old mode 100755 new mode 100644 index aea6868..53d704d --- a/coregen/wb_ddr_ctrl_wb_from_ddr.xco +++ b/coregen/wb_ddr_ctrl_wb_from_ddr.xco @@ -1,213 +1,213 @@ -############################################################## -# -# Xilinx Core Generator version 14.4 -# Date: Tue Feb 26 21:32:50 2013 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# Generated from component: xilinx.com:ip:fifo_generator:9.3 -# -############################################################## -# -# BEGIN Project Options -SET addpads = false -SET asysymbol = true -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = VHDL -SET device = xc3s700an -SET devicefamily = spartan3a -SET flowvendor = Foundation_ISE -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = fgg484 -SET removerpms = false -SET simulationfiles = Behavioral -SET speedgrade = -4 -SET verilogsim = false -SET vhdlsim = true -# END Project Options -# BEGIN Select -SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3 -# END Select -# BEGIN Parameters -CSET add_ngc_constraint_axi=false -CSET almost_empty_flag=false -CSET almost_full_flag=false -CSET aruser_width=1 -CSET awuser_width=1 -CSET axi_address_width=32 -CSET axi_data_width=64 -CSET axi_type=AXI4_Stream -CSET axis_type=FIFO -CSET buser_width=1 -CSET clock_enable_type=Slave_Interface_Clock_Enable -CSET clock_type_axi=Common_Clock -CSET component_name=wb_ddr_ctrl_wb_from_ddr -CSET data_count=false -CSET data_count_width=4 -CSET disable_timing_violations=true -CSET disable_timing_violations_axi=false -CSET dout_reset_value=0 -CSET empty_threshold_assert_value=2 -CSET empty_threshold_assert_value_axis=1022 -CSET empty_threshold_assert_value_rach=1022 -CSET empty_threshold_assert_value_rdch=1022 -CSET empty_threshold_assert_value_wach=1022 -CSET empty_threshold_assert_value_wdch=1022 -CSET empty_threshold_assert_value_wrch=1022 -CSET empty_threshold_negate_value=3 -CSET enable_aruser=false -CSET enable_awuser=false -CSET enable_buser=false -CSET enable_common_overflow=false -CSET enable_common_underflow=false -CSET enable_data_counts_axis=false -CSET enable_data_counts_rach=false -CSET enable_data_counts_rdch=false -CSET enable_data_counts_wach=false -CSET enable_data_counts_wdch=false -CSET enable_data_counts_wrch=false -CSET enable_ecc=false -CSET enable_ecc_axis=false -CSET enable_ecc_rach=false -CSET enable_ecc_rdch=false -CSET enable_ecc_wach=false -CSET enable_ecc_wdch=false -CSET enable_ecc_wrch=false -CSET enable_read_channel=false -CSET enable_read_pointer_increment_by2=false -CSET enable_reset_synchronization=true -CSET enable_ruser=false -CSET enable_tdata=false -CSET enable_tdest=false -CSET enable_tid=false -CSET enable_tkeep=false -CSET enable_tlast=false -CSET enable_tready=true -CSET enable_tstrobe=false -CSET enable_tuser=false -CSET enable_write_channel=false -CSET enable_wuser=false -CSET fifo_application_type_axis=Data_FIFO -CSET fifo_application_type_rach=Data_FIFO -CSET fifo_application_type_rdch=Data_FIFO -CSET fifo_application_type_wach=Data_FIFO -CSET fifo_application_type_wdch=Data_FIFO -CSET fifo_application_type_wrch=Data_FIFO -CSET fifo_implementation=Independent_Clocks_Distributed_RAM -CSET fifo_implementation_axis=Common_Clock_Block_RAM -CSET fifo_implementation_rach=Common_Clock_Block_RAM -CSET fifo_implementation_rdch=Common_Clock_Block_RAM -CSET fifo_implementation_wach=Common_Clock_Block_RAM -CSET fifo_implementation_wdch=Common_Clock_Block_RAM -CSET fifo_implementation_wrch=Common_Clock_Block_RAM -CSET full_flags_reset_value=1 -CSET full_threshold_assert_value=13 -CSET full_threshold_assert_value_axis=1023 -CSET full_threshold_assert_value_rach=1023 -CSET full_threshold_assert_value_rdch=1023 -CSET full_threshold_assert_value_wach=1023 -CSET full_threshold_assert_value_wdch=1023 -CSET full_threshold_assert_value_wrch=1023 -CSET full_threshold_negate_value=12 -CSET id_width=4 -CSET inject_dbit_error=false -CSET inject_dbit_error_axis=false -CSET inject_dbit_error_rach=false -CSET inject_dbit_error_rdch=false -CSET inject_dbit_error_wach=false -CSET inject_dbit_error_wdch=false -CSET inject_dbit_error_wrch=false -CSET inject_sbit_error=false -CSET inject_sbit_error_axis=false -CSET inject_sbit_error_rach=false -CSET inject_sbit_error_rdch=false -CSET inject_sbit_error_wach=false -CSET inject_sbit_error_wdch=false -CSET inject_sbit_error_wrch=false -CSET input_data_width=32 -CSET input_depth=16 -CSET input_depth_axis=1024 -CSET input_depth_rach=16 -CSET input_depth_rdch=1024 -CSET input_depth_wach=16 -CSET input_depth_wdch=1024 -CSET input_depth_wrch=16 -CSET interface_type=Native -CSET output_data_width=32 -CSET output_depth=16 -CSET overflow_flag=false -CSET overflow_flag_axi=false -CSET overflow_sense=Active_High -CSET overflow_sense_axi=Active_High -CSET performance_options=Standard_FIFO -CSET programmable_empty_type=No_Programmable_Empty_Threshold -CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold -CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold -CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold -CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold -CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold -CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold -CSET programmable_full_type=No_Programmable_Full_Threshold -CSET programmable_full_type_axis=No_Programmable_Full_Threshold -CSET programmable_full_type_rach=No_Programmable_Full_Threshold -CSET programmable_full_type_rdch=No_Programmable_Full_Threshold -CSET programmable_full_type_wach=No_Programmable_Full_Threshold -CSET programmable_full_type_wdch=No_Programmable_Full_Threshold -CSET programmable_full_type_wrch=No_Programmable_Full_Threshold -CSET rach_type=FIFO -CSET rdch_type=FIFO -CSET read_clock_frequency=1 -CSET read_data_count=false -CSET read_data_count_width=4 -CSET register_slice_mode_axis=Fully_Registered -CSET register_slice_mode_rach=Fully_Registered -CSET register_slice_mode_rdch=Fully_Registered -CSET register_slice_mode_wach=Fully_Registered -CSET register_slice_mode_wdch=Fully_Registered -CSET register_slice_mode_wrch=Fully_Registered -CSET reset_pin=true -CSET reset_type=Asynchronous_Reset -CSET ruser_width=1 -CSET synchronization_stages=2 -CSET synchronization_stages_axi=2 -CSET tdata_width=64 -CSET tdest_width=4 -CSET tid_width=8 -CSET tkeep_width=4 -CSET tstrb_width=4 -CSET tuser_width=4 -CSET underflow_flag=false -CSET underflow_flag_axi=false -CSET underflow_sense=Active_High -CSET underflow_sense_axi=Active_High -CSET use_clock_enable=false -CSET use_dout_reset=true -CSET use_embedded_registers=false -CSET use_extra_logic=false -CSET valid_flag=false -CSET valid_sense=Active_High -CSET wach_type=FIFO -CSET wdch_type=FIFO -CSET wrch_type=FIFO -CSET write_acknowledge_flag=false -CSET write_acknowledge_sense=Active_High -CSET write_clock_frequency=1 -CSET write_data_count=false -CSET write_data_count_width=4 -CSET wuser_width=1 -# END Parameters -# BEGIN Extra information -MISC pkg_timestamp=2012-11-19T12:39:56Z -# END Extra information -GENERATE -# CRC: cda6b7a3 +############################################################## +# +# Xilinx Core Generator version 14.3 +# Date: Thu Feb 28 16:17:27 2013 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:fifo_generator:9.3 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = VHDL +SET device = xc3s700an +SET devicefamily = spartan3a +SET flowvendor = Foundation_ISE +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fgg484 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -4 +SET verilogsim = false +SET vhdlsim = true +# END Project Options +# BEGIN Select +SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3 +# END Select +# BEGIN Parameters +CSET add_ngc_constraint_axi=false +CSET almost_empty_flag=false +CSET almost_full_flag=false +CSET aruser_width=1 +CSET awuser_width=1 +CSET axi_address_width=32 +CSET axi_data_width=64 +CSET axi_type=AXI4_Stream +CSET axis_type=FIFO +CSET buser_width=1 +CSET clock_enable_type=Slave_Interface_Clock_Enable +CSET clock_type_axi=Common_Clock +CSET component_name=wb_ddr_ctrl_wb_from_ddr +CSET data_count=false +CSET data_count_width=4 +CSET disable_timing_violations=true +CSET disable_timing_violations_axi=false +CSET dout_reset_value=0 +CSET empty_threshold_assert_value=2 +CSET empty_threshold_assert_value_axis=1022 +CSET empty_threshold_assert_value_rach=1022 +CSET empty_threshold_assert_value_rdch=1022 +CSET empty_threshold_assert_value_wach=1022 +CSET empty_threshold_assert_value_wdch=1022 +CSET empty_threshold_assert_value_wrch=1022 +CSET empty_threshold_negate_value=3 +CSET enable_aruser=false +CSET enable_awuser=false +CSET enable_buser=false +CSET enable_common_overflow=false +CSET enable_common_underflow=false +CSET enable_data_counts_axis=false +CSET enable_data_counts_rach=false +CSET enable_data_counts_rdch=false +CSET enable_data_counts_wach=false +CSET enable_data_counts_wdch=false +CSET enable_data_counts_wrch=false +CSET enable_ecc=false +CSET enable_ecc_axis=false +CSET enable_ecc_rach=false +CSET enable_ecc_rdch=false +CSET enable_ecc_wach=false +CSET enable_ecc_wdch=false +CSET enable_ecc_wrch=false +CSET enable_read_channel=false +CSET enable_read_pointer_increment_by2=false +CSET enable_reset_synchronization=true +CSET enable_ruser=false +CSET enable_tdata=false +CSET enable_tdest=false +CSET enable_tid=false +CSET enable_tkeep=false +CSET enable_tlast=false +CSET enable_tready=true +CSET enable_tstrobe=false +CSET enable_tuser=false +CSET enable_write_channel=false +CSET enable_wuser=false +CSET fifo_application_type_axis=Data_FIFO +CSET fifo_application_type_rach=Data_FIFO +CSET fifo_application_type_rdch=Data_FIFO +CSET fifo_application_type_wach=Data_FIFO +CSET fifo_application_type_wdch=Data_FIFO +CSET fifo_application_type_wrch=Data_FIFO +CSET fifo_implementation=Independent_Clocks_Distributed_RAM +CSET fifo_implementation_axis=Common_Clock_Block_RAM +CSET fifo_implementation_rach=Common_Clock_Block_RAM +CSET fifo_implementation_rdch=Common_Clock_Block_RAM +CSET fifo_implementation_wach=Common_Clock_Block_RAM +CSET fifo_implementation_wdch=Common_Clock_Block_RAM +CSET fifo_implementation_wrch=Common_Clock_Block_RAM +CSET full_flags_reset_value=1 +CSET full_threshold_assert_value=13 +CSET full_threshold_assert_value_axis=1023 +CSET full_threshold_assert_value_rach=1023 +CSET full_threshold_assert_value_rdch=1023 +CSET full_threshold_assert_value_wach=1023 +CSET full_threshold_assert_value_wdch=1023 +CSET full_threshold_assert_value_wrch=1023 +CSET full_threshold_negate_value=12 +CSET id_width=4 +CSET inject_dbit_error=false +CSET inject_dbit_error_axis=false +CSET inject_dbit_error_rach=false +CSET inject_dbit_error_rdch=false +CSET inject_dbit_error_wach=false +CSET inject_dbit_error_wdch=false +CSET inject_dbit_error_wrch=false +CSET inject_sbit_error=false +CSET inject_sbit_error_axis=false +CSET inject_sbit_error_rach=false +CSET inject_sbit_error_rdch=false +CSET inject_sbit_error_wach=false +CSET inject_sbit_error_wdch=false +CSET inject_sbit_error_wrch=false +CSET input_data_width=64 +CSET input_depth=16 +CSET input_depth_axis=1024 +CSET input_depth_rach=16 +CSET input_depth_rdch=1024 +CSET input_depth_wach=16 +CSET input_depth_wdch=1024 +CSET input_depth_wrch=16 +CSET interface_type=Native +CSET output_data_width=64 +CSET output_depth=16 +CSET overflow_flag=false +CSET overflow_flag_axi=false +CSET overflow_sense=Active_High +CSET overflow_sense_axi=Active_High +CSET performance_options=Standard_FIFO +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold +CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold +CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold +CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold +CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold +CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold +CSET programmable_full_type=No_Programmable_Full_Threshold +CSET programmable_full_type_axis=No_Programmable_Full_Threshold +CSET programmable_full_type_rach=No_Programmable_Full_Threshold +CSET programmable_full_type_rdch=No_Programmable_Full_Threshold +CSET programmable_full_type_wach=No_Programmable_Full_Threshold +CSET programmable_full_type_wdch=No_Programmable_Full_Threshold +CSET programmable_full_type_wrch=No_Programmable_Full_Threshold +CSET rach_type=FIFO +CSET rdch_type=FIFO +CSET read_clock_frequency=1 +CSET read_data_count=false +CSET read_data_count_width=4 +CSET register_slice_mode_axis=Fully_Registered +CSET register_slice_mode_rach=Fully_Registered +CSET register_slice_mode_rdch=Fully_Registered +CSET register_slice_mode_wach=Fully_Registered +CSET register_slice_mode_wdch=Fully_Registered +CSET register_slice_mode_wrch=Fully_Registered +CSET reset_pin=true +CSET reset_type=Asynchronous_Reset +CSET ruser_width=1 +CSET synchronization_stages=2 +CSET synchronization_stages_axi=2 +CSET tdata_width=64 +CSET tdest_width=4 +CSET tid_width=8 +CSET tkeep_width=4 +CSET tstrb_width=4 +CSET tuser_width=4 +CSET underflow_flag=false +CSET underflow_flag_axi=false +CSET underflow_sense=Active_High +CSET underflow_sense_axi=Active_High +CSET use_clock_enable=false +CSET use_dout_reset=true +CSET use_embedded_registers=false +CSET use_extra_logic=false +CSET valid_flag=false +CSET valid_sense=Active_High +CSET wach_type=FIFO +CSET wdch_type=FIFO +CSET wrch_type=FIFO +CSET write_acknowledge_flag=false +CSET write_acknowledge_sense=Active_High +CSET write_clock_frequency=1 +CSET write_data_count=false +CSET write_data_count_width=4 +CSET wuser_width=1 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-07-25T18:11:59Z +# END Extra information +GENERATE +# CRC: cfabdd53 diff --git a/coregen/wb_ddr_ctrl_wb_to_ddr.xco b/coregen/wb_ddr_ctrl_wb_to_ddr.xco old mode 100755 new mode 100644 index bb2380c..ad149bc --- a/coregen/wb_ddr_ctrl_wb_to_ddr.xco +++ b/coregen/wb_ddr_ctrl_wb_to_ddr.xco @@ -1,213 +1,213 @@ -############################################################## -# -# Xilinx Core Generator version 14.4 -# Date: Tue Feb 26 21:38:19 2013 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# Generated from component: xilinx.com:ip:fifo_generator:9.3 -# -############################################################## -# -# BEGIN Project Options -SET addpads = false -SET asysymbol = true -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = VHDL -SET device = xc3s700an -SET devicefamily = spartan3a -SET flowvendor = Foundation_ISE -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = fgg484 -SET removerpms = false -SET simulationfiles = Behavioral -SET speedgrade = -4 -SET verilogsim = false -SET vhdlsim = true -# END Project Options -# BEGIN Select -SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3 -# END Select -# BEGIN Parameters -CSET add_ngc_constraint_axi=false -CSET almost_empty_flag=false -CSET almost_full_flag=false -CSET aruser_width=1 -CSET awuser_width=1 -CSET axi_address_width=32 -CSET axi_data_width=64 -CSET axi_type=AXI4_Stream -CSET axis_type=FIFO -CSET buser_width=1 -CSET clock_enable_type=Slave_Interface_Clock_Enable -CSET clock_type_axi=Common_Clock -CSET component_name=wb_ddr_ctrl_wb_to_ddr -CSET data_count=false -CSET data_count_width=4 -CSET disable_timing_violations=false -CSET disable_timing_violations_axi=false -CSET dout_reset_value=0 -CSET empty_threshold_assert_value=2 -CSET empty_threshold_assert_value_axis=1022 -CSET empty_threshold_assert_value_rach=1022 -CSET empty_threshold_assert_value_rdch=1022 -CSET empty_threshold_assert_value_wach=1022 -CSET empty_threshold_assert_value_wdch=1022 -CSET empty_threshold_assert_value_wrch=1022 -CSET empty_threshold_negate_value=3 -CSET enable_aruser=false -CSET enable_awuser=false -CSET enable_buser=false -CSET enable_common_overflow=false -CSET enable_common_underflow=false -CSET enable_data_counts_axis=false -CSET enable_data_counts_rach=false -CSET enable_data_counts_rdch=false -CSET enable_data_counts_wach=false -CSET enable_data_counts_wdch=false -CSET enable_data_counts_wrch=false -CSET enable_ecc=false -CSET enable_ecc_axis=false -CSET enable_ecc_rach=false -CSET enable_ecc_rdch=false -CSET enable_ecc_wach=false -CSET enable_ecc_wdch=false -CSET enable_ecc_wrch=false -CSET enable_read_channel=false -CSET enable_read_pointer_increment_by2=false -CSET enable_reset_synchronization=true -CSET enable_ruser=false -CSET enable_tdata=false -CSET enable_tdest=false -CSET enable_tid=false -CSET enable_tkeep=false -CSET enable_tlast=false -CSET enable_tready=true -CSET enable_tstrobe=false -CSET enable_tuser=false -CSET enable_write_channel=false -CSET enable_wuser=false -CSET fifo_application_type_axis=Data_FIFO -CSET fifo_application_type_rach=Data_FIFO -CSET fifo_application_type_rdch=Data_FIFO -CSET fifo_application_type_wach=Data_FIFO -CSET fifo_application_type_wdch=Data_FIFO -CSET fifo_application_type_wrch=Data_FIFO -CSET fifo_implementation=Independent_Clocks_Distributed_RAM -CSET fifo_implementation_axis=Common_Clock_Block_RAM -CSET fifo_implementation_rach=Common_Clock_Block_RAM -CSET fifo_implementation_rdch=Common_Clock_Block_RAM -CSET fifo_implementation_wach=Common_Clock_Block_RAM -CSET fifo_implementation_wdch=Common_Clock_Block_RAM -CSET fifo_implementation_wrch=Common_Clock_Block_RAM -CSET full_flags_reset_value=1 -CSET full_threshold_assert_value=13 -CSET full_threshold_assert_value_axis=1023 -CSET full_threshold_assert_value_rach=1023 -CSET full_threshold_assert_value_rdch=1023 -CSET full_threshold_assert_value_wach=1023 -CSET full_threshold_assert_value_wdch=1023 -CSET full_threshold_assert_value_wrch=1023 -CSET full_threshold_negate_value=12 -CSET id_width=4 -CSET inject_dbit_error=false -CSET inject_dbit_error_axis=false -CSET inject_dbit_error_rach=false -CSET inject_dbit_error_rdch=false -CSET inject_dbit_error_wach=false -CSET inject_dbit_error_wdch=false -CSET inject_dbit_error_wrch=false -CSET inject_sbit_error=false -CSET inject_sbit_error_axis=false -CSET inject_sbit_error_rach=false -CSET inject_sbit_error_rdch=false -CSET inject_sbit_error_wach=false -CSET inject_sbit_error_wdch=false -CSET inject_sbit_error_wrch=false -CSET input_data_width=61 -CSET input_depth=16 -CSET input_depth_axis=1024 -CSET input_depth_rach=16 -CSET input_depth_rdch=1024 -CSET input_depth_wach=16 -CSET input_depth_wdch=1024 -CSET input_depth_wrch=16 -CSET interface_type=Native -CSET output_data_width=61 -CSET output_depth=16 -CSET overflow_flag=false -CSET overflow_flag_axi=false -CSET overflow_sense=Active_High -CSET overflow_sense_axi=Active_High -CSET performance_options=Standard_FIFO -CSET programmable_empty_type=No_Programmable_Empty_Threshold -CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold -CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold -CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold -CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold -CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold -CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold -CSET programmable_full_type=No_Programmable_Full_Threshold -CSET programmable_full_type_axis=No_Programmable_Full_Threshold -CSET programmable_full_type_rach=No_Programmable_Full_Threshold -CSET programmable_full_type_rdch=No_Programmable_Full_Threshold -CSET programmable_full_type_wach=No_Programmable_Full_Threshold -CSET programmable_full_type_wdch=No_Programmable_Full_Threshold -CSET programmable_full_type_wrch=No_Programmable_Full_Threshold -CSET rach_type=FIFO -CSET rdch_type=FIFO -CSET read_clock_frequency=1 -CSET read_data_count=false -CSET read_data_count_width=4 -CSET register_slice_mode_axis=Fully_Registered -CSET register_slice_mode_rach=Fully_Registered -CSET register_slice_mode_rdch=Fully_Registered -CSET register_slice_mode_wach=Fully_Registered -CSET register_slice_mode_wdch=Fully_Registered -CSET register_slice_mode_wrch=Fully_Registered -CSET reset_pin=true -CSET reset_type=Asynchronous_Reset -CSET ruser_width=1 -CSET synchronization_stages=2 -CSET synchronization_stages_axi=2 -CSET tdata_width=64 -CSET tdest_width=4 -CSET tid_width=8 -CSET tkeep_width=4 -CSET tstrb_width=4 -CSET tuser_width=4 -CSET underflow_flag=false -CSET underflow_flag_axi=false -CSET underflow_sense=Active_High -CSET underflow_sense_axi=Active_High -CSET use_clock_enable=false -CSET use_dout_reset=true -CSET use_embedded_registers=false -CSET use_extra_logic=false -CSET valid_flag=false -CSET valid_sense=Active_High -CSET wach_type=FIFO -CSET wdch_type=FIFO -CSET wrch_type=FIFO -CSET write_acknowledge_flag=false -CSET write_acknowledge_sense=Active_High -CSET write_clock_frequency=1 -CSET write_data_count=false -CSET write_data_count_width=4 -CSET wuser_width=1 -# END Parameters -# BEGIN Extra information -MISC pkg_timestamp=2012-11-19T12:39:56Z -# END Extra information -GENERATE -# CRC: 34700267 +############################################################## +# +# Xilinx Core Generator version 14.3 +# Date: Thu Feb 28 16:33:31 2013 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:fifo_generator:9.3 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = VHDL +SET device = xc3s700an +SET devicefamily = spartan3a +SET flowvendor = Foundation_ISE +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fgg484 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -4 +SET verilogsim = false +SET vhdlsim = true +# END Project Options +# BEGIN Select +SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3 +# END Select +# BEGIN Parameters +CSET add_ngc_constraint_axi=false +CSET almost_empty_flag=false +CSET almost_full_flag=false +CSET aruser_width=1 +CSET awuser_width=1 +CSET axi_address_width=32 +CSET axi_data_width=64 +CSET axi_type=AXI4_Stream +CSET axis_type=FIFO +CSET buser_width=1 +CSET clock_enable_type=Slave_Interface_Clock_Enable +CSET clock_type_axi=Common_Clock +CSET component_name=wb_ddr_ctrl_wb_to_ddr +CSET data_count=false +CSET data_count_width=4 +CSET disable_timing_violations=true +CSET disable_timing_violations_axi=false +CSET dout_reset_value=0 +CSET empty_threshold_assert_value=2 +CSET empty_threshold_assert_value_axis=1022 +CSET empty_threshold_assert_value_rach=1022 +CSET empty_threshold_assert_value_rdch=1022 +CSET empty_threshold_assert_value_wach=1022 +CSET empty_threshold_assert_value_wdch=1022 +CSET empty_threshold_assert_value_wrch=1022 +CSET empty_threshold_negate_value=3 +CSET enable_aruser=false +CSET enable_awuser=false +CSET enable_buser=false +CSET enable_common_overflow=false +CSET enable_common_underflow=false +CSET enable_data_counts_axis=false +CSET enable_data_counts_rach=false +CSET enable_data_counts_rdch=false +CSET enable_data_counts_wach=false +CSET enable_data_counts_wdch=false +CSET enable_data_counts_wrch=false +CSET enable_ecc=false +CSET enable_ecc_axis=false +CSET enable_ecc_rach=false +CSET enable_ecc_rdch=false +CSET enable_ecc_wach=false +CSET enable_ecc_wdch=false +CSET enable_ecc_wrch=false +CSET enable_read_channel=false +CSET enable_read_pointer_increment_by2=false +CSET enable_reset_synchronization=true +CSET enable_ruser=false +CSET enable_tdata=false +CSET enable_tdest=false +CSET enable_tid=false +CSET enable_tkeep=false +CSET enable_tlast=false +CSET enable_tready=true +CSET enable_tstrobe=false +CSET enable_tuser=false +CSET enable_write_channel=false +CSET enable_wuser=false +CSET fifo_application_type_axis=Data_FIFO +CSET fifo_application_type_rach=Data_FIFO +CSET fifo_application_type_rdch=Data_FIFO +CSET fifo_application_type_wach=Data_FIFO +CSET fifo_application_type_wdch=Data_FIFO +CSET fifo_application_type_wrch=Data_FIFO +CSET fifo_implementation=Independent_Clocks_Distributed_RAM +CSET fifo_implementation_axis=Common_Clock_Block_RAM +CSET fifo_implementation_rach=Common_Clock_Block_RAM +CSET fifo_implementation_rdch=Common_Clock_Block_RAM +CSET fifo_implementation_wach=Common_Clock_Block_RAM +CSET fifo_implementation_wdch=Common_Clock_Block_RAM +CSET fifo_implementation_wrch=Common_Clock_Block_RAM +CSET full_flags_reset_value=1 +CSET full_threshold_assert_value=13 +CSET full_threshold_assert_value_axis=1023 +CSET full_threshold_assert_value_rach=1023 +CSET full_threshold_assert_value_rdch=1023 +CSET full_threshold_assert_value_wach=1023 +CSET full_threshold_assert_value_wdch=1023 +CSET full_threshold_assert_value_wrch=1023 +CSET full_threshold_negate_value=12 +CSET id_width=4 +CSET inject_dbit_error=false +CSET inject_dbit_error_axis=false +CSET inject_dbit_error_rach=false +CSET inject_dbit_error_rdch=false +CSET inject_dbit_error_wach=false +CSET inject_dbit_error_wdch=false +CSET inject_dbit_error_wrch=false +CSET inject_sbit_error=false +CSET inject_sbit_error_axis=false +CSET inject_sbit_error_rach=false +CSET inject_sbit_error_rdch=false +CSET inject_sbit_error_wach=false +CSET inject_sbit_error_wdch=false +CSET inject_sbit_error_wrch=false +CSET input_data_width=96 +CSET input_depth=16 +CSET input_depth_axis=1024 +CSET input_depth_rach=16 +CSET input_depth_rdch=1024 +CSET input_depth_wach=16 +CSET input_depth_wdch=1024 +CSET input_depth_wrch=16 +CSET interface_type=Native +CSET output_data_width=96 +CSET output_depth=16 +CSET overflow_flag=false +CSET overflow_flag_axi=false +CSET overflow_sense=Active_High +CSET overflow_sense_axi=Active_High +CSET performance_options=Standard_FIFO +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold +CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold +CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold +CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold +CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold +CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold +CSET programmable_full_type=No_Programmable_Full_Threshold +CSET programmable_full_type_axis=No_Programmable_Full_Threshold +CSET programmable_full_type_rach=No_Programmable_Full_Threshold +CSET programmable_full_type_rdch=No_Programmable_Full_Threshold +CSET programmable_full_type_wach=No_Programmable_Full_Threshold +CSET programmable_full_type_wdch=No_Programmable_Full_Threshold +CSET programmable_full_type_wrch=No_Programmable_Full_Threshold +CSET rach_type=FIFO +CSET rdch_type=FIFO +CSET read_clock_frequency=1 +CSET read_data_count=false +CSET read_data_count_width=4 +CSET register_slice_mode_axis=Fully_Registered +CSET register_slice_mode_rach=Fully_Registered +CSET register_slice_mode_rdch=Fully_Registered +CSET register_slice_mode_wach=Fully_Registered +CSET register_slice_mode_wdch=Fully_Registered +CSET register_slice_mode_wrch=Fully_Registered +CSET reset_pin=true +CSET reset_type=Asynchronous_Reset +CSET ruser_width=1 +CSET synchronization_stages=2 +CSET synchronization_stages_axi=2 +CSET tdata_width=64 +CSET tdest_width=4 +CSET tid_width=8 +CSET tkeep_width=4 +CSET tstrb_width=4 +CSET tuser_width=4 +CSET underflow_flag=false +CSET underflow_flag_axi=false +CSET underflow_sense=Active_High +CSET underflow_sense_axi=Active_High +CSET use_clock_enable=false +CSET use_dout_reset=true +CSET use_embedded_registers=false +CSET use_extra_logic=false +CSET valid_flag=false +CSET valid_sense=Active_High +CSET wach_type=FIFO +CSET wdch_type=FIFO +CSET wrch_type=FIFO +CSET write_acknowledge_flag=false +CSET write_acknowledge_sense=Active_High +CSET write_clock_frequency=1 +CSET write_data_count=false +CSET write_data_count_width=4 +CSET wuser_width=1 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-07-25T18:11:59Z +# END Extra information +GENERATE +# CRC: dad99623 diff --git a/src/wb_ddr_ctrl_wb.vhd b/src/wb_ddr_ctrl_wb.vhd index a880a55..7b5dfdb 100755 --- a/src/wb_ddr_ctrl_wb.vhd +++ b/src/wb_ddr_ctrl_wb.vhd @@ -73,10 +73,10 @@ component wb_ddr_ctrl_wb_from_ddr IS rst : IN STD_LOGIC; wr_clk : IN STD_LOGIC; rd_clk : IN STD_LOGIC; - din : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + din : IN STD_LOGIC_VECTOR(63 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; - dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); full : OUT STD_LOGIC; empty : OUT STD_LOGIC ); @@ -86,10 +86,10 @@ component wb_ddr_ctrl_wb_to_ddr IS rst : IN STD_LOGIC; wr_clk : IN STD_LOGIC; rd_clk : IN STD_LOGIC; - din : IN STD_LOGIC_VECTOR(60 DOWNTO 0); + din : IN STD_LOGIC_VECTOR(95 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; - dout : OUT STD_LOGIC_VECTOR(60 DOWNTO 0); + dout : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); full : OUT STD_LOGIC; empty : OUT STD_LOGIC ); @@ -111,11 +111,11 @@ component wb_ddr_ctrl_wb_sc is bte_i : in std_ulogic_vector(1 downto 0); -- To/from ddr clock domain - ddr_din : out std_ulogic_vector(31 downto 0); - ddr_dout : in std_ulogic_vector(31 downto 0); - ddr_adr : out std_ulogic_vector(23 downto 0); + ddr_din : out std_ulogic_vector(63 downto 0); + ddr_dout : in std_ulogic_vector(63 downto 0); + ddr_adr : out std_ulogic_vector(22 downto 0); ddr_we : out std_ulogic; - ddr_be : out std_ulogic_vector(3 downto 0); + ddr_be : out std_ulogic_vector(7 downto 0); fifo_to_ddr_write : out std_ulogic; fifo_from_ddr_read : out std_ulogic; @@ -145,11 +145,11 @@ component wb_ddr_ctrl_wb_dc is ctrl_ar_done : in std_logic; -- To/from system clock domain - din : in std_ulogic_vector(31 downto 0); - dout : out std_ulogic_vector(31 downto 0); - adr : in std_ulogic_vector(23 downto 0); + din : in std_ulogic_vector(63 downto 0); + dout : out std_ulogic_vector(63 downto 0); + adr : in std_ulogic_vector(22 downto 0); we : in std_ulogic; - be : in std_ulogic_vector(3 downto 0); + be : in std_ulogic_vector(7 downto 0); fifo_to_sys_write : out std_ulogic; fifo_from_sys_read : out std_ulogic; @@ -163,10 +163,10 @@ signal s2d_fifo_rd, s2d_fifo_wr, d2s_fifo_rd, d2s_fifo_wr : std_ulogic; signal s2d_fifo_empty, s2d_fifo_full, d2s_fifo_empty, d2s_fifo_full : std_ulogic; -- FIFO data signals -signal s2d_fifo_din : std_ulogic_vector(60 downto 0); -signal d2s_fifo_din : std_ulogic_vector(31 downto 0); -signal s2d_fifo_dout : std_logic_vector(60 downto 0); -signal d2s_fifo_dout : std_logic_vector(31 downto 0); +signal s2d_fifo_din : std_ulogic_vector(95 downto 0); +signal d2s_fifo_din : std_ulogic_vector(63 downto 0); +signal s2d_fifo_dout : std_logic_vector(95 downto 0); +signal d2s_fifo_dout : std_logic_vector(63 downto 0); signal ddr2_clk180 : std_ulogic; @@ -191,11 +191,11 @@ system_cd_inst : wb_ddr_ctrl_wb_sc bte_i => bte_i, -- To/from ddr clock domain - ddr_din => s2d_fifo_din(31 downto 0), + ddr_din => s2d_fifo_din(63 downto 0), ddr_dout => std_ulogic_vector(d2s_fifo_dout), - ddr_adr => s2d_fifo_din(55 downto 32), - ddr_we => s2d_fifo_din(56), - ddr_be => s2d_fifo_din(60 downto 57), + ddr_adr => s2d_fifo_din(86 downto 64), + ddr_we => s2d_fifo_din(87), + ddr_be => s2d_fifo_din(95 downto 88), fifo_to_ddr_write => s2d_fifo_wr, fifo_from_ddr_read => d2s_fifo_rd, @@ -255,11 +255,11 @@ ddr_cd_inst : wb_ddr_ctrl_wb_dc ctrl_ar_done => ctrl_ar_done, -- To/from system clock domain - din => std_ulogic_vector(s2d_fifo_dout(31 downto 0)), + din => std_ulogic_vector(s2d_fifo_dout(63 downto 0)), dout => d2s_fifo_din, - adr => std_ulogic_vector(s2d_fifo_dout(55 downto 32)), - we => s2d_fifo_dout(56), - be => std_ulogic_vector(s2d_fifo_dout(60 downto 57)), + adr => std_ulogic_vector(s2d_fifo_dout(86 downto 64)), + we => s2d_fifo_dout(87), + be => std_ulogic_vector(s2d_fifo_dout(95 downto 88)), fifo_to_sys_write => d2s_fifo_wr, fifo_from_sys_read => s2d_fifo_rd, diff --git a/src/wb_ddr_ctrl_wb_dc.vhd b/src/wb_ddr_ctrl_wb_dc.vhd index e24670f..9cff0ed 100755 --- a/src/wb_ddr_ctrl_wb_dc.vhd +++ b/src/wb_ddr_ctrl_wb_dc.vhd @@ -53,11 +53,11 @@ entity wb_ddr_ctrl_wb_dc is ctrl_ar_done : in std_logic; -- To/from system clock domain - din : in std_ulogic_vector(31 downto 0); - dout : out std_ulogic_vector(31 downto 0); - adr : in std_ulogic_vector(23 downto 0); + din : in std_ulogic_vector(63 downto 0); + dout : out std_ulogic_vector(63 downto 0); + adr : in std_ulogic_vector(22 downto 0); we : in std_ulogic; - be : in std_ulogic_vector(3 downto 0); + be : in std_ulogic_vector(7 downto 0); fifo_to_sys_write : out std_ulogic; fifo_from_sys_read : out std_ulogic; @@ -83,18 +83,20 @@ architecture Behavioral of wb_ddr_ctrl_wb_dc is row_addr : in std_ulogic_vector(12 downto 0); ddr_address_en : out std_ulogic; ddr_dout_en : out std_ulogic; + ddr_dout_high : out std_ulogic; ddr_dmask_rst : out std_ulogic; ddr_dmask_en : out std_ulogic; + dout_low_en : out std_ulogic; ctrl_command_register_d : out std_logic_vector(2 downto 0); ctrl_burst_done_d : out std_ulogic; fifo_from_sys_read : out std_ulogic); end component; -signal ddr_address : std_ulogic_vector(23 downto 0) := (others => '-'); +signal ddr_address : std_ulogic_vector(22 downto 0) := (others => '-'); signal ddr_address_en : std_ulogic := '0'; signal ddr_dout : std_ulogic_vector(31 downto 0) := (others => '-'); -signal ddr_dout_en : std_ulogic := '0'; +signal ddr_dout_en, ddr_dout_high : std_ulogic := '0'; signal ddr_dmask : std_ulogic_vector(3 downto 0) := (others => '0'); signal ddr_dmask_rst, ddr_dmask_en : std_ulogic := '0'; @@ -102,6 +104,10 @@ signal ddr_dmask_rst, ddr_dmask_en : std_ulogic := '0'; signal ctrl_command_register_d : std_logic_vector(2 downto 0) := "000"; signal ctrl_burst_done_d : std_ulogic := '0'; +signal dout_low : std_ulogic_vector(31 downto 0) := (others => '-'); +signal dout_low_en : std_ulogic := '0'; + +signal ctrl_data_valid_toggle : std_ulogic := '0'; begin wb_ddr_ctrl_wb_dc_fsm_inst: wb_ddr_ctrl_wb_dc_fsm @@ -116,11 +122,13 @@ wb_ddr_ctrl_wb_dc_fsm_inst: wb_ddr_ctrl_wb_dc_fsm ctrl_ar_done => ctrl_ar_done, fifo_from_sys_empty => fifo_from_sys_empty, we => we, - row_addr => adr(21 downto 9), + row_addr => adr(20 downto 8), ddr_address_en => ddr_address_en, ddr_dout_en => ddr_dout_en, + ddr_dout_high => ddr_dout_high, ddr_dmask_rst => ddr_dmask_rst, ddr_dmask_en => ddr_dmask_en, + --dout_low_en => dout_low_en, ctrl_command_register_d => ctrl_command_register_d, ctrl_burst_done_d => ctrl_burst_done_d, fifo_from_sys_read => fifo_from_sys_read @@ -137,14 +145,18 @@ ddr_address_reg : process(ddr2_clk180) end process ddr_address_reg; -- remap address for ddr controller (so column is lowest) -ctrl_input_address <= std_logic_vector(ddr_address(21 downto 9) & ddr_address(8 downto 0) & '0' & ddr_address(23 downto 22)); +ctrl_input_address <= std_logic_vector(ddr_address(20 downto 8) & ddr_address(7 downto 0) & "00" & ddr_address(22 downto 21)); -- ddr_dout register ddr_dout_reg : process(ddr2_clk180) begin if rising_edge(ddr2_clk180) then if ddr_dout_en = '1' then - ddr_dout <= din; + if ddr_dout_high = '1' then + ddr_dout <= din(63 downto 32); + else + ddr_dout <= din(31 downto 0); + end if; end if; end if; end process ddr_dout_reg; @@ -154,9 +166,13 @@ ddr_dmask_reg : process(ddr2_clk180) begin if rising_edge(ddr2_clk180) then if ddr_dmask_rst = '1' or ddr2_reset = '1' then - ddr_dmask <= (others => '0'); + ddr_dmask <= (others => '1'); elsif ddr_dmask_en = '1' then - ddr_dmask <= be; + if ddr_dout_high = '1' then + ddr_dmask <= be(7 downto 4); + else + ddr_dmask <= be(3 downto 0); + end if; end if; end if; end process ddr_dmask_reg; @@ -185,9 +201,31 @@ ctrl_burst_done_reg : process(ddr2_clk180) ctrl_burst_done <= ctrl_burst_done_d; end if; end process ctrl_burst_done_reg; + +-- ctrl_data_valid tff +ctrl_data_valid_tff : process(ddr2_clk90) + begin + if rising_edge(ddr2_clk90) then + if ctrl_data_valid = '1' then + ctrl_data_valid_toggle <= not ctrl_data_valid_toggle; + end if; + end if; + end process ctrl_data_valid_tff; + +dout_low_en <= ctrl_data_valid and not ctrl_data_valid_toggle; + +-- dout_low register +dout_low_reg : process(ddr2_clk90) + begin + if rising_edge(ddr2_clk90) then + if dout_low_en = '1' then + dout_low <= std_ulogic_vector(ctrl_output_data); + end if; + end if; + end process dout_low_reg; -- move data from ddr to fifo -dout <= std_ulogic_vector(ctrl_output_data); -fifo_to_sys_write <= ctrl_data_valid; +dout <= std_ulogic_vector(ctrl_output_data) & dout_low; +fifo_to_sys_write <= ctrl_data_valid and ctrl_data_valid_toggle; end Behavioral; diff --git a/src/wb_ddr_ctrl_wb_dc_fsm.vhd b/src/wb_ddr_ctrl_wb_dc_fsm.vhd index 45158aa..80212ad 100755 --- a/src/wb_ddr_ctrl_wb_dc_fsm.vhd +++ b/src/wb_ddr_ctrl_wb_dc_fsm.vhd @@ -51,8 +51,10 @@ entity wb_ddr_ctrl_wb_dc_fsm is -- Outputs ddr_address_en : out std_ulogic; ddr_dout_en : out std_ulogic; + ddr_dout_high : out std_ulogic; ddr_dmask_rst : out std_ulogic; ddr_dmask_en : out std_ulogic; + dout_low_en : out std_ulogic; ctrl_command_register_d : out std_logic_vector(2 downto 0); ctrl_burst_done_d : out std_ulogic; fifo_from_sys_read : out std_ulogic @@ -80,28 +82,18 @@ signal fifo_from_sys_read_int, fifo_from_sys_valid : std_ulogic := '0'; begin --- input FIFO control -fifo_from_sys_read_int <= '1' when ((ctrl_state = S_IDLE and ctrl_auto_ref_req = '0' and fifo_pending = '0') or - (ctrl_state = S_REQUEST_INIT and we = '1') or - (ctrl_state = S_WRITE1 and ctrl_cmd_ack = '1') or - (ctrl_state = S_WRITE2 and not (fifo_from_sys_valid = '0' or row_addr /= burst_start_adr or - we = '0' or ctrl_auto_ref_req = '1')) or - (ctrl_state = S_WRITE4) or - (ctrl_state = S_READ3 or ctrl_state = S_READ5) or - (ctrl_state = S_READ4 and not (fifo_from_sys_valid = '0' or row_addr /= burst_start_adr or - we = '1' or ctrl_auto_ref_req = '1')) or - (ctrl_state = S_READ2) - ) and fifo_from_sys_empty = '0' else - '0'; + is_fifo_from_sys_valid : process(ddr2_clk0) begin if rising_edge(ddr2_clk0) then - fifo_from_sys_valid <= fifo_from_sys_read_int; + if fifo_from_sys_read_int = '1' then + fifo_from_sys_valid <= not fifo_from_sys_empty; + end if; end if; end process is_fifo_from_sys_valid; -fifo_from_sys_read <= fifo_from_sys_read_int; +fifo_from_sys_read <= fifo_from_sys_read_int and not fifo_from_sys_empty; ctrl_fsm_state : process(ddr2_clk180) begin @@ -192,25 +184,48 @@ ctrl_fsm_state : process(ddr2_clk180) end if; end if; end process ctrl_fsm_state; +-- input FIFO control +--fifo_from_sys_read_int <= '1' when ((ctrl_state = S_IDLE and ctrl_auto_ref_req = '0' and fifo_pending = '0') or +-- (ctrl_state = S_REQUEST_INIT and we = '1') or +-- (ctrl_state = S_WRITE1 and ctrl_cmd_ack = '1') or +-- (ctrl_state = S_WRITE2 and not (fifo_from_sys_valid = '0' or row_addr /= burst_start_adr or +-- we = '0' or ctrl_auto_ref_req = '1')) or +-- (ctrl_state = S_WRITE4) or +-- (ctrl_state = S_READ3 or ctrl_state = S_READ5) or +-- (ctrl_state = S_READ4 and not (fifo_from_sys_valid = '0' or row_addr /= burst_start_adr or +-- we = '1' or ctrl_auto_ref_req = '1')) or +-- (ctrl_state = S_READ2) +-- ) else +-- '0'; + ctrl_fsm_out : process(ctrl_state, ddr2_reset, we, ctrl_cmd_ack, fifo_from_sys_valid, row_addr, burst_start_adr, ctrl_auto_ref_req) begin - ddr_dmask_rst <= '0'; - ddr_dmask_en <= '0'; - ddr_dout_en <= '0'; - ddr_address_en <= '0'; + ddr_dmask_rst <= '0'; -- dmask register reset + ddr_dmask_en <= '0'; -- dmask register enable + ddr_dout_en <= '0'; -- output register enable + ddr_dout_high <= '-'; -- output register low/high mux + ddr_address_en <= '0'; -- address register enable + dout_low_en <= '0'; -- input data lower half register enable ctrl_burst_done_d <= '0'; ctrl_command_register_d <= ctrl_command_nop; + fifo_from_sys_read_int <= '0'; case ctrl_state is when S_INITIALIZE => ctrl_command_register_d <= ctrl_command_initialize; + when S_IDLE => + if ctrl_auto_ref_req = '0' and fifo_pending = '0' then + fifo_from_sys_read_int <= '1'; + end if; when S_REQUEST_INIT => if we = '1' then ddr_dmask_en <= '1'; ddr_dout_en <= '1'; + ddr_dout_high <= '0'; ctrl_command_register_d <= ctrl_command_write; + --fifo_from_sys_read_int <= '1'; else ctrl_command_register_d <= ctrl_command_read; end if; @@ -220,6 +235,8 @@ ctrl_fsm_out : process(ctrl_state, ddr2_reset, we, ctrl_cmd_ack, fifo_from_sys_v if ctrl_cmd_ack = '1' then ddr_dmask_en <= '1'; ddr_dout_en <= '1'; + ddr_dout_high <= '1'; + fifo_from_sys_read_int <= '1'; end if; ctrl_command_register_d <= ctrl_command_write; when S_WRITE2 => @@ -230,15 +247,19 @@ ctrl_fsm_out : process(ctrl_state, ddr2_reset, we, ctrl_cmd_ack, fifo_from_sys_v else ddr_dmask_en <= '1'; ddr_dout_en <= '1'; + ddr_dout_high <= '0'; + --fifo_from_sys_read_int <= '1'; end if; ctrl_command_register_d <= ctrl_command_write; when S_WRITE3 => ddr_dmask_en <= '1'; ddr_dout_en <= '1'; + ddr_dout_high <= '1'; ddr_address_en <= '1'; ctrl_command_register_d <= ctrl_command_write; when S_WRITE4 => ctrl_command_register_d <= ctrl_command_write; + fifo_from_sys_read_int <= '1'; when S_WRITE_END1 => ctrl_burst_done_d <= '1'; @@ -246,8 +267,10 @@ ctrl_fsm_out : process(ctrl_state, ddr2_reset, we, ctrl_cmd_ack, fifo_from_sys_v ctrl_command_register_d <= ctrl_command_read; when S_READ2 => ctrl_command_register_d <= ctrl_command_read; + --fifo_from_sys_read_int <= '1'; when S_READ3 => ctrl_command_register_d <= ctrl_command_read; + fifo_from_sys_read_int <= '1'; when S_READ4 => if fifo_from_sys_valid = '0' or row_addr /= burst_start_adr or we = '1' or ctrl_auto_ref_req = '1' then @@ -255,9 +278,11 @@ ctrl_fsm_out : process(ctrl_state, ddr2_reset, we, ctrl_cmd_ack, fifo_from_sys_v ctrl_burst_done_d <= '1'; else ddr_address_en <= '1'; + --fifo_from_sys_read_int <= '1'; end if; when S_READ5 => ctrl_command_register_d <= ctrl_command_read; + fifo_from_sys_read_int <= '1'; when S_READ_END1 => ctrl_burst_done_d <= '1'; diff --git a/src/wb_ddr_ctrl_wb_sc.vhd b/src/wb_ddr_ctrl_wb_sc.vhd index 444300a..e433193 100755 --- a/src/wb_ddr_ctrl_wb_sc.vhd +++ b/src/wb_ddr_ctrl_wb_sc.vhd @@ -48,11 +48,11 @@ entity wb_ddr_ctrl_wb_sc is bte_i : in std_ulogic_vector(1 downto 0); -- To/from ddr clock domain - ddr_din : out std_ulogic_vector(31 downto 0); - ddr_dout : in std_ulogic_vector(31 downto 0); - ddr_adr : out std_ulogic_vector(23 downto 0); + ddr_din : out std_ulogic_vector(63 downto 0); + ddr_dout : in std_ulogic_vector(63 downto 0); + ddr_adr : out std_ulogic_vector(22 downto 0); ddr_we : out std_ulogic; - ddr_be : out std_ulogic_vector(3 downto 0); + ddr_be : out std_ulogic_vector(7 downto 0); fifo_to_ddr_write : out std_ulogic; fifo_from_ddr_read : out std_ulogic; @@ -62,14 +62,18 @@ entity wb_ddr_ctrl_wb_sc is end wb_ddr_ctrl_wb_sc; architecture Behavioral of wb_ddr_ctrl_wb_sc is -type states is (S_IDLE, S_WRITE_CLASSIC1, S_READ_CLASSIC1, S_READ_CLASSIC2); +type states is (S_IDLE, + S_WRITE_CLASSIC1, + S_WRITE_BURST1, S_WRITE_BURST2, S_WRITE_BURST_WAIT1, + S_WRITE_BURST_WAIT2, + S_READ_CLASSIC1, S_READ_CLASSIC2, S_READ_CLASSIC3); signal state : states := S_IDLE; signal fifo_from_ddr_read_int, fifo_from_ddr_valid : std_ulogic; begin -fifo_from_ddr_read_int <= '1' when (((state = S_READ_CLASSIC1 and fifo_to_ddr_full = '0') or - (state = S_READ_CLASSIC2) +fifo_from_ddr_read_int <= '1' when ((--(state = S_READ_CLASSIC1 and fifo_to_ddr_full = '0') or + (state = S_READ_CLASSIC1) ) and fifo_from_ddr_empty = '0') or rst_i = '1' else '0'; @@ -94,34 +98,62 @@ wb_slave : process(clk_i) ack_o <= '0'; state <= S_IDLE; else - ddr_din <= (others => '-'); - ddr_adr <= (others => '-'); + --ddr_din <= (others => '-'); + --ddr_adr <= (others => '-'); ddr_we <= '-'; - ddr_be <= (others => '-'); + --ddr_be <= (others => '-'); fifo_to_ddr_write <= '0'; ack_o <= '0'; case state is when S_IDLE => if stb_i = '1' then if we_i = '1' then - if cti_i = "010" then -- incrementing burst - null; - else -- classic cycle or unsupported - if fifo_to_ddr_full = '0' then - ddr_din <= dat_i; - ddr_adr <= adr_i; - ddr_we <= '1'; - ddr_be <= not sel_i; - fifo_to_ddr_write <= '1'; - state <= S_WRITE_CLASSIC1; + if cti_i = "010" and bte_i = "00" then -- incrementing + -- linear burst + if fifo_to_ddr_full = '0' then + ack_o <= '1'; + if adr_i(2) = '0' then -- aligned start + ddr_adr <= (others => '-'); + ddr_din(63 downto 32) <= (others => '-'); + ddr_din(31 downto 0) <= dat_i; + ddr_be(7 downto 4) <= (others => '-'); + ddr_be(3 downto 0) <= not sel_i; + state <= S_WRITE_BURST1; + else -- unaligned start + ddr_adr <= adr_i(25 downto 3); + ddr_din(31 downto 0) <= (others => '-'); + ddr_din(63 downto 32) <= dat_i; + ddr_be <= not sel_i & "1111"; + ddr_we <= '1'; + fifo_to_ddr_write <= '1'; + state <= S_WRITE_BURST2; end if; + end if; + else -- classic cycle or unsupported + if fifo_to_ddr_full = '0' then + if adr_i(2) = '0' then + ddr_din(31 downto 0) <= dat_i; + ddr_din(63 downto 32) <= (others => '-'); + ddr_be <= "1111" & not sel_i; + else + ddr_din(31 downto 0) <= (others => '-'); + ddr_din(63 downto 32) <= dat_i; + ddr_be <= not sel_i & "1111"; + end if; + ddr_adr <= adr_i(25 downto 3); + ddr_we <= '1'; + + fifo_to_ddr_write <= '1'; + ack_o <= '1'; + state <= S_WRITE_CLASSIC1; + end if; end if; else if cti_i = "010" then -- incrementing burst null; else -- classic cycle or unsupported if fifo_to_ddr_full = '0' then - ddr_adr <= adr_i; + ddr_adr <= adr_i(25 downto 3); ddr_we <= '0'; fifo_to_ddr_write <= '1'; state <= S_READ_CLASSIC1; @@ -131,29 +163,84 @@ wb_slave : process(clk_i) end if; when S_WRITE_CLASSIC1 => - if fifo_to_ddr_full = '0' then - ddr_din <= (others => '-'); - ddr_adr <= std_ulogic_vector(unsigned(adr_i) + 1); + ddr_adr <= (others => '-'); + state <= S_IDLE; + + when S_WRITE_BURST1 => -- high dword, commit + ddr_din(63 downto 32) <= dat_i; + ddr_be(7 downto 0) <= not sel_i; + ddr_adr <= adr_i(25 downto 3); + if fifo_to_ddr_full = '0' then ddr_we <= '1'; - ddr_be <= (others => '1'); fifo_to_ddr_write <= '1'; - ack_o <= '1'; - state <= S_IDLE; - end if; - when S_READ_CLASSIC1 => + if cti_i = "111" then -- EOB, aligned end + state <= S_IDLE; + ack_o <= '0'; + else + state <= S_WRITE_BURST2; + ack_o <= '1'; + end if; + else -- FIFO full + state <= S_WRITE_BURST_WAIT1; + ack_o <= '0'; + end if; + when S_WRITE_BURST2 => -- low dword + ddr_adr <= (others => '-'); + ddr_din(63 downto 32) <= (others => '-'); + ddr_din(31 downto 0) <= dat_i; + ddr_be(7 downto 4) <= (others => '-'); + ddr_be(3 downto 0) <= not sel_i; + + if cti_i = "111" then -- EOB, unaligned end + ddr_be(7 downto 4) <= (others => '1'); + ddr_adr <= adr_i(25 downto 3); + if fifo_to_ddr_full = '1' then + ddr_we <= '1'; + fifo_to_ddr_write <= '1'; + state <= S_IDLE; + else + state <= S_WRITE_BURST_WAIT2; + end if; + ack_o <= '0'; + else + state <= S_WRITE_BURST1; + ack_o <= '1'; + end if; + when S_WRITE_BURST_WAIT1 => if fifo_to_ddr_full = '0' then - ddr_adr <= std_ulogic_vector(unsigned(adr_i) + 1); - ddr_we <= '0'; + ddr_we <= '1'; fifo_to_ddr_write <= '1'; + if cti_i = "111" then + state <= S_IDLE; + ack_o <= '0'; + else + state <= S_WRITE_BURST2; + ack_o <= '1'; + end if; + end if; + when S_WRITE_BURST_WAIT2 => + ddr_we <= '1'; + fifo_to_ddr_write <= '1'; + state <= S_IDLE; + + when S_READ_CLASSIC1 => + ddr_adr <= (others => '-'); + if fifo_from_ddr_valid = '1' then state <= S_READ_CLASSIC2; end if; when S_READ_CLASSIC2 => - if fifo_from_ddr_valid = '1' then - dat_o <= ddr_dout; - ack_o <= '1'; - state <= S_IDLE; + ddr_adr <= (others => '-'); + if adr_i(2) = '0' then + dat_o <= ddr_dout(31 downto 0); + else + dat_o <= ddr_dout(63 downto 32); end if; + ack_o <= '1'; + state <= S_READ_CLASSIC3; + when S_READ_CLASSIC3 => + ddr_adr <= (others => '-'); + state <= S_IDLE; end case; end if; end if; diff --git a/tb/wb_ddr_ctrl_tb.vhd b/tb/wb_ddr_ctrl_tb.vhd index 2944df2..73523b1 100755 --- a/tb/wb_ddr_ctrl_tb.vhd +++ b/tb/wb_ddr_ctrl_tb.vhd @@ -6,7 +6,7 @@ -- Author : Matthias Blankertz -- Company : -- Created : 2013-02-26 --- Last update: 2013-02-27 +-- Last update: 2013-02-28 -- Platform : -- Standard : VHDL'93 ------------------------------------------------------------------------------- @@ -216,8 +216,51 @@ begin -- testbench wait until rising_edge(clk_i); end loop; stb_i <= '0' after 2 ns; - assert dat_o = x"deadbeef" report "Read failed: unexpected data" severity failure; + assert dat_o = x"deadbeef" report "Read failed: unexpected data" severity warning; wait until rising_edge(clk_i); + + -- simple write cycle + wait until rising_edge(clk_i); + stb_i <= '1' after 2 ns; + we_i <= '1' after 2 ns; + sel_i <= "1111" after 2 ns; + adr_i <= x"000011" after 2 ns; + dat_i <= x"12345678" after 2 ns; + + wait until rising_edge(clk_i); + while ack_o = '0' loop + wait until rising_edge(clk_i); + end loop; + stb_i <= '0' after 2 ns; + wait until rising_edge(clk_i); + + -- simple read cycle + wait until rising_edge(clk_i); + stb_i <= '1' after 2 ns; + we_i <= '0' after 2 ns; + adr_i <= x"000010" after 2 ns; + wait until rising_edge(clk_i); + while ack_o = '0' loop + wait until rising_edge(clk_i); + end loop; + stb_i <= '0' after 2 ns; + assert dat_o = x"deadbeef" report "Read failed: unexpected data" severity warning; + wait until rising_edge(clk_i); + + -- simple read cycle + wait until rising_edge(clk_i); + stb_i <= '1' after 2 ns; + we_i <= '0' after 2 ns; + adr_i <= x"000011" after 2 ns; + wait until rising_edge(clk_i); + while ack_o = '0' loop + wait until rising_edge(clk_i); + end loop; + stb_i <= '0' after 2 ns; + assert dat_o = x"1234567" report "Read failed: unexpected data" severity warning; + wait until rising_edge(clk_i); + + assert false report "Test complete" severity failure; wait; end process WaveGen_Proc;