diff --git a/Makefile b/Makefile
index 9c4acae..29099b1 100755
--- a/Makefile
+++ b/Makefile
@@ -117,7 +117,7 @@ timing:	$(TWRFILE)
 #%.vhd:	%.psm
 #	../tools/picoasm/picoasm -t ../tools/picoasm/ROM_form.vhd -i $<
 
-src/wb_interconnect.vhd:	src/wishbone.defines
+src/wb_interconnect.vhd:	src/wishbone.defines tools/wishbone.pl
 	cd src && ../tools/wishbone.pl -nogui wishbone.defines
 
 coregen/%.vhd coregen/%.ngc:	coregen/%.xco coregen/coregen.cgp
diff --git a/planahead_postsynth.tcl b/planahead_postsynth.tcl
deleted file mode 100755
index 67f678f..0000000
--- a/planahead_postsynth.tcl
+++ /dev/null
@@ -1,4 +0,0 @@
-create_project -force -part xc3s700an-fgg484-4 postsynth planahead
-set_property design_mode GateLvl [current_fileset]
-import_files 2d_display_engine.ngc coregen/wb_ddr_ctrl_wb_from_ddr.ngc coregen/wb_ddr_ctrl_wb_to_ddr.ngc coregen/vga_pixeldata_fifo.ngc
-import_files -fileset constrs_1 constr/2d_display_engine.ucf constr/vhdl_bl4.ucf
diff --git a/src/cpu.vhd b/src/cpu.vhd
index 5615797..5424924 100644
--- a/src/cpu.vhd
+++ b/src/cpu.vhd
@@ -110,7 +110,6 @@ fill_fb : process(clk_i)
                 end if;
                 state <= S_WRITE1;
               else
-                adr <= 0;
                 state <= S_FLUSH1;
               end if;
             end if;
@@ -122,7 +121,7 @@ fill_fb : process(clk_i)
             wbm_o.we_o <= '1';
             wbm_o.sel_o <= (others => '1');
             wbm_o.adr_o <= std_logic_vector(to_unsigned(cc_adr,wbm_o.adr_o'length));
-            wbm_o.dat_o <= std_logic_vector(to_unsigned(adr*4,32));
+            wbm_o.dat_o <= x"00000002";
 
             state <= S_FLUSH2;
           when S_FLUSH2 =>
@@ -132,12 +131,7 @@ fill_fb : process(clk_i)
             if wbm_i.ack_i = '1' then
               wbm_o.stb_o <= '0';
               wbm_o.cyc_o <= '0';
-              if adr < 153583 then
-                adr <= adr + 16;
-                state <= S_FLUSH1;
-              else
-                state <= S_DONE;
-              end if;
+              state <= S_DONE;
             end if;
           when S_DONE =>
             null;
diff --git a/src/wb_ddr_ctrl_wb_sc.vhd b/src/wb_ddr_ctrl_wb_sc.vhd
index f07eeea..7052d20 100755
--- a/src/wb_ddr_ctrl_wb_sc.vhd
+++ b/src/wb_ddr_ctrl_wb_sc.vhd
@@ -171,7 +171,7 @@ begin
   ddr_be <= (others => '0');
   ddr_din <= cfe_mem_dat_o;
   ddr_adr_int(22 downto 3) <= vga_adr_reg when bus_owner = B_VGA else
-                              cfe_adr_reg when bus_owner = B_CFE;-- else
+                              cfe_adr_reg;-- when bus_owner = B_CFE else
                               --(others => dontcare);
   ddr_adr_int(2 downto 0) <= std_logic_vector(to_unsigned(out_ctr, 3));
   ddr_we_int <= '1' when bus_owner = B_CFE and cfe_wrrq_reg = '1' else
@@ -184,10 +184,10 @@ begin
                            '0';
 
   ddr_adr <= ddr_adr_int when in_read = '1' else
-             ddr_adr_dly(write_delay-1) when in_write = '1';-- else
+             ddr_adr_dly(write_delay-1);-- when in_write = '1' else
              --(others => dontcare);
   ddr_we <= ddr_we_int when in_read = '1' else
-            ddr_we_dly(write_delay-1) when in_write = '1';-- else
+            ddr_we_dly(write_delay-1);-- when in_write = '1' else
             --dontcare;
   fifo_to_ddr_write <= fifo_to_ddr_write_int when in_read = '1' else
                        fifo_to_ddr_write_dly(write_delay-1) and not fifo_to_ddr_full when in_write = '1' else
diff --git a/src/wishbone.defines b/src/wishbone.defines
index 63f9aaa..b17af96 100644
--- a/src/wishbone.defines
+++ b/src/wishbone.defines
@@ -78,14 +78,14 @@ slave ram
   lock_i=0
   err_o=0
   rty_o=0
-  baseadr=0x000800
+  baseadr=0x0000800
   size=0x800
 end slave ram
 
-# SDRAM controller memory port
-slave sdram_ctrl
+# SDRAM controller Cache control port
+slave sdram_ctrl_cc
   type=rw
-  adr_i_hi=25
+  adr_i_hi=2
   adr_i_lo=2
   tga_i=1
   tgc_i=1
@@ -93,14 +93,14 @@ slave sdram_ctrl
   lock_i=0
   err_o=0
   rty_o=0
-  baseadr=0x4000000
-  size=0x4000000
-end slave sdram_ctrl
+  baseadr=0x8000000
+  size=0x8
+end slave sdram_ctrl_cc
 
-# SDRAM controller Cache control port
-slave sdram_ctrl_cc
+# SDRAM controller memory port
+slave sdram_ctrl
   type=rw
-  adr_i_hi=2
+  adr_i_hi=25
   adr_i_lo=2
   tga_i=0
   tgc_i=0
@@ -108,6 +108,6 @@ slave sdram_ctrl_cc
   lock_i=0
   err_o=0
   rty_o=0
-  baseadr=0x8000000
-  size=0x10
-end slave sdram_ctrl_cc
\ No newline at end of file
+  baseadr=0x4000000
+  size=0x4000000
+end slave sdram_ctrl
diff --git a/tools/wishbone.pl b/tools/wishbone.pl
index b2dd301..8918b64 100755
--- a/tools/wishbone.pl
+++ b/tools/wishbone.pl
@@ -1,6 +1,6 @@
 #!/usr/bin/perl
 
-#use Tk;
+use Tk;
 use Time::Local;
 
 #
@@ -739,7 +739,7 @@ sub generate_defines {
   printf OUTFILE "adr_size=%s\n",$adr_size;
   printf OUTFILE "mux_type=%s\n",$mux_type;
   printf OUTFILE "interconnect=%s\n",$interconnect;
-  for ($i=1; $i le $masters; $i++) {
+  for ($i=1; $i <= $masters; $i++) {
     printf OUTFILE "\nmaster %s\n",$master[$i]{"wbm"};
     printf OUTFILE "  type=%s\n",$master[$i]{"type"};
     printf OUTFILE "  lock_o=%s\n",$master[$i]{"lock_o"};
@@ -751,13 +751,13 @@ sub generate_defines {
     if ($interconnect eq "sharedbus") {
       printf OUTFILE "  priority=%s\n",$master[$i]{"priority"};
     } else {
-      for ($j=1; $j le $slaves; $j++) {
+      for ($j=1; $j <= $slaves; $j++) {
         printf OUTFILE "  priority_%s=%s\n",$slave[$j]{"wbs"},$master[$i]{"priority_".($slave[$j]{"wbs"})};
       };
     };
     printf OUTFILE "end master %s\n",$master[$i]{"wbm"};
   };
-  for ($i=1; $i le $slaves; $i++) {
+  for ($i=1; $i <= $slaves; $i++) {
     printf OUTFILE "\nslave %s\n",$slave[$i]{"wbs"};
     printf OUTFILE "  type=%s\n",$slave[$i]{"type"};
     printf OUTFILE "  adr_i_hi=%s\n",$slave[$i]{"adr_i_hi"};
@@ -786,18 +786,18 @@ sub gen_header {
   $tmp=localtime(time);
   printf OUTFILE "%s Generated %s\n%s\n",$comment,$tmp,$comment;
   printf OUTFILE "%s Wishbone masters:\n",$comment;
-  for ($i=1; $i le $masters; $i++) {
+  for ($i=1; $i <= $masters; $i++) {
     printf OUTFILE "%s   %s\n",$comment,$master[$i]{"wbm"}; };
   printf OUTFILE "%s\n%s Wishbone slaves:\n",$comment,$comment;
-  for ($i=1; $i le $slaves; $i++) {
+  for ($i=1; $i <= $slaves; $i++) {
     printf OUTFILE "%s   %s\n",$comment,$slave[$i]{"wbs"};
-    if ($slave[$i]{"size"} ne ffffffff) {
+    if (hex($slave[$i]{"size"}) != hex(ffffffff)) {
       printf OUTFILE "%s     baseadr 0x%s - size 0x%s\n",$comment,$slave[$i]{"baseadr"},$slave[$i]{"size"}};
-    if ($slave[$i]{"size1"} ne ffffffff) {
+    if (hex($slave[$i]{"size1"}) != hex(ffffffff)) {
       printf OUTFILE "%s     baseadr 0x%s - size 0x%s\n",$comment,$slave[$i]{"baseadr1"},$slave[$i]{"size1"}};
-    if ($slave[$i]{"size2"} ne ffffffff) {
+    if (hex($slave[$i]{"size2"}) != hex(ffffffff)) {
       printf OUTFILE "%s     baseadr 0x%s - size 0x%s\n",$comment,$slave[$i]{"baseadr2"},$slave[$i]{"size2"}};
-    if ($slave[$i]{"size3"} ne ffffffff) {
+    if (hex($slave[$i]{"size3"}) != hex(ffffffff)) {
       printf OUTFILE "%s     baseadr 0x%s - size 0x%s\n",$comment,$slave[$i]{"baseadr3"},$slave[$i]{"size3"}};
   };
 };
@@ -809,12 +809,12 @@ sub gen_vhdl_package {
 
   # records ?
   if ($signal_groups eq 1) {
-    for ($i=1; $i le $masters; $i++) {
+    for ($i=1; $i <= $masters; $i++) {
       # input record
       printf OUTFILE "type %s_wbm_i_type is record\n",$master[$i]{"wbm"};
       if ($master[$i]{"type"} =~ /(ro|rw)/) { printf OUTFILE "  dat_i : std_logic_vector(%s downto 0);\n",$master[$i]{"dat_size"}-1;};
-      if ($master[$i]{"err_i"} eq 1) { printf OUTFILE "  err_i : std_logic;\n";};
-      if ($master[$i]{"rty_i"} eq 1) { printf OUTFILE "  rty_i : std_logic;\n";};
+      if ($master[$i]{"err_i"} == 1) { printf OUTFILE "  err_i : std_logic;\n";};
+      if ($master[$i]{"rty_i"} == 1) { printf OUTFILE "  rty_i : std_logic;\n";};
       printf OUTFILE "  ack_i : std_logic;\n";
       printf OUTFILE "end record;\n";
       # output record
@@ -822,39 +822,39 @@ sub gen_vhdl_package {
       if ($master[$i]{"type"} =~ /(wo|rw)/) {
         printf OUTFILE "  dat_o : std_logic_vector(%s downto 0);\n",$master[$i]{"dat_size"}-1;
         printf OUTFILE "  we_o  : std_logic;\n"; };
-      if ($dat_size eq 8) {
+      if ($dat_size == 8) {
         printf OUTFILE "  sel_o : std_logic;\n";
       } else {
         printf OUTFILE "  sel_o : std_logic_vector(%s downto 0);\n",$dat_size/8-1; };
       printf OUTFILE "  adr_o : std_logic_vector(%s downto 0);\n",$adr_size-1;
-      if ($master[$i]{"lock_o"} eq 1) { printf OUTFILE "  lock_o : std_logic;\n";};
-      if ($master[$i]{"tga_o"} eq 1) { printf OUTFILE "  %s_o : std_logic_vector(%s downto 0);\n",$rename_tga, $tga_bits-1;};
-      if ($master[$i]{"tgc_o"} eq 1) { printf OUTFILE "  %s_o : std_logic_vector(%s downto 0);\n",$rename_tgc, $tgc_bits-1;};
+      if ($master[$i]{"lock_o"} == 1) { printf OUTFILE "  lock_o : std_logic;\n";};
+      if ($master[$i]{"tga_o"} == 1) { printf OUTFILE "  %s_o : std_logic_vector(%s downto 0);\n",$rename_tga, $tga_bits-1;};
+      if ($master[$i]{"tgc_o"} == 1) { printf OUTFILE "  %s_o : std_logic_vector(%s downto 0);\n",$rename_tgc, $tgc_bits-1;};
       printf OUTFILE "  cyc_o : std_logic;\n";
       printf OUTFILE "  stb_o : std_logic;\n";
       printf OUTFILE "end record;\n\n";
     }; #end for
-    for ($i=1; $i le $slaves; $i++) {
+    for ($i=1; $i <= $slaves; $i++) {
       # input record
       printf OUTFILE "type %s_wbs_i_type is record\n",$slave[$i]{"wbs"};
       if ($slave[$i]{"type"} ne "ro") {
         printf OUTFILE "  dat_i : std_logic_vector(%s downto 0);\n",$slave[$i]{"dat_size"}-1;
         printf OUTFILE "  we_i  : std_logic;\n"; };
-      if ($dat_size eq 8) {
+      if ($dat_size == 8) {
         printf OUTFILE "  sel_i : std_logic;\n";
       } else {
         printf OUTFILE "  sel_i : std_logic_vector(%s downto 0);\n",$dat_size/8-1; };
-      if ($slave[$i]{"adr_i_hi"} gt 0) { printf OUTFILE "  adr_i : std_logic_vector(%s downto %s);\n",$slave[$i]{"adr_i_hi"},$slave[$i]{"adr_i_lo"};};
-      if ($slave[$i]{"tga_i"} eq 1) { printf OUTFILE "  %s_i : std_logic_vector(%s downto 0);\n",$rename_tga,$tga_bits-1; };
-      if ($slave[$i]{"tgc_i"} eq 1) { printf OUTFILE "  %s_i : std_logic_vector(%s downto 0);\n",$rename_tgc,$tgc_bits-1; };
+      if ($slave[$i]{"adr_i_hi"} > 0) { printf OUTFILE "  adr_i : std_logic_vector(%s downto %s);\n",$slave[$i]{"adr_i_hi"},$slave[$i]{"adr_i_lo"};};
+      if ($slave[$i]{"tga_i"} == 1) { printf OUTFILE "  %s_i : std_logic_vector(%s downto 0);\n",$rename_tga,$tga_bits-1; };
+      if ($slave[$i]{"tgc_i"} == 1) { printf OUTFILE "  %s_i : std_logic_vector(%s downto 0);\n",$rename_tgc,$tgc_bits-1; };
       printf OUTFILE "  cyc_i : std_logic;\n";
       printf OUTFILE "  stb_i : std_logic;\n";
       printf OUTFILE "end record;\n";
       # output record
       printf OUTFILE "type %s_wbs_o_type is record\n",$slave[$i]{"wbs"};
       if ($slave[$i]{"type"} =~ /(ro|rw)/) { printf OUTFILE "  dat_o : std_logic_vector(%s downto 0);\n",$slave[$i]{"dat_size"}-1 };
-      if ($slave[$i]{"rty_o"} eq 1) { printf OUTFILE "  rty_o : std_logic;\n" };
-      if ($slave[$i]{"err_o"} eq 1) { printf OUTFILE "  err_o : std_logic;\n" };
+      if ($slave[$i]{"rty_o"} == 1) { printf OUTFILE "  rty_o : std_logic;\n" };
+      if ($slave[$i]{"err_o"} == 1) { printf OUTFILE "  err_o : std_logic;\n" };
       printf OUTFILE "  ack_o : std_logic;\n";
       printf OUTFILE "end record;\n";
     }; #end for
@@ -1028,14 +1028,14 @@ sub gen_entity {
   if ($signal_groups eq 1) {
     # master port(s)
     printf OUTFILE "  -- wishbone master port(s)\n";
-    for ($i=1; $i le $masters; $i++) {
+    for ($i=1; $i <= $masters; $i++) {
  	    printf OUTFILE "  -- %s\n",$master[$i]{"wbm"};
       printf OUTFILE "  %s_wbm_i : out %s_wbm_i_type;\n",$master[$i]{"wbm"},$master[$i]{"wbm"};
       printf OUTFILE "  %s_wbm_o : in  %s_wbm_o_type;\n",$master[$i]{"wbm"},$master[$i]{"wbm"};
     }; #end for
     # slave port(s)
     printf OUTFILE "  -- wishbone slave port(s)\n";
-    for ($i=1; $i le $slaves; $i++) {
+    for ($i=1; $i <= $slaves; $i++) {
       printf OUTFILE "  -- %s\n",$slave[$i]{"wbs"};
       printf OUTFILE "  %s_wbs_i : out %s_wbs_i_type;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"};
       printf OUTFILE "  %s_wbs_o : in %s_wbs_o_type;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"};
@@ -1043,7 +1043,7 @@ sub gen_entity {
   # separate signals
   } else {
     printf OUTFILE "  -- wishbone master port(s)\n";
-    for ($i=1; $i le $masters; $i++) {
+    for ($i=1; $i <= $masters; $i++) {
       printf OUTFILE "  -- %s\n",$master[$i]{"wbm"};
       if ($master[$i]{"type"} ne "wo") {
         printf OUTFILE "  %s_dat_i : out std_logic_vector(%s downto 0);\n",$master[$i]{"wbm"},$dat_size-1; };
@@ -1056,7 +1056,7 @@ sub gen_entity {
         printf OUTFILE "  %s_dat_o : in  std_logic_vector(%s downto 0);\n",$master[$i]{"wbm"},$dat_size-1;
         printf OUTFILE "  %s_we_o  : in  std_logic;\n",$master[$i]{"wbm"};
       };
-      if ($dat_size ge 16) {
+      if ($dat_size >= 16) {
         printf OUTFILE "  %s_sel_o : in  std_logic_vector(%s downto 0);\n",$master[$i]{"wbm"},$dat_size/8-1; };
       printf OUTFILE "  %s_adr_o : in  std_logic_vector(%s downto 0);\n",$master[$i]{"wbm"},$adr_size-1;
       if ($master[$i]{"tgc_o"} eq 1) {
@@ -1067,7 +1067,7 @@ sub gen_entity {
       printf OUTFILE "  %s_stb_o : in  std_logic;\n",$master[$i]{"wbm"};
     };
     printf OUTFILE "  -- wishbone slave port(s)\n";
-    for ($i=1; $i le $slaves; $i++) {
+    for ($i=1; $i <= $slaves; $i++) {
       printf OUTFILE "  -- %s\n",$slave[$i]{"wbs"};
       if ($slave[$i]{"type"} ne "wo") {
         printf OUTFILE "  %s_dat_o : in  std_logic_vector(%s downto 0);\n",$slave[$i]{"wbs"},$dat_size-1; };
@@ -1080,7 +1080,7 @@ sub gen_entity {
         printf OUTFILE "  %s_dat_i : out std_logic_vector(%s downto 0);\n",$slave[$i]{"wbs"},$dat_size-1;
         printf OUTFILE "  %s_we_i  : out std_logic;\n",$slave[$i]{"wbs"};
       };
-      if ($dat_size ge 16) {
+      if ($dat_size >= 16) {
         printf OUTFILE "  %s_sel_i : out std_logic_vector(%s downto 0);\n",$slave[$i]{"wbs"},$dat_size/8-1; };
       printf OUTFILE "  %s_adr_i : out std_logic_vector(%s downto %s);\n",$slave[$i]{"wbs"},$slave[$i]{"adr_i_hi"},$slave[$i]{"adr_i_lo"};
       if ($slave[$i]{"tgc_i"} eq 1) {
@@ -1102,19 +1102,19 @@ sub gen_entity {
 # generate signals for remapping (for records)
 sub gen_sig_remap {
   sub gen_sig_dec {
-    if ($_[1] gt 0) {
+    if ($_[1] > 0) {
       printf OUTFILE "  signal %s : std_logic_vector(%s downto %s);\n",$_[0],$_[1]-1,$_[2];
     } else {
       printf OUTFILE "  signal %s : std_logic;\n",$_[0];
     };
   };
-    for ($i=1; $i le $masters; $i++) {
+    for ($i=1; $i <= $masters; $i++) {
       if ($master[$i]{"type"} ne "wo") {
         gen_sig_dec($master[$i]{"wbm"}.'_dat_i',$dat_size,0); };
       gen_sig_dec($master[$i]{"wbm"}.'_ack_i');
-      if ($master[$i]{"err_i"} eq 1) {
+      if ($master[$i]{"err_i"} == 1) {
         gen_sig_dec($master[$i]{"wbm"}.'_err_i'); };
-      if ($master[$i]{"rty_i"} eq 1) {
+      if ($master[$i]{"rty_i"} == 1) {
         gen_sig_dec($master[$i]{"wbm"}.'_rty_i') };
       if ($master[$i]{"type"} ne "ro") {
         gen_sig_dec($master[$i]{"wbm"}.'_dat_o',$dat_size,0);
@@ -1132,13 +1132,13 @@ sub gen_sig_remap {
       gen_sig_dec($master[$i]{"wbm"}.'_cyc_o');
       gen_sig_dec($master[$i]{"wbm"}.'_stb_o');
     };
-    for ($i=1; $i le $slaves; $i++) {
+    for ($i=1; $i <= $slaves; $i++) {
       if ($slave[$i]{"type"} ne "wo") {
         gen_sig_dec($slave[$i]{"wbs"}.'_dat_o',$dat_size,0); };
       gen_sig_dec($slave[$i]{"wbs"}.'_ack_o');
-      if ($slave[$i]{"err_o"} eq 1) {
+      if ($slave[$i]{"err_o"} == 1) {
         gen_sig_dec($slave[$i]{"wbs"}.'_err_o'); };
-      if ($slave[$i]{"rty_o"} eq 1) {
+      if ($slave[$i]{"rty_o"} == 1) {
         gen_sig_dec($slave[$i]{"wbs"}.'_rty_o'); };
       if ($slave[$i]{"type"} ne "ro") {
         gen_sig_dec($slave[$i]{"wbs"}.'_dat_i',$dat_size,0);
@@ -1147,11 +1147,11 @@ sub gen_sig_remap {
       if ($dat_size > 8) {
         gen_sig_dec($slave[$i]{"wbs"}.'_sel_i',$dat_size/8,0); };
       gen_sig_dec($slave[$i]{"wbs"}.'_adr_i',$slave[$i]{"adr_i_hi"}+1,$slave[$i]{"adr_i_lo"});
-      if ($slave[$i]{"tga_i"} eq 1) {
+      if ($slave[$i]{"tga_i"} == 1) {
         gen_sig_dec($slave[$i]{"wbs"}.'_'.$rename_tga.'_i',$tga_bits,0); };
-      if ($slave[$i]{"tgc_i"} eq 1) {
+      if ($slave[$i]{"tgc_i"} == 1) {
         gen_sig_dec($slave[$i]{"wbs"}.'_'.$rename_tgc.'_i',$tgc_bits,0); };
-      if ($slave[$i]{"tgd_i"} eq 1) {
+      if ($slave[$i]{"tgd_i"} == 1) {
         gen_sig_dec($slave[$i]{"wbs"}.'_'.$rename_tgd.'_i',$tgd_bits,0); };
       gen_sig_dec($slave[$i]{"wbs"}.'_cyc_i');
       gen_sig_dec($slave[$i]{"wbs"}.'_stb_i');
@@ -1162,21 +1162,21 @@ sub gen_global_signals {
   # single master
   if ($masters eq 1) {
     # slave select for generation of stb_i to slaves
-    for ($i=1; $i le $slaves; $i++) {
+    for ($i=1; $i <= $slaves; $i++) {
       printf OUTFILE "  signal %s_ss : std_logic; -- slave select\n",$slave[$i]{"wbs"}; };
   # shared bus
   } elsif ($interconnect eq "sharedbus") {
     # bus grant
-    for ($i=1; $i le $masters; $i++) {
+    for ($i=1; $i <= $masters; $i++) {
       printf OUTFILE "  signal %s_bg : std_logic; -- bus grant\n",$master[$i]{"wbm"}; };
     # slave select for generation of stb_i to slaves
-    for ($i=1; $i le $slaves; $i++) {
+    for ($i=1; $i <= $slaves; $i++) {
       printf OUTFILE "  signal %s_ss : std_logic; -- slave select\n",$slave[$i]{"wbs"}; };
   # crossbarswitch
   } else {
-    for ($i=1; $i le $masters; $i++) {
-      for ($j=1; $j le $slaves; $j++) {
-        if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
+    for ($i=1; $i <= $masters; $i++) {
+      for ($j=1; $j <= $slaves; $j++) {
+        if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} != 0) {
           printf OUTFILE "  signal %s_%s_ss : std_logic; -- slave select\n",$master[$i]{"wbm"},$slave[$j]{"wbs"};
           printf OUTFILE "  signal %s_%s_bg : std_logic; -- bus grant\n",$master[$i]{"wbm"},$slave[$j]{"wbs"};
         };
@@ -1187,25 +1187,25 @@ sub gen_global_signals {
 
 sub gen_arbiter {
   # out: wbm_bg (bus grant)
-  if ($masters eq 1) {
+  if ($masters == 1) {
     # ack_i
     # cyc_i
     # printf OUTFILE "%s_bg <= %s_cyc_o;\n",$master[1]{"wbm"},$master[1]{"wbm"};
   # sharedbus
   } elsif ($interconnect eq "sharedbus") {
     printf OUTFILE "arbiter_sharedbus: block\n";
-    for ($i=1; $i le $masters; $i++) {
+    for ($i=1; $i <= $masters; $i++) {
       printf OUTFILE "  signal %s_bg_1, %s_bg_2, %s_bg_q : std_logic;\n",$master[$i]{"wbm"},$master[$i]{"wbm"},$master[$i]{"wbm"}; };
-    for ($i=1; $i le $masters; $i++) {
+    for ($i=1; $i <= $masters; $i++) {
       printf OUTFILE "  signal %s_trafic_ctrl_limit : std_logic;\n",$master[$i]{"wbm"}; };
     printf OUTFILE "  signal ack, ce, idle :std_logic;\n";
     printf OUTFILE "begin -- arbiter\n";
     printf OUTFILE "ack <= %s_ack_o",$slave[1]{"wbs"};
-    for ($i=2; $i le $slaves; $i++) {
+    for ($i=2; $i <= $slaves; $i++) {
       printf OUTFILE " or %s_ack_o",$slave[$i]{"wbs"}; };
     printf OUTFILE ";\n";
     # instantiate trafic_supervision(s)
-    for ($i=1; $i le $masters; $i++) {
+    for ($i=1; $i <= $masters; $i++) {
       printf OUTFILE "\ntrafic_supervision_%s : entity work.trafic_supervision\n",$i;
       printf OUTFILE "generic map(\n";
       printf OUTFILE "  priority => %s,\n",$master[$i]{"priority"};
@@ -1219,51 +1219,51 @@ sub gen_arbiter {
     # _bg_q
     # bg eq 1 => set
     # end of cycle => reset
-    for ($i=1; $i le $masters; $i++) {
+    for ($i=1; $i <= $masters; $i++) {
       printf OUTFILE "\nprocess(clk,reset)\nbegin\nif reset='1' then\n";
       printf OUTFILE "  %s_bg_q <= '0';\n",$master[$i]{"wbm"};
       printf OUTFILE "elsif clk'event and clk='1' then\n";
       printf OUTFILE "if %s_bg_q='0' then\n",$master[$i]{"wbm"};
       printf OUTFILE "  %s_bg_q <= %s_bg;\n",$master[$i]{"wbm"},$master[$i]{"wbm"};
       printf OUTFILE "elsif ack='1'";
-      if ($master[$i]{"tgc_o"} eq 1) {
+      if ($master[$i]{"tgc_o"} == 1) {
         printf OUTFILE " and (%s_%s_o=\"%s\" or %s_%s_o=\"%s\")",$master[$i]{"wbm"},$rename_tgc,$classic,$master[$i]{"wbm"},$rename_tgc,$endofburst; };
       printf OUTFILE " then\n  %s_bg_q <= '0';\nend if;\nend if;\nend process;\n",$master[$i]{"wbm"};
     }; # end for
     # _bg
     printf OUTFILE "\nidle <= '1' when %s_bg_q='0'",$master[1]{"wbm"};
-    for ($i=2; $i le $masters; $i++) {
+    for ($i=2; $i <= $masters; $i++) {
       printf OUTFILE " and %s_bg_q='0'",$master[$i]{"wbm"}; };
     printf OUTFILE " else '0';\n";
     printf OUTFILE "%s_bg_1 <= '1' when idle='1' and %s_cyc_o='1' and %s_trafic_ctrl_limit='0' else '0';\n",$master[1]{"wbm"},$master[1]{"wbm"},$master[1]{"wbm"};
     $depend = $master[1]{"wbm"}."_bg_1='0'";
-    for ($i=2; $i le $masters; $i++) {
+    for ($i=2; $i <= $masters; $i++) {
       printf OUTFILE "%s_bg_1 <= '1' when idle='1' and %s_cyc_o='1' and %s_trafic_ctrl_limit='0' and (%s) else '0';\n",$master[$i]{"wbm"},$master[$i]{"wbm"},$master[$i]{"wbm"},$depend;
       $depend = $depend." and ".$master[$i]{"wbm"}."_bg_1='0'";
     };
 
     printf OUTFILE "%s_bg_2 <= '1' when idle='1' and (%s) and %s_cyc_o='1' else '0';\n",$master[1]{"wbm"},$depend,$master[1]{"wbm"};
     $depend = $depend." and ".$master[1]{"wbm"}."_bg_2='0'";
-    for ($i=2; $i le $masters; $i++) {
+    for ($i=2; $i <= $masters; $i++) {
       printf OUTFILE "%s_bg_2 <= '1' when idle='1' and (%s) and %s_cyc_o='1' else '0';\n",$master[$i]{"wbm"},$depend,$master[$i]{"wbm"}; 
       $depend = $depend." and ".$master[$i]{"wbm"}."_bg_2='0'";
     };
-    for ($i=1; $i le $masters; $i++) {
+    for ($i=1; $i <= $masters; $i++) {
       printf OUTFILE "%s_bg <= %s_bg_q or %s_bg_1 or %s_bg_2;\n",$master[$i]{"wbm"},$master[$i]{"wbm"},$master[$i]{"wbm"},$master[$i]{"wbm"}; };
     # ce
     printf OUTFILE "ce <= %s_cyc_o",$master[1]{"wbm"};
-    for ($i=2; $i le $masters; $i++) {
+    for ($i=2; $i <= $masters; $i++) {
       printf OUTFILE " or %s_cyc_o",$master[$i]{"wbm"}; };
     printf OUTFILE " when idle='1' else '0';\n\n";
     # thats it
     printf OUTFILE "end block arbiter_sharedbus;\n\n";
   # interconnect crossbarswitch
   } else {
-    for ($j=1; $j le $slaves; $j++) {
+    for ($j=1; $j <= $slaves; $j++) {
       # single master ?
       $tmp=0;
-      for ($l=1; $l le $masters; $l++) {
-        if ($master[$l]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
+      for ($l=1; $l <= $masters; $l++) {
+        if ($master[$l]{("priority_".($slave[$j]{"wbs"}))} != 0) {
           $only_master = $l;
           $tmp++;
         };
@@ -1272,8 +1272,8 @@ sub gen_arbiter {
         printf OUTFILE "%s_%s_bg <= %s_%s_ss and %s_cyc_o;\n",$master[$only_master]{"wbm"},$slave[$j]{"wbs"},$master[$only_master]{"wbm"},$slave[$j]{"wbs"},$master[$only_master]{"wbm"};
       } else {
         printf OUTFILE "arbiter_%s : block\n",$slave[$j]{"wbs"};
-        for ($i=1; $i le $masters; $i++) {
-          if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
+        for ($i=1; $i <= $masters; $i++) {
+          if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} != 0) {
             printf OUTFILE "  signal %s_bg, %s_bg_1, %s_bg_2, %s_bg_q : std_logic;\n",$master[$i]{"wbm"},$master[$i]{"wbm"},$master[$i]{"wbm"},$master[$i]{"wbm"};
             printf OUTFILE "  signal %s_trafic_limit : std_logic;\n",$master[$i]{"wbm"};
           };
@@ -1284,10 +1284,10 @@ sub gen_arbiter {
         # instantiate trafic_supervision(s)
         # calc tot priority per slave
         $priority = 0;
-        for ($i=1; $i le $masters; $i++) {
+        for ($i=1; $i <= $masters; $i++) {
           $priority += $master[$i]{("priority_".($slave[$j]{"wbs"}))}; };
-        for ($i=1; $i le $masters; $i++) {
-          if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
+        for ($i=1; $i <= $masters; $i++) {
+          if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} != 0) {
             printf OUTFILE "\ntrafic_supervision_%s : entity work.trafic_supervision\n",$i;
             printf OUTFILE "generic map(\n";
             printf OUTFILE "  priority => %s,\n",$master[$i]{("priority_".($slave[$j]{"wbs"}))};
@@ -1303,33 +1303,33 @@ sub gen_arbiter {
         # _bg_q
         # bg eq 1 => set
         # end of cycle => reset
-        for ($i=1; $i le $masters; $i++) {
-          if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
+        for ($i=1; $i <= $masters; $i++) {
+          if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} != 0) {
             printf OUTFILE "\nprocess(clk,reset)\nbegin\nif reset='1' then\n";
             printf OUTFILE "  %s_bg_q <= '0';\n",$master[$i]{"wbm"};
             printf OUTFILE "elsif clk'event and clk='1' then\n";
             printf OUTFILE "if %s_bg_q='0' then\n",$master[$i]{"wbm"};
             printf OUTFILE "  %s_bg_q <= %s_bg;\n",$master[$i]{"wbm"},$master[$i]{"wbm"};
             printf OUTFILE "elsif ack='1'";
-            if ($master[$i]{"tgc_o"} eq 1) {
+            if ($master[$i]{"tgc_o"} == 1) {
               printf OUTFILE " and (%s_%s_o=\"%s\" or %s_%s_o=\"%s\")",$master[$i]{"wbm"},$rename_tgc,$classic,$master[$i]{"wbm"},$rename_tgc,$endofburst; };
             printf OUTFILE " then\n  %s_bg_q <= '0';\nend if;\nend if;\nend process;\n",$master[$i]{"wbm"};
           };
         }; # end for
         # _bg
 	$depend = "";
-        $tmp=1; until ($master[$tmp]{("priority_".($slave[$j]{"wbs"}))} ne 0) {$tmp++};
+        $tmp=1; until ($master[$tmp]{("priority_".($slave[$j]{"wbs"}))} != 0) {$tmp++};
         printf OUTFILE "\nidle <= '1' when %s_bg_q='0'",$master[$tmp]{"wbm"};
-        for ($i=$tmp+1; $i le $masters; $i++) {
-          if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
+        for ($i=$tmp+1; $i <= $masters; $i++) {
+          if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} != 0) {
             printf OUTFILE " and %s_bg_q='0'",$master[$i]{"wbm"};
           };
         };
         printf OUTFILE " else '0';\n";
         printf OUTFILE "%s_bg_1 <= '1' when idle='1' and %s_cyc_o='1' and %s_%s_ss='1' and %s_trafic_limit='0' else '0';\n",$master[$tmp]{"wbm"},$master[$tmp]{"wbm"},$master[$tmp]{"wbm"},$slave[$j]{"wbs"},$master[$tmp]{"wbm"};
 	$depend = $master[$tmp]{"wbm"}."_bg_1='0'",;
-        for ($i=$tmp+1; $i le $masters; $i++) {
-          if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
+        for ($i=$tmp+1; $i <= $masters; $i++) {
+          if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} != 0) {
 	    printf OUTFILE "%s_bg_1 <= '1' when idle='1' and (%s) and %s_cyc_o='1' and %s_%s_ss='1' and %s_trafic_limit='0' else '0';\n",$master[$i]{"wbm"},$depend,$master[$i]{"wbm"},$master[$i]{"wbm"},$slave[$j]{"wbs"},$master[$i]{"wbm"},$slave[$j]{"wbs"},$master[$i]{"wbm"};;
 	    $depend = $depend." and ".$master[$i]{"wbm"}."_bg_1='0'";
           };
@@ -1337,29 +1337,29 @@ sub gen_arbiter {
         printf OUTFILE "%s_bg_2 <= '1' when idle='1' and (%s) and %s_cyc_o='1' and %s_%s_ss='1' else '0';\n",$master[$tmp]{"wbm"},$depend,$master[$tmp]{"wbm"},$master[$tmp]{"wbm"},$slave[$j]{"wbs"};
         $depend = $depend." and ".$master[$tmp]{"wbm"}."_bg_2='0'";
         $tmp1 = $tmp;
-        for ($i=$tmp+1; $i le $masters; $i++) {
-          if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
+        for ($i=$tmp+1; $i <= $masters; $i++) {
+          if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} != 0) {
             printf OUTFILE "%s_bg_2 <= '1' when idle='1' and (%s) and %s_cyc_o='1' and %s_%s_ss='1' else '0';\n",$master[$i]{"wbm"},$depend,$master[$i]{"wbm"},$master[$i]{"wbm"},$slave[$j]{"wbs"};
           $depend = $depend." and ".$master[$i]{"wbm"}."_bg_2='0'";
           };
         };
-        for ($i=1; $i le $masters; $i++) {
-          if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
+        for ($i=1; $i <= $masters; $i++) {
+          if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} != 0) {
             printf OUTFILE "%s_bg <= %s_bg_q or %s_bg_1 or %s_bg_2;\n",$master[$i]{"wbm"},$master[$i]{"wbm"},$master[$i]{"wbm"},$master[$i]{"wbm"};
           };
         };
         # ce
-        $tmp=1; until ($master[$tmp]{("priority_".($slave[$j]{"wbs"}))} ne 0) {$tmp++};
+        $tmp=1; until ($master[$tmp]{("priority_".($slave[$j]{"wbs"}))} != 0) {$tmp++};
         printf OUTFILE "ce <= (%s_cyc_o and %s_%s_ss)",$master[$tmp]{"wbm"},$master[$tmp]{"wbm"},$slave[$j]{"wbs"};
-          for ($i=$tmp+1; $i le $masters; $i++) {
-            if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
+          for ($i=$tmp+1; $i <= $masters; $i++) {
+            if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} != 0) {
               printf OUTFILE " or (%s_cyc_o and %s_%s_ss)",$master[$i]{"wbm"},$master[$i]{"wbm"},$slave[$j]{"wbs"};
             };
           };
         printf OUTFILE " when idle='1' else '0';\n";
         # global bg
-        for ($i=1; $i le $masters; $i++) {
-          if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
+        for ($i=1; $i <= $masters; $i++) {
+          if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} != 0) {
             printf OUTFILE "%s_%s_bg <= %s_bg;\n",$master[$i]{"wbm"},$slave[$j]{"wbs"},$master[$i]{"wbm"};
           };
         };
@@ -1376,16 +1376,16 @@ sub gen_adr_decoder{
     printf OUTFILE "begin\n";
     # adr
     printf OUTFILE "adr <= (%s_adr_o and %s_bg)",$master[1]{"wbm"},$master[1]{"wbm"};
-    if ($masters gt 1){
-      for ($i=2; $i le $masters; $i++) {
+    if ($masters > 1){
+      for ($i=2; $i <= $masters; $i++) {
         printf OUTFILE " or (%s_adr_o and %s_bg)",$master[$i]{"wbm"},$master[$i]{"wbm"}; };
     };
     printf OUTFILE ";\n";
     # slave select
-    for ($i=1; $i le $slaves; $i++) {
+    for ($i=1; $i <= $slaves; $i++) {
       printf OUTFILE "%s_ss <= '1' when adr(%s downto %s)=\"",$slave[$i]{"wbs"}, $adr_size-1,log(hex($slave[$i]{"size"}))/log(2);
       $slave[$i]{"baseadr"}=hex($slave[$i]{"baseadr"});
-      for ($j=$adr_size-1; $j ge (log(hex($slave[$i]{"size"}))/log(2)); $j--) {
+      for ($j=$adr_size-1; $j >= (log(hex($slave[$i]{"size"}))/log(2)); $j--) {
         if (($slave[$i]{"baseadr"}) >= (2**$j)) {
           $slave[$i]{"baseadr"} -= 2**$j;
           printf OUTFILE "1";
@@ -1395,10 +1395,10 @@ sub gen_adr_decoder{
       };
       printf OUTFILE "\"";
       # 1
-      if ($slave[$i]{"size1"} ne "ffffffff") {
+      if (hex($slave[$i]{"size1"}) != hex("ffffffff")) {
         printf OUTFILE " else\n'1' when adr(%s downto %s)=\"",$adr_size-1,log(hex($slave[$i]{"size1"}))/log(2);
         $slave[$i]{"baseadr1"}=hex($slave[$i]{"baseadr1"});
-        for ($j=$adr_size-1; $j ge (log(hex($slave[$i]{"size1"}))/log(2)); $j--) {
+        for ($j=$adr_size-1; $j >= (log(hex($slave[$i]{"size1"}))/log(2)); $j--) {
 		      if (($slave[$i]{"baseadr1"}) >= (2**$j)) {
             $slave[$i]{"baseadr1"} -= 2**$j;
             printf OUTFILE "1";
@@ -1409,10 +1409,10 @@ sub gen_adr_decoder{
         printf OUTFILE "\"";
       };
       # 2
-      if ($slave[$i]{"size2"} ne "ffffffff") {
+      if (hex($slave[$i]{"size2"}) != hex("ffffffff")) {
         printf OUTFILE " else\n'1' when adr(%s downto %s)=\"",$adr_size-1,log(hex($slave[$i]{"size2"}))/log(2);
         $slave[$i]{"baseadr2"}=hex($slave[$i]{"baseadr2"});
-        for ($j=$adr_size-1; $j ge (log(hex($slave[$i]{"size2"}))/log(2)); $j--) {
+        for ($j=$adr_size-1; $j >= (log(hex($slave[$i]{"size2"}))/log(2)); $j--) {
 		      if (($slave[$i]{"baseadr2"}) >= (2**$j)) {
 		        $slave[$i]{"baseadr2"} -= 2**$j;
 		        printf OUTFILE "1";
@@ -1423,10 +1423,10 @@ sub gen_adr_decoder{
         printf OUTFILE "\"";
       };
       # 3
-      if ($slave[$i]{"size3"} ne "ffffffff") {
+      if (hex($slave[$i]{"size3"}) != hex("ffffffff")) {
         printf OUTFILE " else\n'1' when adr(%s downto %s)=\"",$adr_size-1,log(hex($slave[$i]{"size3"}))/log(2);
         $slave[$i]{"baseadr3"}=hex($slave[$i]{"baseadr3"});
-        for ($j=$adr_size-1; $j ge (log(hex($slave[$i]{"size3"}))/log(2)); $j--) {
+        for ($j=$adr_size-1; $j >= (log(hex($slave[$i]{"size3"}))/log(2)); $j--) {
 		      if (($slave[$i]{"baseadr3"}) >= (2**$j)) {
             $slave[$i]{"baseadr3"} -= 2**$j;
 		        printf OUTFILE "1";
@@ -1439,20 +1439,20 @@ sub gen_adr_decoder{
       printf OUTFILE " else\n'0';\n";
       # adr to slaves
     };
-    for ($i=1; $i le $slaves; $i++) {
+    for ($i=1; $i <= $slaves; $i++) {
       printf OUTFILE "%s_adr_i <= adr(%s downto %s);\n",$slave[$i]{"wbs"},$slave[$i]{"adr_i_hi"},$slave[$i]{"adr_i_lo"}; };
   # crossbar switch
   } else {
     printf OUTFILE "begin\n";
     # master_slave_ss
 #    $j=0;
-    for ($i=1; $i le $masters; $i++) {
+    for ($i=1; $i <= $masters; $i++) {
       $slave[$j]{"baseadr"}=hex($slave[$j]{"baseadr"});
-      for ($j=1; $j le $slaves; $j++) {
-        if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
+      for ($j=1; $j <= $slaves; $j++) {
+        if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} != 0) {
         printf OUTFILE "%s_%s_ss <= '1' when %s_adr_o(%s downto %s)=\"",$master[$i]{"wbm"},$slave[$j]{"wbs"},$master[$i]{"wbm"},$adr_size-1,log(hex($slave[$j]{"size"}))/log(2);
         $tmp=hex($slave[$j]{"baseadr"});
-        for ($k=$adr_size-1; $k ge (log(hex($slave[$j]{"size"}))/log(2)); $k--) {
+        for ($k=$adr_size-1; $k >= (log(hex($slave[$j]{"size"}))/log(2)); $k--) {
           if ($tmp >= (2**$k)) {
             $tmp -= 2**$k;
             printf OUTFILE "1";
@@ -1462,10 +1462,10 @@ sub gen_adr_decoder{
         };
         printf OUTFILE "\"";
         # 2?
-        if ($slave[$j]{"size1"} ne "ffffffff") {
+        if (hex($slave[$j]{"size1"}) != hex("ffffffff")) {
           printf OUTFILE " else\n'1' when %s_adr_o(%s downto %s)=\"",$master[$i]{"wbm"},$adr_size-1,log(hex($slave[$j]{"size1"}))/log(2);
           $tmp=hex($slave[$j]{"baseadr1"});
-          for ($k=$adr_size-1; $k ge (log(hex($slave[$j]{"size1"}))/log(2)); $k--) {
+          for ($k=$adr_size-1; $k >= (log(hex($slave[$j]{"size1"}))/log(2)); $k--) {
 		        if ($tmp >= (2**$k)) {
 		          $tmp -= 2**$k;
 		          printf OUTFILE "1";
@@ -1476,10 +1476,10 @@ sub gen_adr_decoder{
           printf OUTFILE "\"";
         };
         # 3?
-        if ($slave[$j]{"size2"} ne "ffffffff") {
+        if (hex($slave[$j]{"size2"}) != hex("ffffffff")) {
           printf OUTFILE " else\n'1' when %s_adr_o(%s downto %s)=\"",$master[$i]{"wbm"},$adr_size-1,log(hex($slave[$j]{"size2"}))/log(2);
           $tmp=hex($slave[$j]{"baseadr2"});
-          for ($k=$adr_size-1; $k ge (log(hex($slave[$j]{"size2"}))/log(2)); $k--) {
+          for ($k=$adr_size-1; $k >= (log(hex($slave[$j]{"size2"}))/log(2)); $k--) {
 		        if ($tmp >= (2**$k)) {
 		          $tmp -= 2**$k;
 		          printf OUTFILE "1";
@@ -1494,22 +1494,22 @@ sub gen_adr_decoder{
       };
     };
     # _adr_o
-    for ($i=1; $i le $slaves; $i++) {
+    for ($i=1; $i <= $slaves; $i++) {
       # mux ?
       $tmp=0;
-      for ($l=1; $l le $masters; $l++) {
-        if ($master[$l]{("priority_".($slave[$i]{"wbs"}))} ne 0) {
+      for ($l=1; $l <= $masters; $l++) {
+        if ($master[$l]{("priority_".($slave[$i]{"wbs"}))} != 0) {
           $tmp++;
         };
       };
       if ($tmp eq 1) {
-        $k=1; until ($master[$k]{("priority_".($slave[$i]{"wbs"}))} ne 0) {$k++};
+        $k=1; until ($master[$k]{("priority_".($slave[$i]{"wbs"}))} != 0) {$k++};
         printf OUTFILE "%s_adr_i <= %s_adr_o(%s downto %s);\n",$slave[$i]{"wbs"},$master[$k]{"wbm"},$slave[$i]{"adr_i_hi"},$slave[$i]{"adr_i_lo"};
       } else {
-        $k=1; until ($master[$k]{("priority_".($slave[$i]{"wbs"}))} ne 0) {$k++};
+        $k=1; until ($master[$k]{("priority_".($slave[$i]{"wbs"}))} != 0) {$k++};
         printf OUTFILE "%s_adr_i <= (%s_adr_o(%s downto %s) and %s_%s_bg)",$slave[$i]{"wbs"},$master[$k]{"wbm"},$slave[$i]{"adr_i_hi"},$slave[$i]{"adr_i_lo"},$master[$k]{"wbm"},$slave[$i]{"wbs"};
-        for ($j=$k+1; $j le $masters; $j++) {
-          if ($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) {
+        for ($j=$k+1; $j <= $masters; $j++) {
+          if ($master[$j]{("priority_".($slave[$i]{"wbs"}))} != 0) {
             printf OUTFILE " or (%s_adr_o(%s downto %s) and %s_%s_bg)",$master[$j]{"wbm"},$slave[$i]{"adr_i_hi"},$slave[$i]{"adr_i_lo"},$master[$j]{"wbm"},$slave[$i]{"wbs"};
           };
         };
@@ -1523,9 +1523,9 @@ sub gen_adr_decoder{
 sub gen_muxshb{
     printf OUTFILE "mux: block\n";
     printf OUTFILE "  signal cyc, stb, we, ack : std_logic;\n";
-    if (($rty_i gt 0) && ($rty_o gt 1)) {
+    if (($rty_i > 0) && ($rty_o > 1)) {
       printf OUTFILE "  signal rty : std_logic;\n"; };
-    if (($err_i gt 0) && ($err_o gt 1)) {
+    if (($err_i > 0) && ($err_o > 1)) {
       printf OUTFILE "  signal err : std_logic;\n"; };
     if ($dat_size eq 8) {
       printf OUTFILE "  signal sel : std_logic;\n";
@@ -1533,130 +1533,130 @@ sub gen_muxshb{
       printf OUTFILE "  signal sel : std_logic_vector(%s downto 0);\n",$dat_size/8-1;
     };
     printf OUTFILE "  signal dat_m2s, dat_s2m : std_logic_vector(%s downto 0);\n",$dat_size-1;
-    if (($tgc_o gt 0) && ($tgc_i gt 0)) {
+    if (($tgc_o > 0) && ($tgc_i > 0)) {
       printf OUTFILE "  signal tgc : std_logic_vector(%s downto 0);\n",$tgc_bits-1; };
-    if (($tga_o gt 0) && ($tga_i gt 0)) {
+    if (($tga_o > 0) && ($tga_i > 0)) {
       printf OUTFILE "  signal tga : std_logic_vector(%s downto 0);\n",$tga_bits-1; };
     printf OUTFILE "begin\n";
     # cyc
     printf OUTFILE "cyc <= (%s_cyc_o and %s_bg)",$master[1]{"wbm"},$master[1]{"wbm"};
-    if ($masters gt 1) {
-      for ($i=2; $i le $masters; $i++) {
+    if ($masters > 1) {
+      for ($i=2; $i <= $masters; $i++) {
         printf OUTFILE " or (%s_cyc_o and %s_bg)",$master[$i]{"wbm"},$master[$i]{"wbm"}; };
     };
     printf OUTFILE ";\n";
-    for ($i=1; $i le $slaves; $i++) {
+    for ($i=1; $i <= $slaves; $i++) {
       printf OUTFILE "%s_cyc_i <= %s_ss and cyc;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"}; };
     # stb
     printf OUTFILE "stb <= (%s_stb_o and %s_bg)",$master[1]{"wbm"},$master[1]{"wbm"};
-    if ($masters gt 1) {
-      for ($i=2; $i le $masters; $i++) {
+    if ($masters > 1) {
+      for ($i=2; $i <= $masters; $i++) {
         printf OUTFILE " or (%s_stb_o and %s_bg)",$master[$i]{"wbm"},$master[$i]{"wbm"}; };
     };
     printf OUTFILE ";\n";
-    for ($i=1; $i le $slaves; $i++) {
+    for ($i=1; $i <= $slaves; $i++) {
       printf OUTFILE "%s_stb_i <= stb;\n",$slave[$i]{"wbs"}; };
     # we
     $i=1; until ($master[$i]{"type"} ne "ro") {$i++};
     printf OUTFILE "we <= (%s_we_o and %s_bg)",$master[$i]{"wbm"},$master[$i]{"wbm"};
-    if ($i lt $masters) {
-      for ($j=$i+1; $j le $masters; $j++) {
+    if ($i < $masters) {
+      for ($j=$i+1; $j <= $masters; $j++) {
         if ($master[$j]{"type"} ne "ro") {
           printf OUTFILE " or (%s_we_o and %s_bg)",$master[$j]{"wbm"},$master[$j]{"wbm"};
         };
       };
     };
     printf OUTFILE ";\n";
-    for ($i=1; $i le $slaves; $i++) {
+    for ($i=1; $i <= $slaves; $i++) {
       if ($slave[$i]{"type"} ne "ro") {
         printf OUTFILE "%s_we_i <= we;\n",$slave[$i]{"wbs"};
       };
     };
     # ack
     printf OUTFILE "ack <= %s_ack_o",$slave[1]{"wbs"};
-    for ($i=2; $i le $slaves; $i++) {
+    for ($i=2; $i <= $slaves; $i++) {
       printf OUTFILE " or %s_ack_o",$slave[$i]{"wbs"}; };
     printf OUTFILE ";\n";
-    for ($i=1; $i le $masters; $i++) {
+    for ($i=1; $i <= $masters; $i++) {
       printf OUTFILE "%s_ack_i <= ack and %s_bg;\n",$master[$i]{"wbm"},$master[$i]{"wbm"}; };
     # rty
-    if (($rty_o eq 0) && ($rty_i gt 0)) {
-      for ($i=1; $i le $masters; $i++) {
-        if ($master[$i]{"rty_i"} eq 1) {
+    if (($rty_o == 0) && ($rty_i > 0)) {
+      for ($i=1; $i <= $masters; $i++) {
+        if ($master[$i]{"rty_i"} == 1) {
           printf OUTFILE "%s_rty_i <= '0';\n",$master[$i]{"wbm"};
         };
       };
-    } elsif (($rty_o eq 1) && ($rty_i gt 0)) {
-      $i=1; until ($slave[$i]{"rty_o"} eq 1) {$i++};
-      for ($j=1; $j le $masters; $j++) {
-        if ($master[$j]{"rty_i"} eq 1) {
+    } elsif (($rty_o == 1) && ($rty_i > 0)) {
+      $i=1; until ($slave[$i]{"rty_o"} == 1) {$i++};
+      for ($j=1; $j <= $masters; $j++) {
+        if ($master[$j]{"rty_i"} == 1) {
           printf OUTFILE "%s_rty_i <= %s_rty_o;\n",$master[$j]{"wbm"},$slave[$i]{"wbs"};
         };
       };
-    } elsif (($rty_o gt 1) && ($rty_i gt 0)) {
-      $i=1; until ($slave[$i]{"rty_o"} eq 1) {$i++};
+    } elsif (($rty_o > 1) && ($rty_i > 0)) {
+      $i=1; until ($slave[$i]{"rty_o"} == 1) {$i++};
       printf OUTFILE "rty <= %s_rty_o",$slave[$i]{"wbs"};
-      for ($j=$i+1; $j le $slaves; $j++) {
-        if ($slave[$j]{"rty_o"} eq 1) {
+      for ($j=$i+1; $j <= $slaves; $j++) {
+        if ($slave[$j]{"rty_o"} == 1) {
           printf OUTFILE " or %s_rty_o",$slave[$j]{"wbs"};
         };
       };
       printf OUTFILE ";\n";
-      for ($i=1; $i le $masters; $i++) {
-        if ($master[$i]{"rty_i"} eq 1) {
+      for ($i=1; $i <= $masters; $i++) {
+        if ($master[$i]{"rty_i"} == 1) {
           printf OUTFILE "%s_rty_i <= rty;\n",$master[$i]{"wbm"};
         };
       };
     };
     # err
-    if (($err_o eq 0) && ($err_i gt 0)) {
-      for ($i=1; $i le $masters; $i++) {
-        if ($master[$i]{"err_i"} eq 1) {
+    if (($err_o == 0) && ($err_i > 0)) {
+      for ($i=1; $i <= $masters; $i++) {
+        if ($master[$i]{"err_i"} == 1) {
           printf OUTFILE "%s_err_i <= '0';\n",$master[$i]{"wbm"};
         };
       };
-    } elsif (($err_o eq 1) && ($err_i gt 0)) {
-      $i=1; until ($slave[$i]{"err_o"} eq 1) {$i++};
-      for ($j=1; $j le $masters; $j++) {
-        if ($master[$j]{"err_i"} eq 1) {
+    } elsif (($err_o == 1) && ($err_i > 0)) {
+      $i=1; until ($slave[$i]{"err_o"} == 1) {$i++};
+      for ($j=1; $j <= $masters; $j++) {
+        if ($master[$j]{"err_i"} == 1) {
           printf OUTFILE "%s_err_i <= %s_err_o;\n",$master[$j]{"wbm"},$slave[$i]{"wbs"};
         };
       };
-    } elsif (($err_o gt 1) && ($err_i gt 0)) {
-      $i=1; until ($slave[$i]{"err_o"} eq 1) {$i++};
+    } elsif (($err_o > 1) && ($err_i > 0)) {
+      $i=1; until ($slave[$i]{"err_o"} == 1) {$i++};
       printf OUTFILE "err <= %s_err_o",$slave[$i]{"wbs"};
-      for ($j=$i+1; $j le $slaves; $j++) {
-        if ($slave[$j]{"err_o"} eq 1) {
+      for ($j=$i+1; $j <= $slaves; $j++) {
+        if ($slave[$j]{"err_o"} == 1) {
           printf OUTFILE " or %s_err_o",$slave[$j]{"wbs"};
         };
       };
       printf OUTFILE ";\n";
-      for ($i=1; $i le $masters; $i++) {
-        if ($master[$i]{"err_i"} eq 1) {
+      for ($i=1; $i <= $masters; $i++) {
+        if ($master[$i]{"err_i"} == 1) {
           printf OUTFILE "%s_err_i <= err;\n",$master[$i]{"wbm"};
         };
       };
     };
     # sel
     printf OUTFILE "sel <= (%s_sel_o and %s_bg)",$master[1]{"wbm"},$master[1]{"wbm"};
-    if ($masters gt 1) {
-      for ($i=2; $i le $masters; $i++) {
+    if ($masters > 1) {
+      for ($i=2; $i <= $masters; $i++) {
         printf OUTFILE " or (%s_sel_o and %s_bg)",$master[$i]{"wbm"},$master[$i]{"wbm"};
       };
     };
     printf OUTFILE ";\n";
-    for ($i=1; $i le $slaves; $i++) {
+    for ($i=1; $i <= $slaves; $i++) {
       printf OUTFILE "%s_sel_i <= sel;\n",$slave[$i]{"wbs"}; };
     # data m2s
     $i=1; until ($master[$i]{"type"} ne "ro") {$i++};
     printf OUTFILE "dat_m2s <= (%s_dat_o and %s_bg)",$master[$i]{"wbm"},$master[$i]{"wbm"};
-    if ($i lt $masters) {
-      for ($j=$i+1; $j le $masters; $j++) {
+    if ($i < $masters) {
+      for ($j=$i+1; $j <= $masters; $j++) {
         printf OUTFILE " or (%s_dat_o and %s_bg)",$master[$j]{"wbm"},$master[$j]{"wbm"};
       };
     };
     printf OUTFILE ";\n";
-    for ($i=1; $i le $slaves; $i++) {
+    for ($i=1; $i <= $slaves; $i++) {
       if ($slave[$i]{"type"} ne "ro") {
         printf OUTFILE "%s_dat_i <= dat_m2s;\n",$slave[$i]{"wbs"};
       };
@@ -1664,57 +1664,57 @@ sub gen_muxshb{
     # data s2m
     $i=1; until ($slave[$i]{"type"} ne "wo") {$i++};
     printf OUTFILE "dat_s2m <= (%s_dat_o and %s_ss)",$slave[$i]{"wbs"},$slave[$i]{"wbs"};
-    if ($i lt $slaves) {
-      for ($j=$i+1; $j le $slaves; $j++) {
+    if ($i < $slaves) {
+      for ($j=$i+1; $j <= $slaves; $j++) {
         printf OUTFILE " or (%s_dat_o and %s_ss)",$slave[$j]{"wbs"},$slave[$j]{"wbs"};
       };
     };
     printf OUTFILE ";\n";
-    for ($i=1; $i le $masters; $i++) {
+    for ($i=1; $i <= $masters; $i++) {
       if ($master[$i]{"type"} ne "wo") {
         printf OUTFILE "%s_dat_i <= dat_s2m;\n",$master[$i]{"wbm"};
       };
     };
     # tgc
-    if (($tgc_o eq 0) && ($tgc_i gt 0)) {
-      for ($i=1; $i le $slaves; $i++) {
-        if ($slave[$i]{"tgc_i"} eq 1) {
+    if (($tgc_o == 0) && ($tgc_i > 0)) {
+      for ($i=1; $i <= $slaves; $i++) {
+        if ($slave[$i]{"tgc_i"} == 1) {
           printf OUTFILE "%s_%s_i <= %s;\n",$slave[$i]{"wbs"},$rename_tgc,$classic;
         };
       };
-    } elsif (($tgc_o gt 0) && ($tgc_i gt 0)) {
-      $i=1; until ($master[$i]{"tgc_o"} eq 1) {$i++};
+    } elsif (($tgc_o > 0) && ($tgc_i > 0)) {
+      $i=1; until ($master[$i]{"tgc_o"} == 1) {$i++};
       printf OUTFILE "tgc <= (%s_%s_o and %s_bg)",$master[$i]{"wbm"},$rename_tgc,$master[$i]{"wbm"};
-      for ($j=$i+1; $j le $masters; $j++) {
-        if ($master[$j]{"tgc_o"} eq 1) {
+      for ($j=$i+1; $j <= $masters; $j++) {
+        if ($master[$j]{"tgc_o"} == 1) {
           printf OUTFILE " or (%s_%s_o and %s_bg)",$master[$j]{"wbm"},$rename_tgc,$master[$j]{"wbm"};
         };
       };
       printf OUTFILE ";\n";
-      for ($i=1; $i le $slaves; $i++) {
-        if ($slave[$i]{"tgc_i"} eq 1) {
+      for ($i=1; $i <= $slaves; $i++) {
+        if ($slave[$i]{"tgc_i"} ==  1) {
           printf OUTFILE "%s_%s_i <= tgc;\n",$slave[$i]{"wbs"},$rename_tgc,$slave[$i]{"wbs"};
         };
       };
     };
     # tga
-    if (($tga_o eq 0) && ($tga_i gt 0)) {
-      for ($i=1; $i le $slaves; $i++) {
-        if ($slave[$i]{"tga_i"} eq 1) {
+    if (($tga_o == 0) && ($tga_i > 0)) {
+      for ($i=1; $i <= $slaves; $i++) {
+        if ($slave[$i]{"tga_i"} == 1) {
           printf OUTFILE "%s_%s_i <= (others=>'0');\n",$slave[$i]{"wbs"},$rename_tga;
         };
       };
-    } elsif (($tga_o gt 0) && ($tga_i gt 0)) {
-      $i=1; until ($master[$i]{"tga_o"} eq 1) {$i++};
+    } elsif (($tga_o > 0) && ($tga_i > 0)) {
+      $i=1; until ($master[$i]{"tga_o"} == 1) {$i++};
       printf OUTFILE "tga <= (%s_%s_o and %s_bg)",$master[$i]{"wbm"},$rename_tga,$master[$i]{"wbm"};
-      for ($j=$i+1; $j le $masters; $j++) {
-        if ($master[$j]{"tga_o"} eq 1) {
+      for ($j=$i+1; $j <= $masters; $j++) {
+        if ($master[$j]{"tga_o"} == 1) {
           printf OUTFILE " or (%s_%s_o and %s_bg)",$master[$j]{"wbm"},$rename_tga,$master[$j]{"wbm"};
         };
       };
       printf OUTFILE ";\n";
-      for ($i=1; $i le $slaves; $i++) {
-        if ($slave[$i]{"tga_i"} eq 1) {
+      for ($i=1; $i <= $slaves; $i++) {
+        if ($slave[$i]{"tga_i"} == 1) {
           printf OUTFILE "%s_%s_i <= tga;\n",$slave[$i]{"wbs"},$rename_tga,$slave[$i]{"wbs"};
         };
       };
@@ -1726,11 +1726,11 @@ sub gen_muxshb{
 sub gen_muxcbs{
     # cyc
     printf OUTFILE "-- cyc_i(s)\n";
-    for ($i=1; $i le $slaves; $i++) {
-      $tmp=1; until ($master[$tmp]{("priority_".($slave[$i]{"wbs"}))} ne 0) {$tmp++};
+    for ($i=1; $i <= $slaves; $i++) {
+      $tmp=1; until ($master[$tmp]{("priority_".($slave[$i]{"wbs"}))} != 0) {$tmp++};
       printf OUTFILE "%s_cyc_i <= (%s_cyc_o and %s_%s_bg)",$slave[$i]{"wbs"},$master[$tmp]{"wbm"},$master[$tmp]{"wbm"},$slave[$i]{"wbs"};
-      for ($j=$tmp+1; $j le $masters; $j++) {
-        if ($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) {
+      for ($j=$tmp+1; $j <= $masters; $j++) {
+        if ($master[$j]{("priority_".($slave[$i]{"wbs"}))} != 0) {
           printf OUTFILE " or (%s_cyc_o and %s_%s_bg)",$master[$j]{"wbm"},$master[$j]{"wbm"},$slave[$i]{"wbs"};
         };
       };
@@ -1738,11 +1738,11 @@ sub gen_muxcbs{
     };
     # stb
     printf OUTFILE "-- stb_i(s)\n";
-    for ($i=1; $i le $slaves; $i++) {
-      $tmp=1; until ($master[$tmp]{("priority_".($slave[$i]{"wbs"}))} ne 0) {$tmp++};
+    for ($i=1; $i <= $slaves; $i++) {
+      $tmp=1; until ($master[$tmp]{("priority_".($slave[$i]{"wbs"}))} != 0) {$tmp++};
       printf OUTFILE "%s_stb_i <= (%s_stb_o and %s_%s_bg)",$slave[$i]{"wbs"},$master[$tmp]{"wbm"},$master[$tmp]{"wbm"},$slave[$i]{"wbs"};
-      for ($j=$tmp+1; $j le $masters; $j++) {
-        if ($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) {
+      for ($j=$tmp+1; $j <= $masters; $j++) {
+        if ($master[$j]{("priority_".($slave[$i]{"wbs"}))} != 0) {
           printf OUTFILE " or (%s_stb_o and %s_%s_bg)",$master[$j]{"wbm"},$master[$j]{"wbm"},$slave[$i]{"wbs"};
         };
       };
@@ -1750,12 +1750,12 @@ sub gen_muxcbs{
     };
     # we
     printf OUTFILE "-- we_i(s)\n";
-    for ($i=1; $i le $slaves; $i++) {
+    for ($i=1; $i <= $slaves; $i++) {
       if ($slave[$i]{"type"} ne "ro") {
-        $tmp=1; until (($master[$tmp]{("priority_".($slave[$i]{"wbs"}))} ne 0) && ($master[$tmp]{"type"} ne "ro")) {$tmp++};
+        $tmp=1; until (($master[$tmp]{("priority_".($slave[$i]{"wbs"}))} != 0) && ($master[$tmp]{"type"} ne "ro")) {$tmp++};
         printf OUTFILE "%s_we_i <= (%s_we_o and %s_%s_bg)",$slave[$i]{"wbs"},$master[$tmp]{"wbm"},$master[$tmp]{"wbm"},$slave[$i]{"wbs"};
-        for ($j=$tmp+1; $j le $masters; $j++) {
-          if (($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) && ($master[$j]{"type"} ne "ro")) {
+        for ($j=$tmp+1; $j <= $masters; $j++) {
+          if (($master[$j]{("priority_".($slave[$i]{"wbs"}))} != 0) && ($master[$j]{"type"} ne "ro")) {
             printf OUTFILE " or (%s_we_o and %s_%s_bg)",$master[$j]{"wbm"},$master[$j]{"wbm"},$slave[$i]{"wbs"};
           };
         };
@@ -1764,11 +1764,11 @@ sub gen_muxcbs{
     };
     # ack
     printf OUTFILE "-- ack_i(s)\n";
-    for ($i=1; $i le $masters; $i++) {
-      $tmp=1; until ($master[$i]{("priority_".($slave[$tmp]{"wbs"}))} ne 0) {$tmp++};
+    for ($i=1; $i <= $masters; $i++) {
+      $tmp=1; until ($master[$i]{("priority_".($slave[$tmp]{"wbs"}))} != 0) {$tmp++};
       printf OUTFILE "%s_ack_i <= (%s_ack_o and %s_%s_bg)",$master[$i]{"wbm"},$slave[$tmp]{"wbs"},$master[$i]{"wbm"},$slave[$tmp]{"wbs"};
-      for ($j=$tmp+1; $j le $slaves; $j++) {
-        if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
+      for ($j=$tmp+1; $j <= $slaves; $j++) {
+        if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} != 0) {
           printf OUTFILE " or (%s_ack_o and %s_%s_bg)",$slave[$j]{"wbs"},$master[$i]{"wbm"},$slave[$j]{"wbs"};
         };
       };
@@ -1776,21 +1776,21 @@ sub gen_muxcbs{
     };
     # rty
     printf OUTFILE "-- rty_i(s)\n";
-    for ($i=1; $i le $masters; $i++) {
-      if ($master[$i]{"rty_i"} eq 1) {
+    for ($i=1; $i <= $masters; $i++) {
+      if ($master[$i]{"rty_i"} == 1) {
         $rty_o=0;
-        for ($j=1; $j le $masters; $j++) {
-          if (($slave[$j]{"rty_o"} eq 1) && ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0)) {
+        for ($j=1; $j <= $masters; $j++) {
+          if (($slave[$j]{"rty_o"} == 1) && ($master[$i]{("priority_".($slave[$j]{"wbs"}))} != 0)) {
             $rty_o+=1;
           };
         };
-        if ($rty_o eq 0) {
+        if ($rty_o == 0) {
           printf OUTFILE "%s_rty_i <= '0';\n",$master[$i]{"wbm"};
         } else {
-          $tmp=1; until ($master[$i]{("priority_".($slave[$tmp]{"wbs"}))} ne 0) {$tmp++};
+          $tmp=1; until ($master[$i]{("priority_".($slave[$tmp]{"wbs"}))} != 0) {$tmp++};
           printf OUTFILE "%s_rty_i <= (%s_rty_o and %s_%s_bg)",$master[$i]{"wbm"},$slave[$tmp]{"wbs"},$master[$i]{"wbm"},$slave[$tmp]{"wbs"};
-          for ($j=$tmp+1; $j le $slaves; $j++) {
-            if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
+          for ($j=$tmp+1; $j <= $slaves; $j++) {
+            if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} != 0) {
               printf OUTFILE " or (%s_rty_o and %s_%s_bg)",$slave[$j]{"wbs"},$master[$i]{"wbm"},$slave[$j]{"wbs"};
             };
           };
@@ -1800,21 +1800,21 @@ sub gen_muxcbs{
     };
     # err
     printf OUTFILE "-- err_i(s)\n";
-    for ($i=1; $i le $masters; $i++) {
-      if ($master[$i]{"err_i"} eq 1) {
+    for ($i=1; $i <= $masters; $i++) {
+      if ($master[$i]{"err_i"} == 1) {
         $err_o=0;
-        for ($j=1; $j le $masters; $j++) {
-          if (($slave[$j]{"err_o"} eq 1) && ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0)) {
+        for ($j=1; $j <= $masters; $j++) {
+          if (($slave[$j]{"err_o"} == 1) && ($master[$i]{("priority_".($slave[$j]{"wbs"}))} != 0)) {
             $err_o+=1;
           };
         };
-        if ($err_o eq 0) {
+        if ($err_o == 0) {
           printf OUTFILE "%s_err_i <= '0';\n",$master[$i]{"wbm"};
         } else {
-          $tmp=1; until ($master[$i]{("priority_".($slave[$tmp]{"wbs"}))} ne 0) {$tmp++};
+          $tmp=1; until ($master[$i]{("priority_".($slave[$tmp]{"wbs"}))} != 0) {$tmp++};
           printf OUTFILE "%s_err_i <= (%s_err_o and %s_%s_bg)",$master[$i]{"wbm"},$slave[$tmp]{"wbs"},$master[$i]{"wbm"},$slave[$tmp]{"wbs"};
-          for ($j=$tmp+1; $j le $slaves; $j++) {
-            if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
+          for ($j=$tmp+1; $j <= $slaves; $j++) {
+            if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} != 0) {
               printf OUTFILE " or (%s_err_o and %s_%s_bg)",$slave[$j]{"wbs"},$master[$i]{"wbm"},$slave[$j]{"wbs"};
             };
           };
@@ -1824,12 +1824,12 @@ sub gen_muxcbs{
     };
     # sel
     printf OUTFILE "-- sel_i(s)\n";
-    for ($i=1; $i le $slaves; $i++) {
+    for ($i=1; $i <= $slaves; $i++) {
       if ($dat_size >= 16) {
-        $tmp=1; until ($master[$tmp]{("priority_".($slave[$i]{"wbs"}))} ne 0) {$tmp++};
+        $tmp=1; until ($master[$tmp]{("priority_".($slave[$i]{"wbs"}))} != 0) {$tmp++};
         printf OUTFILE "%s_sel_i <= (%s_sel_o and %s_%s_bg)",$slave[$i]{"wbs"},$master[$tmp]{"wbm"},$master[$tmp]{"wbm"},$slave[$i]{"wbs"};
-        for ($j=$tmp+1; $j le $masters; $j++) {
-          if ($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) {
+        for ($j=$tmp+1; $j <= $masters; $j++) {
+          if ($master[$j]{("priority_".($slave[$i]{"wbs"}))} != 0) {
             printf OUTFILE " or (%s_sel_o and %s_%s_bg)",$master[$j]{"wbm"},$master[$j]{"wbm"},$slave[$i]{"wbs"};
           };
         };
@@ -1838,22 +1838,22 @@ sub gen_muxcbs{
     };
     # dat
     printf OUTFILE "-- slave dat_i(s)\n";
-    for ($i=1; $i le $slaves; $i++) {
+    for ($i=1; $i <= $slaves; $i++) {
       if ($slave[$i]{"type"} ne "ro") {
         $tmp=0;
-        for ($j=1; $j le $masters; $j++) {
-          if (($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) && ($master[$j]{"type"} ne "ro")) {
+        for ($j=1; $j <= $masters; $j++) {
+          if (($master[$j]{("priority_".($slave[$i]{"wbs"}))} != 0) && ($master[$j]{"type"} ne "ro")) {
             $tmp+=1;
           };
         };
-        if ($tmp eq 1) {
-          $j=1; until (($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) && ($master[$j]{"type"} ne "ro")) {$j++};
+        if ($tmp == 1) {
+          $j=1; until (($master[$j]{("priority_".($slave[$i]{"wbs"}))} != 0) && ($master[$j]{"type"} ne "ro")) {$j++};
           printf OUTFILE "%s_dat_i <= %s_dat_o;\n",$slave[$i]{"wbs"},$master[$j]{"wbm"};
         } elsif ($tmp >= 1) {
-          $tmp=1; until (($master[$tmp]{("priority_".($slave[$i]{"wbs"}))} ne 0) && ($master[$tmp]{"type"} ne "ro")) {$tmp++};
+          $tmp=1; until (($master[$tmp]{("priority_".($slave[$i]{"wbs"}))} != 0) && ($master[$tmp]{"type"} ne "ro")) {$tmp++};
           printf OUTFILE "%s_dat_i <= (%s_dat_o and %s_%s_bg)",$slave[$i]{"wbs"},$master[$tmp]{"wbm"},$master[$tmp]{"wbm"},$slave[$i]{"wbs"};
-          for ($j=$tmp+1; $j le $masters; $j++) {
-            if (($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) && ($master[$j]{"type"} ne "ro")) {
+          for ($j=$tmp+1; $j <= $masters; $j++) {
+            if (($master[$j]{("priority_".($slave[$i]{"wbs"}))} != 0) && ($master[$j]{"type"} ne "ro")) {
               printf OUTFILE " or (%s_dat_o and %s_%s_bg)",$master[$j]{"wbm"},$master[$j]{"wbm"},$slave[$i]{"wbs"};
             };
           };
@@ -1862,22 +1862,22 @@ sub gen_muxcbs{
       };
     };
     printf OUTFILE "-- master dat_i(s)\n";
-    for ($i=1; $i le $masters; $i++) {
+    for ($i=1; $i <= $masters; $i++) {
       if ($master[$i]{"type"} ne "wo") {
         $tmp=0;
-        for ($j=1; $j le $slaves; $j++) {
-          if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
+        for ($j=1; $j <= $slaves; $j++) {
+          if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} != 0) {
             $tmp+=1;
           };
         };
-        if ($tmp eq 1) {
-          $tmp=1; until ($master[$i]{("priority_".($slave[$tmp]{"wbs"}))} ne 0) {$tmp++};
+        if ($tmp == 1) {
+          $tmp=1; until ($master[$i]{("priority_".($slave[$tmp]{"wbs"}))} != 0) {$tmp++};
           printf OUTFILE "%s_dat_i <= %s_dat_o",$master[$i]{"wbm"},$slave[$tmp]{"wbs"};
         } else {
-          $tmp=1; until ($master[$i]{("priority_".($slave[$tmp]{"wbs"}))} ne 0) {$tmp++};
+          $tmp=1; until ($master[$i]{("priority_".($slave[$tmp]{"wbs"}))} != 0) {$tmp++};
           printf OUTFILE "%s_dat_i <= (%s_dat_o and %s_%s_bg)",$master[$i]{"wbm"},$slave[$tmp]{"wbs"},$master[$i]{"wbm"},$slave[$tmp]{"wbs"};
-          for ($j=$tmp+1; $j le $slaves; $j++) {
-            if (($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) && ($master[$i]{"type"} ne "wo")) {
+          for ($j=$tmp+1; $j <= $slaves; $j++) {
+            if (($master[$i]{("priority_".($slave[$j]{"wbs"}))} != 0) && ($master[$i]{"type"} ne "wo")) {
               printf OUTFILE " or (%s_dat_o and %s_%s_bg)",$slave[$j]{"wbs"},$master[$i]{"wbm"},$slave[$j]{"wbs"};
             };
           };
@@ -1887,23 +1887,23 @@ sub gen_muxcbs{
     };
     # tgc
     printf OUTFILE "-- tgc_i\n";
-    for ($i=1; $i le $slaves; $i++) {
-      if ($slave[$i]{"tgc_i"} eq 1) {
+    for ($i=1; $i <= $slaves; $i++) {
+      if ($slave[$i]{"tgc_i"} == 1) {
         $tmp=0;
-        for ($j=1; $j le $masters; $j++) {
-          if ($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) {
+        for ($j=1; $j <= $masters; $j++) {
+          if ($master[$j]{("priority_".($slave[$i]{"wbs"}))} != 0) {
             $tmp+=1;
           };
         };
-        if ($tmp eq 1) {
-          $tmp=1; until ($master[$tmp]{("priority_".($slave[$i]{"wbs"}))} ne 0) {$tmp++;};
+        if ($tmp == 1) {
+          $tmp=1; until ($master[$tmp]{("priority_".($slave[$i]{"wbs"}))} != 0) {$tmp++;};
           printf OUTFILE "%s_%s_i <= %s_%s_o",$slave[$i]{"wbs"},$rename_tgc,$master[$tmp]{"wbm"},$rename_tgc;
         } else {
-          $tmp=1; until ($master[$tmp]{("priority_".($slave[$i]{"wbs"}))} ne 0) {$tmp++;};
+          $tmp=1; until ($master[$tmp]{("priority_".($slave[$i]{"wbs"}))} != 0) {$tmp++;};
           printf OUTFILE "%s_%s_i <= (%s_%s_o and %s_%s_bg)",$slave[$i]{"wbs"},$rename_tgc,$master[$tmp]{"wbm"},$rename_tgc,$master[$tmp]{"wbm"},$slave[$i]{"wbs"};
-          for ($j=$tmp+1; $j le $masters; $j++) {
-            if ($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) {
-	      if ($master[$j]{"tga_o"} eq 1) {
+          for ($j=$tmp+1; $j <= $masters; $j++) {
+            if ($master[$j]{("priority_".($slave[$i]{"wbs"}))} != 0) {
+	      if ($master[$j]{"tga_o"} == 1) {
                 printf OUTFILE " or (%s_%s_o and %s_%s_bg)",$master[$j]{"wbm"},$rename_tgc,$master[$j]{"wbm"},$slave[$i]{"wbs"};
 	      } else {
 		if ($classic ne "000") {
@@ -1919,23 +1919,23 @@ sub gen_muxcbs{
     };
     # tga
     printf OUTFILE "-- tga_i\n";
-    for ($i=1; $i le $slaves; $i++) {
-      if ($slave[$i]{"tga_i"} eq 1) {
+    for ($i=1; $i <= $slaves; $i++) {
+      if ($slave[$i]{"tga_i"} == 1) {
         $tmp=0;
-        for ($j=1; $j le $masters; $j++) {
-          if ($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) {
+        for ($j=1; $j <= $masters; $j++) {
+          if ($master[$j]{("priority_".($slave[$i]{"wbs"}))} != 0) {
             $tmp+=1;
           };
         };
-        if ($tmp eq 1) {
-          $tmp=1; until ($master[$tmp]{("priority_".($slave[$i]{"wbs"}))} ne 0) {$tmp++;};
+        if ($tmp == 1) {
+          $tmp=1; until ($master[$tmp]{("priority_".($slave[$i]{"wbs"}))} != 0) {$tmp++;};
           printf OUTFILE "%s_%s_i <= %s_%s_o",$slave[$i]{"wbs"},$rename_tga,$master[$tmp]{"wbm"},$rename_tga;
         } else {
-          $tmp=1; until ($master[$tmp]{("priority_".($slave[$i]{"wbs"}))} ne 0) {$tmp++;};
+          $tmp=1; until ($master[$tmp]{("priority_".($slave[$i]{"wbs"}))} != 0) {$tmp++;};
           printf OUTFILE "%s_%s_i <= (%s_%s_o and %s_%s_bg)",$slave[$i]{"wbs"},$rename_tga,$master[$tmp]{"wbm"},$rename_tga,$master[$tmp]{"wbm"},$slave[$i]{"wbs"};
-          for ($j=$tmp+1; $j le $masters; $j++) {
-            if ($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) {
-	      if ($master[$j]{"tga_o"} eq 1) {
+          for ($j=$tmp+1; $j <= $masters; $j++) {
+            if ($master[$j]{("priority_".($slave[$i]{"wbs"}))} != 0) {
+	      if ($master[$j]{"tga_o"} == 1) {
                 printf OUTFILE " or (%s_%s_o and %s_%s_bg)",$master[$j]{"wbm"},$rename_tga,$master[$j]{"wbm"},$slave[$i]{"wbs"};
 	      };
             };
@@ -1947,13 +1947,13 @@ sub gen_muxcbs{
 };
 
 sub gen_remap{
-    for ($i=1; $i le $masters; $i++) {
+    for ($i=1; $i <= $masters; $i++) {
       if ($master[$i]{"type"} ne "wo") {
         printf OUTFILE "%s_wbm_i.dat_i <= %s_dat_i;\n",$master[$i]{"wbm"},$master[$i]{"wbm"}; };
       printf OUTFILE "%s_wbm_i.ack_i <= %s_ack_i ;\n",$master[$i]{"wbm"},$master[$i]{"wbm"};
-      if ($master[$i]{"err_i"} eq 1) {
+      if ($master[$i]{"err_i"} == 1) {
         printf OUTFILE "%s_wbm_i.err_i <= %s_err_i;\n",$master[$i]{"wbm"},$master[$i]{"wbm"}; };
-      if ($master[$i]{"rty_i"} eq 1) {
+      if ($master[$i]{"rty_i"} == 1) {
         printf OUTFILE "%s_wbm_i.rty_i <= %s_rty_i;\n",$master[$i]{"wbm"},$master[$i]{"wbm"}; };
       if ($master[$i]{"type"} ne "ro") {
         printf OUTFILE "%s_dat_o <= %s_wbm_o.dat_o;\n",$master[$i]{"wbm"},$master[$i]{"wbm"};
@@ -1961,20 +1961,20 @@ sub gen_remap{
       };
       printf OUTFILE "%s_sel_o <= %s_wbm_o.sel_o;\n",$master[$i]{"wbm"},$master[$i]{"wbm"};
       printf OUTFILE "%s_adr_o <= %s_wbm_o.adr_o;\n",$master[$i]{"wbm"},$master[$i]{"wbm"};
-      if ($master[$i]{"tgc_o"} eq 1) {
+      if ($master[$i]{"tgc_o"} == 1) {
         printf OUTFILE "%s_%s_o <= %s_wbm_o.%s_o;\n",$master[$i]{"wbm"},$rename_tgc,$master[$i]{"wbm"},$rename_tgc; };
-      if ($master[$i]{"tga_o"} eq 1) {
+      if ($master[$i]{"tga_o"} == 1) {
         printf OUTFILE "%s_%s_o <= %s_wbm_o.%s_o;\n",$master[$i]{"wbm"},$rename_tga,$master[$i]{"wbm"},$rename_tga; };
       printf OUTFILE "%s_cyc_o <= %s_wbm_o.cyc_o;\n",$master[$i]{"wbm"},$master[$i]{"wbm"};
       printf OUTFILE "%s_stb_o <= %s_wbm_o.stb_o;\n",$master[$i]{"wbm"},$master[$i]{"wbm"};
     };
-    for ($i=1; $i le $slaves; $i++) {
+    for ($i=1; $i <= $slaves; $i++) {
       if ($slave[$i]{"type"} ne "wo") {
         printf OUTFILE "%s_dat_o <= %s_wbs_o.dat_o;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"}; };
       printf OUTFILE "%s_ack_o <= %s_wbs_o.ack_o;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"};
-      if ($slave[$i]{"err_o"} eq 1) {
+      if ($slave[$i]{"err_o"} == 1) {
         printf OUTFILE "%s_err_o <= %s_wbs_o.err_o;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"}; };
-      if ($slave[$i]{"rty_o"} eq 1) {
+      if ($slave[$i]{"rty_o"} == 1) {
         printf OUTFILE "%s_rty_o <= %s_wbs_o.rty_o;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"}; };
       if ($slave[$i]{"type"} ne "ro") {
         printf OUTFILE "%s_wbs_i.dat_i <= %s_dat_i;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"};
@@ -1982,9 +1982,9 @@ sub gen_remap{
       };
       printf OUTFILE "%s_wbs_i.sel_i <= %s_sel_i;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"};
       printf OUTFILE "%s_wbs_i.adr_i <= %s_adr_i;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"};
-      if ($slave[$i]{"tgc_i"} eq 1) {
+      if ($slave[$i]{"tgc_i"} == 1) {
         printf OUTFILE "%s_wbs_i.%s_i <= %s_%s_i;\n",$slave[$i]{"wbs"},$rename_tgc,$slave[$i]{"wbs"},$rename_tgc; };
-      if ($slave[$i]{"tga_i"} eq 1) {
+      if ($slave[$i]{"tga_i"} == 1) {
         printf OUTFILE "%s_wbs_i.%s_i <= %s_%s_i;\n",$slave[$i]{"wbs"},$rename_tga,$slave[$i]{"wbs"},$rename_tga; };
       printf OUTFILE "%s_wbs_i.cyc_i <= %s_cyc_i;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"};
       printf OUTFILE "%s_wbs_i.stb_i <= %s_stb_i;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"};
diff --git a/toplevel_tb.wcfg b/toplevel_tb.wcfg
index a5d657f..9326504 100644
--- a/toplevel_tb.wcfg
+++ b/toplevel_tb.wcfg
@@ -176,6 +176,32 @@
    <wvobject fp_name="/toplevel_tb/DUT/cpu_wbm_o" type="array" db_ref_id="1">
       <obj_property name="ElementShortName">cpu_wbm_o</obj_property>
       <obj_property name="ObjectShortName">cpu_wbm_o</obj_property>
+      <wvobject fp_name="/toplevel_tb/DUT/cpu_wbm_o.dat_o" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">.dat_o</obj_property>
+         <obj_property name="ObjectShortName">cpu_wbm_o.dat_o</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/toplevel_tb/DUT/cpu_wbm_o.we_o" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">.we_o</obj_property>
+         <obj_property name="ObjectShortName">cpu_wbm_o.we_o</obj_property>
+      </wvobject>
+      <wvobject fp_name="/toplevel_tb/DUT/cpu_wbm_o.sel_o" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">.sel_o</obj_property>
+         <obj_property name="ObjectShortName">cpu_wbm_o.sel_o</obj_property>
+      </wvobject>
+      <wvobject fp_name="/toplevel_tb/DUT/cpu_wbm_o.adr_o" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">.adr_o</obj_property>
+         <obj_property name="ObjectShortName">cpu_wbm_o.adr_o</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/toplevel_tb/DUT/cpu_wbm_o.cyc_o" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">.cyc_o</obj_property>
+         <obj_property name="ObjectShortName">cpu_wbm_o.cyc_o</obj_property>
+      </wvobject>
+      <wvobject fp_name="/toplevel_tb/DUT/cpu_wbm_o.stb_o" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">.stb_o</obj_property>
+         <obj_property name="ObjectShortName">cpu_wbm_o.stb_o</obj_property>
+      </wvobject>
    </wvobject>
    <wvobject fp_name="/toplevel_tb/DUT/sdram_ctrl_wbs_i" type="array" db_ref_id="1">
       <obj_property name="ElementShortName">sdram_ctrl_wbs_i</obj_property>
@@ -198,14 +224,6 @@
          <obj_property name="ObjectShortName">sdram_ctrl_wbs_i.adr_i</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
       </wvobject>
-      <wvobject fp_name="/toplevel_tb/DUT/sdram_ctrl_wbs_i.bte_i" type="array" db_ref_id="1">
-         <obj_property name="ElementShortName">.bte_i</obj_property>
-         <obj_property name="ObjectShortName">sdram_ctrl_wbs_i.bte_i</obj_property>
-      </wvobject>
-      <wvobject fp_name="/toplevel_tb/DUT/sdram_ctrl_wbs_i.cti_i" type="array" db_ref_id="1">
-         <obj_property name="ElementShortName">.cti_i</obj_property>
-         <obj_property name="ObjectShortName">sdram_ctrl_wbs_i.cti_i</obj_property>
-      </wvobject>
       <wvobject fp_name="/toplevel_tb/DUT/sdram_ctrl_wbs_i.cyc_i" type="logic" db_ref_id="1">
          <obj_property name="ElementShortName">.cyc_i</obj_property>
          <obj_property name="ObjectShortName">sdram_ctrl_wbs_i.cyc_i</obj_property>
@@ -313,6 +331,7 @@
       <wvobject fp_name="/toplevel_tb/DUT/vga_1/vga_pixelreader_inst/pixeldata" type="array" db_ref_id="1">
          <obj_property name="ElementShortName">pixeldata[63:0]</obj_property>
          <obj_property name="ObjectShortName">pixeldata[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
       </wvobject>
       <wvobject fp_name="/toplevel_tb/DUT/vga_1/vga_pixelreader_inst/fifo_write" type="logic" db_ref_id="1">
          <obj_property name="ElementShortName">fifo_write</obj_property>
@@ -337,6 +356,7 @@
       <wvobject fp_name="/toplevel_tb/DUT/vga_1/vga_pixelreader_inst/mem_adr" type="array" db_ref_id="1">
          <obj_property name="ElementShortName">mem_adr[19:0]</obj_property>
          <obj_property name="ObjectShortName">mem_adr[19:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
       </wvobject>
       <wvobject fp_name="/toplevel_tb/DUT/vga_1/vga_pixelreader_inst/mem_ack" type="logic" db_ref_id="1">
          <obj_property name="ElementShortName">mem_ack</obj_property>
@@ -732,6 +752,10 @@
          <obj_property name="ElementShortName">set_dirty</obj_property>
          <obj_property name="ObjectShortName">set_dirty</obj_property>
       </wvobject>
+      <wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/set_clean" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">set_clean</obj_property>
+         <obj_property name="ObjectShortName">set_clean</obj_property>
+      </wvobject>
       <wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/set_valid" type="logic" db_ref_id="1">
          <obj_property name="ElementShortName">set_valid</obj_property>
          <obj_property name="ObjectShortName">set_valid</obj_property>
@@ -756,10 +780,6 @@
          <obj_property name="ElementShortName">cache_to_mem</obj_property>
          <obj_property name="ObjectShortName">cache_to_mem</obj_property>
       </wvobject>
-      <wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/user_cc" type="logic" db_ref_id="1">
-         <obj_property name="ElementShortName">user_cc</obj_property>
-         <obj_property name="ObjectShortName">user_cc</obj_property>
-      </wvobject>
       <wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/adr_tag_eq_num_dirty" type="logic" db_ref_id="1">
          <obj_property name="ElementShortName">adr_tag_eq_num_dirty</obj_property>
          <obj_property name="ObjectShortName">adr_tag_eq_num_dirty</obj_property>
@@ -780,6 +800,31 @@
          <obj_property name="ElementShortName">mem_wrrq_int</obj_property>
          <obj_property name="ObjectShortName">mem_wrrq_int</obj_property>
       </wvobject>
+      <wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/mfi" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">mfi</obj_property>
+         <obj_property name="ObjectShortName">mfi</obj_property>
+      </wvobject>
+      <wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/mfi_index" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">mfi_index[4:0]</obj_property>
+         <obj_property name="ObjectShortName">mfi_index[4:0]</obj_property>
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/mfi_num" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">mfi_num[0:0]</obj_property>
+         <obj_property name="ObjectShortName">mfi_num[0:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/mfi_index_ctr_en" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">mfi_index_ctr_en</obj_property>
+         <obj_property name="ObjectShortName">mfi_index_ctr_en</obj_property>
+      </wvobject>
+      <wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/mfi_num_ctr_en" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">mfi_num_ctr_en</obj_property>
+         <obj_property name="ObjectShortName">mfi_num_ctr_en</obj_property>
+      </wvobject>
+      <wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/mfi_num_dirty" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">mfi_num_dirty</obj_property>
+         <obj_property name="ObjectShortName">mfi_num_dirty</obj_property>
+      </wvobject>
       <wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/user_cc_req_flush" type="logic" db_ref_id="1">
          <obj_property name="ElementShortName">user_cc_req_flush</obj_property>
          <obj_property name="ObjectShortName">user_cc_req_flush</obj_property>
@@ -788,9 +833,9 @@
          <obj_property name="ElementShortName">user_cc_req_inval</obj_property>
          <obj_property name="ObjectShortName">user_cc_req_inval</obj_property>
       </wvobject>
-      <wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/user_cc_read" type="logic" db_ref_id="1">
-         <obj_property name="ElementShortName">user_cc_read</obj_property>
-         <obj_property name="ObjectShortName">user_cc_read</obj_property>
+      <wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/user_cc_req_none" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">user_cc_req_none</obj_property>
+         <obj_property name="ObjectShortName">user_cc_req_none</obj_property>
       </wvobject>
       <wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/wb_ddr_ctrl_wb_sc_fe_fsm_inst/state" type="other" db_ref_id="1">
          <obj_property name="ElementShortName">state</obj_property>
@@ -868,6 +913,7 @@
       <wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/dout" type="array" db_ref_id="1">
          <obj_property name="ElementShortName">dout[63:0]</obj_property>
          <obj_property name="ObjectShortName">dout[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
       </wvobject>
       <wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/adr" type="array" db_ref_id="1">
          <obj_property name="ElementShortName">adr[22:0]</obj_property>
@@ -905,6 +951,7 @@
       <wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/ddr_address" type="array" db_ref_id="1">
          <obj_property name="ElementShortName">ddr_address[22:0]</obj_property>
          <obj_property name="ObjectShortName">ddr_address[22:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
       </wvobject>
       <wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/ddr_address_en" type="logic" db_ref_id="1">
          <obj_property name="ElementShortName">ddr_address_en</obj_property>
@@ -913,6 +960,7 @@
       <wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/ddr_dout" type="array" db_ref_id="1">
          <obj_property name="ElementShortName">ddr_dout[31:0]</obj_property>
          <obj_property name="ObjectShortName">ddr_dout[31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
       </wvobject>
       <wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/ddr_dout_en" type="logic" db_ref_id="1">
          <obj_property name="ElementShortName">ddr_dout_en</obj_property>
@@ -945,6 +993,7 @@
       <wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/dout_low" type="array" db_ref_id="1">
          <obj_property name="ElementShortName">dout_low[31:0]</obj_property>
          <obj_property name="ObjectShortName">dout_low[31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
       </wvobject>
       <wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/dout_low_en" type="logic" db_ref_id="1">
          <obj_property name="ElementShortName">dout_low_en</obj_property>
@@ -958,10 +1007,6 @@
          <obj_property name="ElementShortName">ctrl_state</obj_property>
          <obj_property name="ObjectShortName">ctrl_state</obj_property>
       </wvobject>
-      <wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/wb_ddr_ctrl_wb_dc_fsm_inst/burst_start_adr" type="array" db_ref_id="1">
-         <obj_property name="ElementShortName">burst_start_adr[12:0]</obj_property>
-         <obj_property name="ObjectShortName">burst_start_adr[12:0]</obj_property>
-      </wvobject>
       <wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/wb_ddr_ctrl_wb_dc_fsm_inst/fifo_pending" type="logic" db_ref_id="1">
          <obj_property name="ElementShortName">fifo_pending</obj_property>
          <obj_property name="ObjectShortName">fifo_pending</obj_property>