From cac9a8a60f58c856554b5326f92d080262445a5a Mon Sep 17 00:00:00 2001
From: Matthias Blankertz <matthias@blankertz.org>
Date: Sat, 2 Mar 2013 12:29:07 +0100
Subject: [PATCH] - Corrected write timing

---
 src/wb_ddr_ctrl_wb_dc_fsm.vhd | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/wb_ddr_ctrl_wb_dc_fsm.vhd b/src/wb_ddr_ctrl_wb_dc_fsm.vhd
index 80212ad..a0c9e49 100755
--- a/src/wb_ddr_ctrl_wb_dc_fsm.vhd
+++ b/src/wb_ddr_ctrl_wb_dc_fsm.vhd
@@ -70,7 +70,7 @@ constant ctrl_command_read : std_logic_vector(2 downto 0) := "110";
 
 -- DDR-side FSM
 type ctrl_states is (S_RESET, S_INITIALIZE, S_WAITINITDONE, S_IDLE, S_REFRESH, S_REQUEST_INIT, S_WRITE1,
-                     S_WRITE2, S_WRITE3, S_WRITE4, S_WRITE_END1, S_WRITE_END2, S_READ1, S_READ2,
+                     S_WRITE2, S_WRITE3, S_WRITE_END1, S_WRITE_END2, S_WRITE_END3, S_READ1, S_READ2,
                      S_READ3, S_READ4, S_READ5, S_READ_END1, S_READ_END2);
 signal ctrl_state : ctrl_states := S_RESET;
 signal burst_start_adr : std_ulogic_vector(12 downto 0) := (others => '-');
@@ -143,13 +143,13 @@ ctrl_fsm_state : process(ddr2_clk180)
               ctrl_state <= S_WRITE3;
             end if;
           when S_WRITE3 =>
-            ctrl_state <= S_WRITE4;
-          when S_WRITE4 =>
             ctrl_state <= S_WRITE2;
             
           when S_WRITE_END1 =>
             ctrl_state <= S_WRITE_END2;
           when S_WRITE_END2 =>
+            ctrl_state <= S_WRITE_END3;
+          when S_WRITE_END3 =>
             if ctrl_cmd_ack = '0' then
               ctrl_state <= S_IDLE;
             end if;
@@ -243,7 +243,7 @@ ctrl_fsm_out : process(ctrl_state, ddr2_reset, we, ctrl_cmd_ack, fifo_from_sys_v
         if fifo_from_sys_valid = '0' or row_addr /= burst_start_adr or
            we = '0' or ctrl_auto_ref_req = '1' then
           -- next request incompatible with burst type, or auto refresh requested
-          ctrl_burst_done_d <= '1';
+         
         else
           ddr_dmask_en <= '1';
           ddr_dout_en <= '1';
@@ -257,11 +257,11 @@ ctrl_fsm_out : process(ctrl_state, ddr2_reset, we, ctrl_cmd_ack, fifo_from_sys_v
         ddr_dout_high <= '1';
         ddr_address_en <= '1';
         ctrl_command_register_d <= ctrl_command_write;
-      when S_WRITE4 =>
-        ctrl_command_register_d <= ctrl_command_write;
         fifo_from_sys_read_int <= '1';
       when S_WRITE_END1 =>
         ctrl_burst_done_d <= '1';
+      when S_WRITE_END2 =>
+        ctrl_burst_done_d <= '1';
 
       when S_READ1 =>
         ctrl_command_register_d <= ctrl_command_read;