------------------------------------------------------------------------------- -- Title : Testbench for design "toplevel" -- Project : ------------------------------------------------------------------------------- -- File : toplevel_tb.vhd -- Author : -- Company : -- Created : 2013-03-02 -- Last update: 2013-06-07 -- Platform : -- Standard : VHDL'87 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- -- Copyright (c) 2013 ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2013-03-02 1.0 Matthias Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use work.sim_bmppack.all; ------------------------------------------------------------------------------- entity toplevel_tb is end toplevel_tb; ------------------------------------------------------------------------------- architecture testbench of toplevel_tb is component toplevel generic ( dontcare : std_logic ); port ( clkin_50MHz : IN std_ulogic; clkin_133MHz : IN std_ulogic; reset : IN std_ulogic; vga_r, vga_g, vga_b : OUT std_logic_vector(3 downto 0); vga_vsync, vga_hsync : OUT std_ulogic; dataflash_mosi, dataflash_sck, dataflash_ss, dataflash_wp, dataflash_rst : OUT std_ulogic; dataflash_miso : IN std_ulogic; -- led : OUT std_ulogic_vector(7 downto 0); ddr2_dq : inout std_logic_vector(15 downto 0); ddr2_a : out std_logic_vector(12 downto 0); ddr2_ba : out std_logic_vector(1 downto 0); ddr2_cke : out std_logic; ddr2_cs_n : out std_logic; ddr2_ras_n : out std_logic; ddr2_cas_n : out std_logic; ddr2_we_n : out std_logic; ddr2_odt : out std_logic; ddr2_dm : out std_logic_vector(1 downto 0); rst_dqs_div_in : in std_logic; rst_dqs_div_out : out std_logic; ddr2_dqs : inout std_logic_vector(1 downto 0); ddr2_dqs_n : inout std_logic_vector(1 downto 0); ddr2_ck : out std_logic_vector(0 downto 0); ddr2_ck_n : out std_logic_vector(0 downto 0); rs232_txd : out std_logic; rs232_rxd : in std_logic; sd_miso : in std_logic; sd_mosi : out std_logic; sd_cs : out std_logic; sd_sck : out std_logic ); end component; component ddr2_model port ( ck : in std_logic; ck_n : in std_logic; cke : in std_logic; cs_n : in std_logic; ras_n : in std_logic; cas_n : in std_logic; we_n : in std_logic; dm_rdqs : inout std_logic_vector(1 downto 0); ba : in std_logic_vector(1 downto 0); addr : in std_logic_vector(12 downto 0); dq : inout std_logic_vector(15 downto 0); dqs : inout std_logic_vector(1 downto 0); dqs_n : inout std_logic_vector(1 downto 0); rdqs_n : out std_logic_vector(1 downto 0); odt : in std_logic ); end component; constant dontcare : std_logic := '0'; -- component ports signal clkin_50MHz : std_ulogic := '0'; signal clkin_133MHz : std_ulogic := '0'; signal reset : std_ulogic := '0'; signal vga_r, vga_g, vga_b : std_logic_vector(3 downto 0); signal vga_vsync, vga_hsync : std_ulogic; signal dataflash_mosi, dataflash_sck, dataflash_ss, dataflash_wp, dataflash_rst : std_ulogic; signal dataflash_miso : std_ulogic; signal led : std_ulogic_vector(7 downto 0); signal ddr2_dq : std_logic_vector(15 downto 0); signal ddr2_a : std_logic_vector(12 downto 0); signal ddr2_ba : std_logic_vector(1 downto 0); signal ddr2_cke : std_logic; signal ddr2_cs_n : std_logic; signal ddr2_ras_n : std_logic; signal ddr2_cas_n : std_logic; signal ddr2_we_n : std_logic; signal ddr2_odt : std_logic; signal ddr2_dm : std_logic_vector(1 downto 0); signal rst_dqs_div_in : std_logic; signal rst_dqs_div_out : std_logic; signal ddr2_dqs : std_logic_vector(1 downto 0); signal ddr2_dqs_n : std_logic_vector(1 downto 0); signal ddr2_ck : std_logic_vector(0 downto 0); signal ddr2_ck_n : std_logic_vector(0 downto 0); signal rs232_txd, rs232_rxd : std_logic := '1'; signal sd_mosi, sd_miso, sd_cs, sd_sck : std_logic := '0'; signal sim_done : boolean := false; begin -- testbench -- component instantiation DUT: toplevel generic map ( dontcare => dontcare ) port map ( clkin_50MHz => clkin_50MHz, clkin_133MHz => clkin_133MHz, reset => reset, vga_r => vga_r, vga_g => vga_g, vga_b => vga_b, vga_vsync => vga_vsync, vga_hsync => vga_hsync, dataflash_mosi => dataflash_mosi, dataflash_sck => dataflash_sck, dataflash_ss => dataflash_ss, dataflash_wp => dataflash_wp, dataflash_rst => dataflash_rst, dataflash_miso => dataflash_miso, -- led => led, ddr2_dq => ddr2_dq, ddr2_a => ddr2_a, ddr2_ba => ddr2_ba, ddr2_cke => ddr2_cke, ddr2_cs_n => ddr2_cs_n, ddr2_ras_n => ddr2_ras_n, ddr2_cas_n => ddr2_cas_n, ddr2_we_n => ddr2_we_n, ddr2_odt => ddr2_odt, ddr2_dm => ddr2_dm, rst_dqs_div_in => rst_dqs_div_in, rst_dqs_div_out => rst_dqs_div_out, ddr2_dqs => ddr2_dqs, ddr2_dqs_n => ddr2_dqs_n, ddr2_ck => ddr2_ck, ddr2_ck_n => ddr2_ck_n, rs232_txd => rs232_txd, rs232_rxd => rs232_rxd, sd_mosi => sd_mosi, sd_miso => sd_miso, sd_cs => sd_cs, sd_sck => sd_sck); rst_dqs_div_in <= rst_dqs_div_out after 100 ps; rs232_rxd <= rs232_txd; ddr2_model_inst : ddr2_model port map ( ck => ddr2_ck(0), ck_n => ddr2_ck_n(0), cke => ddr2_cke, cs_n => ddr2_cs_n, ras_n => ddr2_ras_n, cas_n => ddr2_cas_n, we_n => ddr2_we_n, dm_rdqs => ddr2_dm, ba => ddr2_ba, addr => ddr2_a, dq => ddr2_dq, dqs => ddr2_dqs, dqs_n => ddr2_dqs_n, rdqs_n => open, odt => ddr2_odt); -- clock generation clkin_133MHz <= not clkin_133MHz after 3.7594 ns when sim_done = false else '0'; clkin_50MHz <= not clkin_50MHz after 10 ns when sim_done = false else '0'; -- waveform generation WaveGen_Proc: process begin -- insert signal assignments here wait; end process WaveGen_Proc; VGARead: process variable i: integer := 0; variable pixeldata : std_logic_vector(23 downto 0); begin ReadFile("vga.bmp"); wait for 100 ns; -- wait for uut to stat wait until rising_edge(vga_vsync); -- wait for vga frame to start (depends -- on latency of UUT) wait for 1061.76 us; while true loop for y in 479 downto 0 loop for x in 0 to 639 loop pixeldata := std_logic_vector(vga_r) & "0000" & std_logic_vector(vga_g) & "0000" & std_logic_vector(vga_b) & "0000"; SetPixel(x, y, pixeldata); wait for 40 ns; end loop; -- x wait for 6400 ns; end loop; -- x wait for 1440 us; WriteFile("vga" & integer'image(i) & ".bmp"); i := i + 1; if i = 4 then sim_done <= true; wait; end if; end loop; end process; end testbench; ------------------------------------------------------------------------------- configuration toplevel_tb_testbench_cfg of toplevel_tb is for testbench end for; end toplevel_tb_testbench_cfg; -------------------------------------------------------------------------------