clkin_50mhz clkin_50mhz clkin_133mhz clkin_133mhz reset reset vga_r[3:0] vga_r[3:0] HEXRADIX vga_g[3:0] vga_g[3:0] HEXRADIX vga_b[3:0] vga_b[3:0] HEXRADIX vga_vsync vga_vsync vga_hsync vga_hsync led[7:0] led[7:0] dataflash_mosi dataflash_mosi dataflash_sck dataflash_sck dataflash_ss dataflash_ss dataflash_wp dataflash_wp dataflash_rst dataflash_rst dataflash_miso dataflash_miso ddr2_dq[15:0] ddr2_dq[15:0] HEXRADIX ddr2_a[12:0] ddr2_a[12:0] ddr2_ba[1:0] ddr2_ba[1:0] ddr2_cke ddr2_cke ddr2_cs_n ddr2_cs_n ddr2_ras_n ddr2_ras_n ddr2_cas_n ddr2_cas_n ddr2_we_n ddr2_we_n ddr2_odt ddr2_odt ddr2_dm[1:0] ddr2_dm[1:0] rst_dqs_div_in rst_dqs_div_in rst_dqs_div_out rst_dqs_div_out ddr2_dqs[1:0] ddr2_dqs[1:0] ddr2_dqs_n[1:0] ddr2_dqs_n[1:0] ddr2_ck[0:0] ddr2_ck[0:0] ddr2_ck_n[0:0] ddr2_ck_n[0:0] rs232_txd rs232_txd rs232_rxd rs232_rxd sysclk sysclk sysrst sysrst vga_mem_rdrq vga_mem_rdrq vga_mem_adr[19:0] vga_mem_adr[19:0] HEXRADIX vga_mem_ack vga_mem_ack vga_mem_dat_i[63:0] vga_mem_dat_i[63:0] HEXRADIX cpu_wbm_o cpu_wbm_o .dat_o cpu_wbm_o.dat_o HEXRADIX .we_o cpu_wbm_o.we_o .sel_o cpu_wbm_o.sel_o HEXRADIX .adr_o cpu_wbm_o.adr_o HEXRADIX .cyc_o cpu_wbm_o.cyc_o .stb_o cpu_wbm_o.stb_o cpu_wbm_i cpu_wbm_i .dat_i cpu_wbm_i.dat_i HEXRADIX .ack_i cpu_wbm_i.ack_i rom_wbs_o rom_wbs_o .dat_o rom_wbs_o.dat_o HEXRADIX .ack_o rom_wbs_o.ack_o rom_wbs_i rom_wbs_i .sel_i rom_wbs_i.sel_i .adr_i rom_wbs_i.adr_i HEXRADIX .cyc_i rom_wbs_i.cyc_i .stb_i rom_wbs_i.stb_i ram_wbs_o ram_wbs_o .dat_o ram_wbs_o.dat_o HEXRADIX .ack_o ram_wbs_o.ack_o ram_wbs_i ram_wbs_i .dat_i ram_wbs_i.dat_i HEXRADIX .we_i ram_wbs_i.we_i .sel_i ram_wbs_i.sel_i .adr_i ram_wbs_i.adr_i HEXRADIX .cyc_i ram_wbs_i.cyc_i .stb_i ram_wbs_i.stb_i uart_wbs_i uart_wbs_i .dat_i uart_wbs_i.dat_i HEXRADIX .we_i uart_wbs_i.we_i .adr_i uart_wbs_i.adr_i .cyc_i uart_wbs_i.cyc_i .stb_i uart_wbs_i.stb_i uart_wbs_o uart_wbs_o .dat_o uart_wbs_o.dat_o HEXRADIX .ack_o uart_wbs_o.ack_o spi_sd_wbs_i spi_sd_wbs_i spi_sd_wbs_o spi_sd_wbs_o fb_flip fb_flip fb_flip_ack fb_flip_ack fb_in_use fb_in_use cpu label cpu_wrapper label mb_imem_o mb_imem_o .adr_o mb_imem_o.adr_o HEXRADIX .ena_o mb_imem_o.ena_o mb_imem_i mb_imem_i .dat_i mb_imem_i.dat_i HEXRADIX mb_wb_o mb_wb_o .adr_o mb_wb_o.adr_o HEXRADIX .dat_o mb_wb_o.dat_o HEXRADIX .we_o mb_wb_o.we_o .stb_o mb_wb_o.stb_o .sel_o mb_wb_o.sel_o .cyc_o mb_wb_o.cyc_o mb_wb_i mb_wb_i .clk_i mb_wb_i.clk_i .rst_i mb_wb_i.rst_i .dat_i mb_wb_i.dat_i HEXRADIX .ack_i mb_wb_i.ack_i .int_i mb_wb_i.int_i cpu label dmem_o dmem_o .dat_o dmem_o.dat_o HEXRADIX .adr_o dmem_o.adr_o HEXRADIX .sel_o dmem_o.sel_o .we_o dmem_o.we_o .ena_o dmem_o.ena_o dmem_i dmem_i .dat_i dmem_i.dat_i HEXRADIX .ena_i dmem_i.ena_i fetch_i fetch_i .hazard fetch_i.hazard .branch fetch_i.branch .branch_target fetch_i.branch_target HEXRADIX fetch_o fetch_o HEXRADIX .program_counter fetch_o.program_counter HEXRADIX decode_i decode_i .program_counter decode_i.program_counter HEXRADIX .instruction decode_i.instruction HEXRADIX .ctrl_wrb decode_i.ctrl_wrb .reg_d decode_i.ctrl_wrb.reg_d UNSIGNEDDECRADIX .reg_write decode_i.ctrl_wrb.reg_write .ctrl_mem_wrb decode_i.ctrl_mem_wrb .mem_result decode_i.mem_result HEXRADIX .alu_result decode_i.alu_result HEXRADIX .interrupt decode_i.interrupt .flush_id decode_i.flush_id decode_o decode_o gprf_o gprf_o exec_i exec_i exec_o exec_o .alu_result exec_o.alu_result HEXRADIX .dat_d exec_o.dat_d .branch exec_o.branch .program_counter exec_o.program_counter .flush_id exec_o.flush_id .ctrl_mem exec_o.ctrl_mem .ctrl_wrb exec_o.ctrl_wrb mem_i mem_i .dat_d mem_i.dat_d HEXRADIX .alu_result mem_i.alu_result HEXRADIX .mem_result mem_i.mem_result HEXRADIX .program_counter mem_i.program_counter .branch mem_i.branch .ctrl_mem mem_i.ctrl_mem .ctrl_wrb mem_i.ctrl_wrb .reg_d mem_i.ctrl_wrb.reg_d UNSIGNEDDECRADIX .reg_write mem_i.ctrl_wrb.reg_write mem_o mem_o .alu_result mem_o.alu_result HEXRADIX .ctrl_wrb mem_o.ctrl_wrb .reg_d mem_o.ctrl_wrb.reg_d UNSIGNEDDECRADIX .reg_write mem_o.ctrl_wrb.reg_write .ctrl_mem_wrb mem_o.ctrl_mem_wrb ena_i ena_i r r rin rin r r rin rin reg reg regin regin wb_dat_d[31:0] wb_dat_d[31:0] r r rin rin reg reg regin regin r r rin rin mem_result[31:0] mem_result[31:0] HEXRADIX ram[31:0] ram[31:0] HEXRADIX [31] ram[31] HEXRADIX [30] ram[30] HEXRADIX [29] ram[29] HEXRADIX [28] ram[28] HEXRADIX [27] ram[27] HEXRADIX [26] ram[26] HEXRADIX [25] ram[25] HEXRADIX [24] ram[24] HEXRADIX [23] ram[23] HEXRADIX [22] ram[22] HEXRADIX [21] ram[21] HEXRADIX [20] ram[20] HEXRADIX [19] ram[19] HEXRADIX [18] ram[18] HEXRADIX [17] ram[17] HEXRADIX [16] ram[16] HEXRADIX [15] ram[15] HEXRADIX [14] ram[14] HEXRADIX [13] ram[13] HEXRADIX [12] ram[12] HEXRADIX [11] ram[11] HEXRADIX [10] ram[10] HEXRADIX [9] ram[9] HEXRADIX [8] ram[8] HEXRADIX [7] ram[7] HEXRADIX [6] ram[6] HEXRADIX [5] ram[5] HEXRADIX [4] ram[4] HEXRADIX [3] ram[3] HEXRADIX [2] ram[2] HEXRADIX [1] ram[1] HEXRADIX [0] ram[0] HEXRADIX ram[31:0] ram[31:0] HEXRADIX ram[31:0] ram[31:0] HEXRADIX vga_pixelgen_1 label clk clk rst rst pixeldata[63:0] pixeldata[63:0] HEXRADIX fifo_write fifo_write fifo_full16 fifo_full16 fifo_rst fifo_rst vsync vsync mem_rdrq mem_rdrq mem_adr[19:0] mem_adr[19:0] HEXRADIX mem_ack mem_ack mem_dat_i[63:0] mem_dat_i[63:0] state state addr_ctr addr_ctr burst_ctr burst_ctr fb_in_use_int fb_in_use_int flip_req flip_req fb_flip_last fb_flip_last fb_flip_ack_int fb_flip_ack_int ddr_ctrl_sc label clk_i clk_i rst_i rst_i vga_mem_rdrq vga_mem_rdrq vga_mem_adr[19:0] vga_mem_adr[19:0] HEXRADIX vga_mem_ack vga_mem_ack vga_mem_dat_i[63:0] vga_mem_dat_i[63:0] HEXRADIX ddr_din[63:0] ddr_din[63:0] HEXRADIX ddr_dout[63:0] ddr_dout[63:0] HEXRADIX ddr_adr[22:0] ddr_adr[22:0] HEXRADIX ddr_we ddr_we ddr_be[7:0] ddr_be[7:0] fifo_to_ddr_write fifo_to_ddr_write fifo_from_ddr_read fifo_from_ddr_read fifo_to_ddr_full fifo_to_ddr_full fifo_from_ddr_empty fifo_from_ddr_empty dout_data_valid dout_data_valid bus_owner bus_owner bus_owner_reg bus_owner_reg out_ctr out_ctr in_ctr in_ctr out_complete out_complete in_complete in_complete in_read in_read in_write in_write fifo_to_ddr_full_last fifo_to_ddr_full_last cfe label ddr_ctrl_dc label ddr2_clk0 ddr2_clk0 ddr2_clk180 ddr2_clk180 ddr2_clk90 ddr2_clk90 ddr2_reset ddr2_reset ctrl_input_data[31:0] ctrl_input_data[31:0] ctrl_data_mask[3:0] ctrl_data_mask[3:0] ctrl_output_data[31:0] ctrl_output_data[31:0] ctrl_data_valid ctrl_data_valid ctrl_input_address[24:0] ctrl_input_address[24:0] ctrl_command_register[2:0] ctrl_command_register[2:0] ctrl_burst_done ctrl_burst_done ctrl_auto_ref_req ctrl_auto_ref_req ctrl_cmd_ack ctrl_cmd_ack ctrl_init_done ctrl_init_done ctrl_ar_done ctrl_ar_done din[63:0] din[63:0] HEXRADIX dout[63:0] dout[63:0] HEXRADIX adr[22:0] adr[22:0] HEXRADIX we we be[7:0] be[7:0] fifo_to_sys_write fifo_to_sys_write fifo_from_sys_read fifo_from_sys_read fifo_to_sys_full fifo_to_sys_full fifo_from_sys_empty fifo_from_sys_empty fifo_from_sys_almost_empty fifo_from_sys_almost_empty ddr_address[22:0] ddr_address[22:0] HEXRADIX ddr_address_en ddr_address_en ddr_dout[31:0] ddr_dout[31:0] HEXRADIX ddr_dout_en ddr_dout_en ddr_dout_high ddr_dout_high ddr_dmask[3:0] ddr_dmask[3:0] ddr_dmask_rst ddr_dmask_rst ddr_dmask_en ddr_dmask_en ctrl_command_register_d[2:0] ctrl_command_register_d[2:0] ctrl_burst_done_d ctrl_burst_done_d dout_low[31:0] dout_low[31:0] HEXRADIX dout_low_en dout_low_en ctrl_data_valid_toggle ctrl_data_valid_toggle ctrl_state ctrl_state fifo_pending fifo_pending fifo_from_sys_read_int fifo_from_sys_read_int fifo_from_sys_valid fifo_from_sys_valid pio_led label pio_out[7:0] pio_out[7:0] pio_reg[31:0] pio_reg[31:0] pio_sr[0:2] pio_sr[0:2] uart label clk clk serialin serialin serialout serialout dataout[7:0] dataout[7:0] HEXRADIX datain[7:0] datain[7:0] HEXRADIX readfifostb readfifostb writefifostb writefifostb readfull readfull readempty readempty writefull writefull writeempty writeempty pulse16 pulse16 readstb readstb done done full_read full_read empty_read empty_read writestb writestb full_write full_write empty_write empty_write load load writefifo_readstb writefifo_readstb read_data_in[7:0] read_data_in[7:0] HEXRADIX read_data_out[7:0] read_data_out[7:0] HEXRADIX write_data_out[7:0] write_data_out[7:0] HEXRADIX readctrl label rs232in_ff rs232in_ff sr8[7:0] sr8[7:0] sr16[15:0] sr16[15:0] dly10_sr10[9:0] dly10_sr10[9:0] start start running running shift[7:0] shift[7:0] HEXRADIX spi label clk_divider[5:0] clk_divider[5:0] clk_ctr[5:0] clk_ctr[5:0] spi_clk spi_clk spi_clk_dly spi_clk_dly spi_clk_rst spi_clk_rst spi_clk_inv spi_clk_inv sclk_o_en sclk_o_en sclk_o_d0 sclk_o_d0 sclk_o_d1 sclk_o_d1 spi_state spi_state spi_idle spi_idle indata_pending indata_pending spi_ctr spi_ctr sreg[8:0] sreg[8:0] infifo_rd infifo_rd infifo_wr infifo_wr infifo_full infifo_full infifo_empty infifo_empty infifo_din[7:0] infifo_din[7:0] infifo_dout[7:0] infifo_dout[7:0] outfifo_rd outfifo_rd outfifo_wr outfifo_wr outfifo_full outfifo_full outfifo_empty outfifo_empty outfifo_din[7:0] outfifo_din[7:0] outfifo_dout[7:0] outfifo_dout[7:0] wb_in_cyc wb_in_cyc ack_o_int ack_o_int