sim_done sim_done delay delay readrate readrate fifo[0:127] fifo[0:127] fifo_rdptr fifo_rdptr fifo_wrptr fifo_wrptr wrptr_dly[8:0] wrptr_dly[8:0] clk_i clk_i rst_i rst_i vga_mem_rdrq vga_mem_rdrq vga_mem_adr[19:0] vga_mem_adr[19:0] HEXRADIX vga_mem_ack vga_mem_ack vga_mem_dat_i[63:0] vga_mem_dat_i[63:0] HEXRADIX wb_mem_rdrq wb_mem_rdrq wb_mem_wrrq wb_mem_wrrq wb_mem_adr[19:0] wb_mem_adr[19:0] HEXRADIX wb_mem_dat_o[63:0] wb_mem_dat_o[63:0] HEXRADIX wb_mem_sel[7:0] wb_mem_sel[7:0] wb_mem_ack wb_mem_ack wb_mem_dat_i[63:0] wb_mem_dat_i[63:0] HEXRADIX ddr_din[63:0] ddr_din[63:0] HEXRADIX ddr_dout[63:0] ddr_dout[63:0] HEXRADIX ddr_adr[22:0] ddr_adr[22:0] HEXRADIX ddr_we ddr_we ddr_be[7:0] ddr_be[7:0] fifo_to_ddr_write fifo_to_ddr_write fifo_from_ddr_read fifo_from_ddr_read fifo_to_ddr_full fifo_to_ddr_full fifo_from_ddr_empty fifo_from_ddr_empty p_rdrq[1:0] p_rdrq[1:0] p_wrrq[1:0] p_wrrq[1:0] p_ack[1:0] p_ack[1:0] p_adr[1:0] p_adr[1:0] HEXRADIX p_dat_o[1:0] p_dat_o[1:0] HEXRADIX p_dat_i[1:0] p_dat_i[1:0] HEXRADIX p_sel[1:0] p_sel[1:0] rdrq_reg[1:0] rdrq_reg[1:0] wrrq_reg[1:0] wrrq_reg[1:0] adr_reg[1:0] adr_reg[1:0] HEXRADIX rq_complete[1:0] rq_complete[1:0] dout_data_valid dout_data_valid bus_owner bus_owner bus_owner_reg bus_owner_reg out_ctr out_ctr in_ctr in_ctr out_complete out_complete in_complete in_complete in_read in_read in_write in_write fifo_to_ddr_full_last fifo_to_ddr_full_last