clk_i clk_i rst_i rst_i wbs_i wbs_i .dat_i wbs_i.dat_i HEXRADIX .we_i wbs_i.we_i .sel_i wbs_i.sel_i .adr_i wbs_i.adr_i HEXRADIX .cyc_i wbs_i.cyc_i .stb_i wbs_i.stb_i wbs_o wbs_o .dat_o wbs_o.dat_o HEXRADIX .ack_o wbs_o.ack_o wb_mem_rdrq wb_mem_rdrq wb_mem_wrrq wb_mem_wrrq wb_mem_adr[19:0] wb_mem_adr[19:0] HEXRADIX wb_mem_dat_o[63:0] wb_mem_dat_o[63:0] HEXRADIX wb_mem_sel[7:0] wb_mem_sel[7:0] wb_mem_ack wb_mem_ack wb_mem_dat_i[63:0] wb_mem_dat_i[63:0] HEXRADIX buf_dirty[63:0] buf_dirty[63:0] buf_valid buf_valid buf_tag[25:6] buf_tag[25:6] HEXRADIX buf_adr[2:0] buf_adr[2:0] UNSIGNEDDECRADIX buf_bwe[7:0] buf_bwe[7:0] buf_hit buf_hit buf_dat_o[63:0] buf_dat_o[63:0] HEXRADIX buf_dat_i[63:0] buf_dat_i[63:0] HEXRADIX wb_in_cyc wb_in_cyc write_flush write_flush read_fill read_fill buf_wbwr buf_wbwr ctr[2:0] ctr[2:0] mem_ctrl label clk_i clk_i rst_i rst_i vga_mem_rdrq vga_mem_rdrq vga_mem_adr[19:0] vga_mem_adr[19:0] vga_mem_ack vga_mem_ack vga_mem_dat_i[63:0] vga_mem_dat_i[63:0] wb_mem_rdrq wb_mem_rdrq wb_mem_wrrq wb_mem_wrrq wb_mem_adr[19:0] wb_mem_adr[19:0] wb_mem_dat_o[63:0] wb_mem_dat_o[63:0] wb_mem_sel[7:0] wb_mem_sel[7:0] wb_mem_ack wb_mem_ack wb_mem_dat_i[63:0] wb_mem_dat_i[63:0] ddr_din[63:0] ddr_din[63:0] ddr_dout[63:0] ddr_dout[63:0] ddr_adr[22:0] ddr_adr[22:0] ddr_we ddr_we ddr_be[7:0] ddr_be[7:0] fifo_to_ddr_write fifo_to_ddr_write fifo_from_ddr_read fifo_from_ddr_read fifo_to_ddr_full fifo_to_ddr_full fifo_from_ddr_empty fifo_from_ddr_empty p_rdrq[1:0] p_rdrq[1:0] p_wrrq[1:0] p_wrrq[1:0] p_ack[1:0] p_ack[1:0] p_adr[1:0] p_adr[1:0] p_dat_o[1:0] p_dat_o[1:0] p_dat_i[1:0] p_dat_i[1:0] p_sel[1:0] p_sel[1:0] rdrq_reg[1:0] rdrq_reg[1:0] wrrq_reg[1:0] wrrq_reg[1:0] adr_reg[1:0] adr_reg[1:0] rq_complete[1:0] rq_complete[1:0] dout_data_valid dout_data_valid bus_owner bus_owner bus_owner_reg bus_owner_reg out_ctr out_ctr in_ctr in_ctr out_complete out_complete in_complete in_complete in_read in_read in_write in_write fifo_to_ddr_full_last fifo_to_ddr_full_last