Matthias Blankertz
0a96ce78f0
- WIP: New cache for CPU - Memory controller now supports modulu bursts and different burst lengths - WIP: Timing problems...
16 lines
462 B
Plaintext
16 lines
462 B
Plaintext
# Timing constraints
|
|
NET "CLKIN_50MHZ" PERIOD = 20.0ns HIGH 40%;
|
|
NET "CLKIN_133MHZ" PERIOD = 7.51ns HIGH 40%;
|
|
|
|
#TIMESPEC TSfalse1 = FROM FFS(cpu_inst_mblite_wbm_inst/wbm_o.adr_o*)
|
|
|
|
#MODEL wb_ddr_ctrl_ddrwrap keep_hierarchy = yes ;
|
|
#MODEL vhdl_bl4_infrastructure_top keep_hierarchy = yes ;
|
|
#MODEL vhdl_bl4_cal_top keep_hierarchy = yes;
|
|
|
|
|
|
#BEGIN MODEL vhdl_bl4_cal_top
|
|
# INST cal_ctl0 keep_hierarchy = yes ;
|
|
# INST tap_dly0 keep_hierarchy = yes ;
|
|
#END;
|