Matthias Blankertz
90631f89bd
- Started changing DDR controller interface to 64 bit bus width - Debugging
119 lines
6.1 KiB
XML
119 lines
6.1 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<wave_config>
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<wave_state>
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</wave_state>
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<db_ref_list>
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<db_ref path="./isim.wdb" id="1" type="auto">
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<top_modules>
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<top_module name="intercon_package" />
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<top_module name="numeric_std" />
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<top_module name="sim_bmppack" />
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<top_module name="std_logic_1164" />
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<top_module name="std_logic_arith" />
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<top_module name="std_logic_unsigned" />
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<top_module name="vga_tb" />
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</top_modules>
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</db_ref>
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</db_ref_list>
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<WVObjectSize size="24" />
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<wvobject fp_name="/vga_tb/DUT/clk_in" type="logic" db_ref_id="1">
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<obj_property name="ElementShortName">clk_in</obj_property>
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<obj_property name="ObjectShortName">clk_in</obj_property>
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</wvobject>
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<wvobject fp_name="/vga_tb/DUT/clk_vga" type="logic" db_ref_id="1">
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<obj_property name="ElementShortName">clk_vga</obj_property>
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<obj_property name="ObjectShortName">clk_vga</obj_property>
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</wvobject>
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<wvobject fp_name="/vga_tb/DUT/rst" type="logic" db_ref_id="1">
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<obj_property name="ElementShortName">rst</obj_property>
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<obj_property name="ObjectShortName">rst</obj_property>
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</wvobject>
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<wvobject fp_name="/vga_tb/DUT/mem_rdrq" type="logic" db_ref_id="1">
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<obj_property name="ElementShortName">mem_rdrq</obj_property>
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<obj_property name="ObjectShortName">mem_rdrq</obj_property>
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</wvobject>
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<wvobject fp_name="/vga_tb/DUT/mem_adr" type="array" db_ref_id="1">
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<obj_property name="ElementShortName">mem_adr[19:0]</obj_property>
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<obj_property name="ObjectShortName">mem_adr[19:0]</obj_property>
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</wvobject>
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<wvobject fp_name="/vga_tb/DUT/mem_ack" type="logic" db_ref_id="1">
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<obj_property name="ElementShortName">mem_ack</obj_property>
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<obj_property name="ObjectShortName">mem_ack</obj_property>
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</wvobject>
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<wvobject fp_name="/vga_tb/DUT/mem_dat_i" type="array" db_ref_id="1">
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<obj_property name="ElementShortName">mem_dat_i[31:0]</obj_property>
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<obj_property name="ObjectShortName">mem_dat_i[31:0]</obj_property>
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<obj_property name="Radix">HEXRADIX</obj_property>
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</wvobject>
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<wvobject fp_name="/vga_tb/DUT/red" type="array" db_ref_id="1">
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<obj_property name="ElementShortName">red[3:0]</obj_property>
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<obj_property name="ObjectShortName">red[3:0]</obj_property>
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</wvobject>
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<wvobject fp_name="/vga_tb/DUT/green" type="array" db_ref_id="1">
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<obj_property name="ElementShortName">green[3:0]</obj_property>
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<obj_property name="ObjectShortName">green[3:0]</obj_property>
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</wvobject>
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<wvobject fp_name="/vga_tb/DUT/blue" type="array" db_ref_id="1">
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<obj_property name="ElementShortName">blue[3:0]</obj_property>
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<obj_property name="ObjectShortName">blue[3:0]</obj_property>
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</wvobject>
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<wvobject fp_name="/vga_tb/DUT/vsync" type="logic" db_ref_id="1">
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<obj_property name="ElementShortName">vsync</obj_property>
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<obj_property name="ObjectShortName">vsync</obj_property>
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</wvobject>
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<wvobject fp_name="/vga_tb/DUT/hsync" type="logic" db_ref_id="1">
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<obj_property name="ElementShortName">hsync</obj_property>
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<obj_property name="ObjectShortName">hsync</obj_property>
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</wvobject>
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<wvobject fp_name="/vga_tb/DUT/vid_en" type="logic" db_ref_id="1">
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<obj_property name="ElementShortName">vid_en</obj_property>
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<obj_property name="ObjectShortName">vid_en</obj_property>
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</wvobject>
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<wvobject fp_name="/vga_tb/DUT/in_pixeldata" type="array" db_ref_id="1">
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<obj_property name="ElementShortName">in_pixeldata[31:0]</obj_property>
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<obj_property name="ObjectShortName">in_pixeldata[31:0]</obj_property>
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<obj_property name="Radix">HEXRADIX</obj_property>
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</wvobject>
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<wvobject fp_name="/vga_tb/DUT/out_pixeldata" type="array" db_ref_id="1">
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<obj_property name="ElementShortName">out_pixeldata[15:0]</obj_property>
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<obj_property name="ObjectShortName">out_pixeldata[15:0]</obj_property>
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<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
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</wvobject>
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<wvobject fp_name="/vga_tb/DUT/fifo_write" type="logic" db_ref_id="1">
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<obj_property name="ElementShortName">fifo_write</obj_property>
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<obj_property name="ObjectShortName">fifo_write</obj_property>
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</wvobject>
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<wvobject fp_name="/vga_tb/DUT/fifo_read" type="logic" db_ref_id="1">
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<obj_property name="ElementShortName">fifo_read</obj_property>
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<obj_property name="ObjectShortName">fifo_read</obj_property>
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</wvobject>
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<wvobject fp_name="/vga_tb/DUT/fifo_empty" type="logic" db_ref_id="1">
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<obj_property name="ElementShortName">fifo_empty</obj_property>
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<obj_property name="ObjectShortName">fifo_empty</obj_property>
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</wvobject>
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<wvobject fp_name="/vga_tb/DUT/fifo_full16" type="logic" db_ref_id="1">
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<obj_property name="ElementShortName">fifo_full16</obj_property>
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<obj_property name="ObjectShortName">fifo_full16</obj_property>
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</wvobject>
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<wvobject fp_name="/vga_tb/DUT/fifo_rst" type="logic" db_ref_id="1">
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<obj_property name="ElementShortName">fifo_rst</obj_property>
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<obj_property name="ObjectShortName">fifo_rst</obj_property>
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</wvobject>
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<wvobject fp_name="/vga_tb/DUT/vsync_i" type="logic" db_ref_id="1">
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<obj_property name="ElementShortName">vsync_i</obj_property>
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<obj_property name="ObjectShortName">vsync_i</obj_property>
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</wvobject>
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<wvobject fp_name="/vga_tb/DUT/vsync_to_clk_in" type="array" db_ref_id="1">
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<obj_property name="ElementShortName">vsync_to_clk_in[1:0]</obj_property>
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<obj_property name="ObjectShortName">vsync_to_clk_in[1:0]</obj_property>
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</wvobject>
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<wvobject fp_name="/vga_tb/DUT/vga_pixelgen_inst/empty_dly" type="logic" db_ref_id="1">
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<obj_property name="ElementShortName">empty_dly</obj_property>
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<obj_property name="ObjectShortName">empty_dly</obj_property>
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</wvobject>
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<wvobject fp_name="/vga_tb/DUT/vga_pixelgen_inst/data_valid" type="logic" db_ref_id="1">
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<obj_property name="ElementShortName">data_valid</obj_property>
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<obj_property name="ObjectShortName">data_valid</obj_property>
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</wvobject>
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</wave_config>
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