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2d_display_engine-new/wb_ddr_ctrl_wb_sc_tb.wcfg
Matthias Blankertz 0a96ce78f0 - New Wishbone master for CPU 
- WIP: New cache for CPU
- Memory controller now supports modulu bursts and different burst lengths
- WIP: Timing problems...
2013-06-19 09:16:36 +02:00

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<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="./isim.wdb" id="1" type="auto">
<top_modules>
<top_module name="numeric_std" />
<top_module name="std_logic_1164" />
<top_module name="std_logic_1164_additions" />
<top_module name="textio" />
<top_module name="wb_ddr_ctrl_wb_sc_tb" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="57" />
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/sim_done" type="other" db_ref_id="1">
<obj_property name="ElementShortName">sim_done</obj_property>
<obj_property name="ObjectShortName">sim_done</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/delay" type="other" db_ref_id="1">
<obj_property name="ElementShortName">delay</obj_property>
<obj_property name="ObjectShortName">delay</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/readrate" type="other" db_ref_id="1">
<obj_property name="ElementShortName">readrate</obj_property>
<obj_property name="ObjectShortName">readrate</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/fifo" type="array" db_ref_id="1">
<obj_property name="ElementShortName">fifo[0:127]</obj_property>
<obj_property name="ObjectShortName">fifo[0:127]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/fifo_rdptr" type="other" db_ref_id="1">
<obj_property name="ElementShortName">fifo_rdptr</obj_property>
<obj_property name="ObjectShortName">fifo_rdptr</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/fifo_wrptr" type="other" db_ref_id="1">
<obj_property name="ElementShortName">fifo_wrptr</obj_property>
<obj_property name="ObjectShortName">fifo_wrptr</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/wrptr_dly" type="array" db_ref_id="1">
<obj_property name="ElementShortName">wrptr_dly[8:0]</obj_property>
<obj_property name="ObjectShortName">wrptr_dly[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/DUT/clk_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk_i</obj_property>
<obj_property name="ObjectShortName">clk_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/DUT/rst_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rst_i</obj_property>
<obj_property name="ObjectShortName">rst_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/DUT/vga_mem_rdrq" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">vga_mem_rdrq</obj_property>
<obj_property name="ObjectShortName">vga_mem_rdrq</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/DUT/vga_mem_adr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">vga_mem_adr[19:0]</obj_property>
<obj_property name="ObjectShortName">vga_mem_adr[19:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/DUT/vga_mem_ack" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">vga_mem_ack</obj_property>
<obj_property name="ObjectShortName">vga_mem_ack</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/DUT/vga_mem_dat_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">vga_mem_dat_i[63:0]</obj_property>
<obj_property name="ObjectShortName">vga_mem_dat_i[63:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/DUT/wb_mem_rdrq" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">wb_mem_rdrq</obj_property>
<obj_property name="ObjectShortName">wb_mem_rdrq</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/DUT/wb_mem_wrrq" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">wb_mem_wrrq</obj_property>
<obj_property name="ObjectShortName">wb_mem_wrrq</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/DUT/wb_mem_adr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">wb_mem_adr[19:0]</obj_property>
<obj_property name="ObjectShortName">wb_mem_adr[19:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/DUT/wb_mem_dat_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">wb_mem_dat_o[63:0]</obj_property>
<obj_property name="ObjectShortName">wb_mem_dat_o[63:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/DUT/wb_mem_sel" type="array" db_ref_id="1">
<obj_property name="ElementShortName">wb_mem_sel[7:0]</obj_property>
<obj_property name="ObjectShortName">wb_mem_sel[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/DUT/wb_mem_ack" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">wb_mem_ack</obj_property>
<obj_property name="ObjectShortName">wb_mem_ack</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/DUT/wb_mem_dat_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">wb_mem_dat_i[63:0]</obj_property>
<obj_property name="ObjectShortName">wb_mem_dat_i[63:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/cpu_mem_rdrq" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">cpu_mem_rdrq</obj_property>
<obj_property name="ObjectShortName">cpu_mem_rdrq</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/cpu_mem_wrrq" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">cpu_mem_wrrq</obj_property>
<obj_property name="ObjectShortName">cpu_mem_wrrq</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/cpu_mem_adr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cpu_mem_adr[22:0]</obj_property>
<obj_property name="ObjectShortName">cpu_mem_adr[22:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/cpu_mem_dat_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cpu_mem_dat_o[63:0]</obj_property>
<obj_property name="ObjectShortName">cpu_mem_dat_o[63:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/cpu_mem_sel" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cpu_mem_sel[7:0]</obj_property>
<obj_property name="ObjectShortName">cpu_mem_sel[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/cpu_mem_ack" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">cpu_mem_ack</obj_property>
<obj_property name="ObjectShortName">cpu_mem_ack</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/cpu_mem_dat_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cpu_mem_dat_i[63:0]</obj_property>
<obj_property name="ObjectShortName">cpu_mem_dat_i[63:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/DUT/ddr_din" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr_din[63:0]</obj_property>
<obj_property name="ObjectShortName">ddr_din[63:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/DUT/ddr_dout" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr_dout[63:0]</obj_property>
<obj_property name="ObjectShortName">ddr_dout[63:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/DUT/ddr_adr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr_adr[22:0]</obj_property>
<obj_property name="ObjectShortName">ddr_adr[22:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/DUT/ddr_we" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr_we</obj_property>
<obj_property name="ObjectShortName">ddr_we</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/DUT/ddr_be" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr_be[7:0]</obj_property>
<obj_property name="ObjectShortName">ddr_be[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/DUT/fifo_to_ddr_write" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_to_ddr_write</obj_property>
<obj_property name="ObjectShortName">fifo_to_ddr_write</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/DUT/fifo_from_ddr_read" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_from_ddr_read</obj_property>
<obj_property name="ObjectShortName">fifo_from_ddr_read</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/DUT/fifo_to_ddr_full" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_to_ddr_full</obj_property>
<obj_property name="ObjectShortName">fifo_to_ddr_full</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/DUT/fifo_from_ddr_empty" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_from_ddr_empty</obj_property>
<obj_property name="ObjectShortName">fifo_from_ddr_empty</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/DUT/p_rdrq" type="array" db_ref_id="1">
<obj_property name="ElementShortName">p_rdrq[2:0]</obj_property>
<obj_property name="ObjectShortName">p_rdrq[2:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/DUT/p_wrrq" type="array" db_ref_id="1">
<obj_property name="ElementShortName">p_wrrq[2:0]</obj_property>
<obj_property name="ObjectShortName">p_wrrq[2:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/DUT/p_ack" type="array" db_ref_id="1">
<obj_property name="ElementShortName">p_ack[2:0]</obj_property>
<obj_property name="ObjectShortName">p_ack[2:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/DUT/p_adr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">p_adr[2:0]</obj_property>
<obj_property name="ObjectShortName">p_adr[2:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/DUT/p_dat_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">p_dat_o[2:0]</obj_property>
<obj_property name="ObjectShortName">p_dat_o[2:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/DUT/p_dat_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">p_dat_i[2:0]</obj_property>
<obj_property name="ObjectShortName">p_dat_i[2:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/DUT/p_sel" type="array" db_ref_id="1">
<obj_property name="ElementShortName">p_sel[2:0]</obj_property>
<obj_property name="ObjectShortName">p_sel[2:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/DUT/rdrq_reg" type="array" db_ref_id="1">
<obj_property name="ElementShortName">rdrq_reg[2:0]</obj_property>
<obj_property name="ObjectShortName">rdrq_reg[2:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/DUT/wrrq_reg" type="array" db_ref_id="1">
<obj_property name="ElementShortName">wrrq_reg[2:0]</obj_property>
<obj_property name="ObjectShortName">wrrq_reg[2:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/DUT/adr_reg" type="array" db_ref_id="1">
<obj_property name="ElementShortName">adr_reg[2:0]</obj_property>
<obj_property name="ObjectShortName">adr_reg[2:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/DUT/rq_complete" type="array" db_ref_id="1">
<obj_property name="ElementShortName">rq_complete[2:0]</obj_property>
<obj_property name="ObjectShortName">rq_complete[2:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/DUT/dout_data_valid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">dout_data_valid</obj_property>
<obj_property name="ObjectShortName">dout_data_valid</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/DUT/bus_owner" type="other" db_ref_id="1">
<obj_property name="ElementShortName">bus_owner</obj_property>
<obj_property name="ObjectShortName">bus_owner</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/DUT/bus_owner_reg" type="other" db_ref_id="1">
<obj_property name="ElementShortName">bus_owner_reg</obj_property>
<obj_property name="ObjectShortName">bus_owner_reg</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/DUT/out_ctr" type="other" db_ref_id="1">
<obj_property name="ElementShortName">out_ctr</obj_property>
<obj_property name="ObjectShortName">out_ctr</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/DUT/in_ctr" type="other" db_ref_id="1">
<obj_property name="ElementShortName">in_ctr</obj_property>
<obj_property name="ObjectShortName">in_ctr</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/DUT/out_complete" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">out_complete</obj_property>
<obj_property name="ObjectShortName">out_complete</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/DUT/in_complete" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">in_complete</obj_property>
<obj_property name="ObjectShortName">in_complete</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/DUT/in_read" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">in_read</obj_property>
<obj_property name="ObjectShortName">in_read</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/DUT/in_write" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">in_write</obj_property>
<obj_property name="ObjectShortName">in_write</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_wb_sc_tb/DUT/fifo_to_ddr_full_last" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_to_ddr_full_last</obj_property>
<obj_property name="ObjectShortName">fifo_to_ddr_full_last</obj_property>
</wvobject>
</wave_config>
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