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2d_display_engine-new/wb_mem_bridge_tb.wcfg
Matthias Blankertz 1807fb99b5 - Replaced cache with simpler wishbone-memory bridge 
- Redesign wishbone interconnect
- Changed wb_ddr_ctrl_wb_sc to allow easier addition of ports
2013-06-04 23:18:16 +02:00

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<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="./isim.wdb" id="1" type="auto">
<top_modules>
<top_module name="intercon_package" />
<top_module name="numeric_std" />
<top_module name="std_logic_1164" />
<top_module name="std_logic_1164_additions" />
<top_module name="textio" />
<top_module name="vcomponents" />
<top_module name="vital_primitives" />
<top_module name="vital_timing" />
<top_module name="vpkg" />
<top_module name="wb_mem_bridge_tb" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="25" />
<wvobject fp_name="/wb_mem_bridge_tb/DUT/clk_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk_i</obj_property>
<obj_property name="ObjectShortName">clk_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/DUT/rst_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rst_i</obj_property>
<obj_property name="ObjectShortName">rst_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/DUT/wbs_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">wbs_i</obj_property>
<obj_property name="ObjectShortName">wbs_i</obj_property>
<wvobject fp_name="/wb_mem_bridge_tb/DUT/wbs_i.dat_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">.dat_i</obj_property>
<obj_property name="ObjectShortName">wbs_i.dat_i</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/DUT/wbs_i.we_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">.we_i</obj_property>
<obj_property name="ObjectShortName">wbs_i.we_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/DUT/wbs_i.sel_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">.sel_i</obj_property>
<obj_property name="ObjectShortName">wbs_i.sel_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/DUT/wbs_i.adr_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">.adr_i</obj_property>
<obj_property name="ObjectShortName">wbs_i.adr_i</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/DUT/wbs_i.cyc_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">.cyc_i</obj_property>
<obj_property name="ObjectShortName">wbs_i.cyc_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/DUT/wbs_i.stb_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">.stb_i</obj_property>
<obj_property name="ObjectShortName">wbs_i.stb_i</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/DUT/wbs_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">wbs_o</obj_property>
<obj_property name="ObjectShortName">wbs_o</obj_property>
<wvobject fp_name="/wb_mem_bridge_tb/DUT/wbs_o.dat_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">.dat_o</obj_property>
<obj_property name="ObjectShortName">wbs_o.dat_o</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/DUT/wbs_o.ack_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">.ack_o</obj_property>
<obj_property name="ObjectShortName">wbs_o.ack_o</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/DUT/wb_mem_rdrq" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">wb_mem_rdrq</obj_property>
<obj_property name="ObjectShortName">wb_mem_rdrq</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/DUT/wb_mem_wrrq" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">wb_mem_wrrq</obj_property>
<obj_property name="ObjectShortName">wb_mem_wrrq</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/DUT/wb_mem_adr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">wb_mem_adr[19:0]</obj_property>
<obj_property name="ObjectShortName">wb_mem_adr[19:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/DUT/wb_mem_dat_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">wb_mem_dat_o[63:0]</obj_property>
<obj_property name="ObjectShortName">wb_mem_dat_o[63:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/DUT/wb_mem_sel" type="array" db_ref_id="1">
<obj_property name="ElementShortName">wb_mem_sel[7:0]</obj_property>
<obj_property name="ObjectShortName">wb_mem_sel[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/DUT/wb_mem_ack" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">wb_mem_ack</obj_property>
<obj_property name="ObjectShortName">wb_mem_ack</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/DUT/wb_mem_dat_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">wb_mem_dat_i[63:0]</obj_property>
<obj_property name="ObjectShortName">wb_mem_dat_i[63:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/DUT/buf_dirty" type="array" db_ref_id="1">
<obj_property name="ElementShortName">buf_dirty[63:0]</obj_property>
<obj_property name="ObjectShortName">buf_dirty[63:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/DUT/buf_valid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">buf_valid</obj_property>
<obj_property name="ObjectShortName">buf_valid</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/DUT/buf_tag" type="array" db_ref_id="1">
<obj_property name="ElementShortName">buf_tag[25:6]</obj_property>
<obj_property name="ObjectShortName">buf_tag[25:6]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/DUT/buf_adr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">buf_adr[2:0]</obj_property>
<obj_property name="ObjectShortName">buf_adr[2:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/DUT/buf_bwe" type="array" db_ref_id="1">
<obj_property name="ElementShortName">buf_bwe[7:0]</obj_property>
<obj_property name="ObjectShortName">buf_bwe[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/DUT/buf_hit" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">buf_hit</obj_property>
<obj_property name="ObjectShortName">buf_hit</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/DUT/buf_dat_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">buf_dat_o[63:0]</obj_property>
<obj_property name="ObjectShortName">buf_dat_o[63:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/DUT/buf_dat_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">buf_dat_i[63:0]</obj_property>
<obj_property name="ObjectShortName">buf_dat_i[63:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/DUT/wb_in_cyc" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">wb_in_cyc</obj_property>
<obj_property name="ObjectShortName">wb_in_cyc</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/DUT/write_flush" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">write_flush</obj_property>
<obj_property name="ObjectShortName">write_flush</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/DUT/read_fill" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">read_fill</obj_property>
<obj_property name="ObjectShortName">read_fill</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/DUT/buf_wbwr" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">buf_wbwr</obj_property>
<obj_property name="ObjectShortName">buf_wbwr</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/DUT/ctr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ctr[2:0]</obj_property>
<obj_property name="ObjectShortName">ctr[2:0]</obj_property>
</wvobject>
<wvobject fp_name="group25" type="group">
<obj_property name="label">mem_ctrl</obj_property>
<obj_property name="DisplayName">label</obj_property>
<wvobject fp_name="/wb_mem_bridge_tb/mem_ctrl_inst/clk_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk_i</obj_property>
<obj_property name="ObjectShortName">clk_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/mem_ctrl_inst/rst_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rst_i</obj_property>
<obj_property name="ObjectShortName">rst_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/mem_ctrl_inst/vga_mem_rdrq" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">vga_mem_rdrq</obj_property>
<obj_property name="ObjectShortName">vga_mem_rdrq</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/mem_ctrl_inst/vga_mem_adr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">vga_mem_adr[19:0]</obj_property>
<obj_property name="ObjectShortName">vga_mem_adr[19:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/mem_ctrl_inst/vga_mem_ack" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">vga_mem_ack</obj_property>
<obj_property name="ObjectShortName">vga_mem_ack</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/mem_ctrl_inst/vga_mem_dat_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">vga_mem_dat_i[63:0]</obj_property>
<obj_property name="ObjectShortName">vga_mem_dat_i[63:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/mem_ctrl_inst/wb_mem_rdrq" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">wb_mem_rdrq</obj_property>
<obj_property name="ObjectShortName">wb_mem_rdrq</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/mem_ctrl_inst/wb_mem_wrrq" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">wb_mem_wrrq</obj_property>
<obj_property name="ObjectShortName">wb_mem_wrrq</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/mem_ctrl_inst/wb_mem_adr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">wb_mem_adr[19:0]</obj_property>
<obj_property name="ObjectShortName">wb_mem_adr[19:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/mem_ctrl_inst/wb_mem_dat_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">wb_mem_dat_o[63:0]</obj_property>
<obj_property name="ObjectShortName">wb_mem_dat_o[63:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/mem_ctrl_inst/wb_mem_sel" type="array" db_ref_id="1">
<obj_property name="ElementShortName">wb_mem_sel[7:0]</obj_property>
<obj_property name="ObjectShortName">wb_mem_sel[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/mem_ctrl_inst/wb_mem_ack" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">wb_mem_ack</obj_property>
<obj_property name="ObjectShortName">wb_mem_ack</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/mem_ctrl_inst/wb_mem_dat_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">wb_mem_dat_i[63:0]</obj_property>
<obj_property name="ObjectShortName">wb_mem_dat_i[63:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/mem_ctrl_inst/ddr_din" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr_din[63:0]</obj_property>
<obj_property name="ObjectShortName">ddr_din[63:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/mem_ctrl_inst/ddr_dout" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr_dout[63:0]</obj_property>
<obj_property name="ObjectShortName">ddr_dout[63:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/mem_ctrl_inst/ddr_adr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr_adr[22:0]</obj_property>
<obj_property name="ObjectShortName">ddr_adr[22:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/mem_ctrl_inst/ddr_we" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr_we</obj_property>
<obj_property name="ObjectShortName">ddr_we</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/mem_ctrl_inst/ddr_be" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr_be[7:0]</obj_property>
<obj_property name="ObjectShortName">ddr_be[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/mem_ctrl_inst/fifo_to_ddr_write" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_to_ddr_write</obj_property>
<obj_property name="ObjectShortName">fifo_to_ddr_write</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/mem_ctrl_inst/fifo_from_ddr_read" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_from_ddr_read</obj_property>
<obj_property name="ObjectShortName">fifo_from_ddr_read</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/mem_ctrl_inst/fifo_to_ddr_full" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_to_ddr_full</obj_property>
<obj_property name="ObjectShortName">fifo_to_ddr_full</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/mem_ctrl_inst/fifo_from_ddr_empty" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_from_ddr_empty</obj_property>
<obj_property name="ObjectShortName">fifo_from_ddr_empty</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/mem_ctrl_inst/p_rdrq" type="array" db_ref_id="1">
<obj_property name="ElementShortName">p_rdrq[1:0]</obj_property>
<obj_property name="ObjectShortName">p_rdrq[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/mem_ctrl_inst/p_wrrq" type="array" db_ref_id="1">
<obj_property name="ElementShortName">p_wrrq[1:0]</obj_property>
<obj_property name="ObjectShortName">p_wrrq[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/mem_ctrl_inst/p_ack" type="array" db_ref_id="1">
<obj_property name="ElementShortName">p_ack[1:0]</obj_property>
<obj_property name="ObjectShortName">p_ack[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/mem_ctrl_inst/p_adr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">p_adr[1:0]</obj_property>
<obj_property name="ObjectShortName">p_adr[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/mem_ctrl_inst/p_dat_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">p_dat_o[1:0]</obj_property>
<obj_property name="ObjectShortName">p_dat_o[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/mem_ctrl_inst/p_dat_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">p_dat_i[1:0]</obj_property>
<obj_property name="ObjectShortName">p_dat_i[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/mem_ctrl_inst/p_sel" type="array" db_ref_id="1">
<obj_property name="ElementShortName">p_sel[1:0]</obj_property>
<obj_property name="ObjectShortName">p_sel[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/mem_ctrl_inst/rdrq_reg" type="array" db_ref_id="1">
<obj_property name="ElementShortName">rdrq_reg[1:0]</obj_property>
<obj_property name="ObjectShortName">rdrq_reg[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/mem_ctrl_inst/wrrq_reg" type="array" db_ref_id="1">
<obj_property name="ElementShortName">wrrq_reg[1:0]</obj_property>
<obj_property name="ObjectShortName">wrrq_reg[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/mem_ctrl_inst/adr_reg" type="array" db_ref_id="1">
<obj_property name="ElementShortName">adr_reg[1:0]</obj_property>
<obj_property name="ObjectShortName">adr_reg[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/mem_ctrl_inst/rq_complete" type="array" db_ref_id="1">
<obj_property name="ElementShortName">rq_complete[1:0]</obj_property>
<obj_property name="ObjectShortName">rq_complete[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/mem_ctrl_inst/dout_data_valid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">dout_data_valid</obj_property>
<obj_property name="ObjectShortName">dout_data_valid</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/mem_ctrl_inst/bus_owner" type="other" db_ref_id="1">
<obj_property name="ElementShortName">bus_owner</obj_property>
<obj_property name="ObjectShortName">bus_owner</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/mem_ctrl_inst/bus_owner_reg" type="other" db_ref_id="1">
<obj_property name="ElementShortName">bus_owner_reg</obj_property>
<obj_property name="ObjectShortName">bus_owner_reg</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/mem_ctrl_inst/out_ctr" type="other" db_ref_id="1">
<obj_property name="ElementShortName">out_ctr</obj_property>
<obj_property name="ObjectShortName">out_ctr</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/mem_ctrl_inst/in_ctr" type="other" db_ref_id="1">
<obj_property name="ElementShortName">in_ctr</obj_property>
<obj_property name="ObjectShortName">in_ctr</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/mem_ctrl_inst/out_complete" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">out_complete</obj_property>
<obj_property name="ObjectShortName">out_complete</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/mem_ctrl_inst/in_complete" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">in_complete</obj_property>
<obj_property name="ObjectShortName">in_complete</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/mem_ctrl_inst/in_read" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">in_read</obj_property>
<obj_property name="ObjectShortName">in_read</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/mem_ctrl_inst/in_write" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">in_write</obj_property>
<obj_property name="ObjectShortName">in_write</obj_property>
</wvobject>
<wvobject fp_name="/wb_mem_bridge_tb/mem_ctrl_inst/fifo_to_ddr_full_last" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_to_ddr_full_last</obj_property>
<obj_property name="ObjectShortName">fifo_to_ddr_full_last</obj_property>
</wvobject>
</wvobject>
</wave_config>
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