Matthias Blankertz
0bc4815926
- Debugged UART - Firmware support for SPI, UART - Work on SD/MMC support in firmware - Debugged mblite core/WB interface
98 lines
2.6 KiB
VHDL
98 lines
2.6 KiB
VHDL
-------------------------------------------------------------------------------
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-- Title : Wrapper to integrate mblite core
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-- Project :
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-------------------------------------------------------------------------------
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-- File : mblite_wrapper.vhd
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-- Author : Matthias Blankertz <matthias@blankertz.org>
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-- Company :
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-- Created : 2013-06-02
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-- Last update: 2013-06-07
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-- Platform :
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-- Standard : VHDL'93/02
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-------------------------------------------------------------------------------
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-- Description:
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-------------------------------------------------------------------------------
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-- Copyright (c) 2013
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Date Version Author Description
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-- 2013-06-02 1.0 matthias Created
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-------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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use work.intercon_package.all;
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library mblite;
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use mblite.core_Pkg.all;
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entity mblite_wrapper is
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port (
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clk_i : in std_logic;
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rst_i : in std_logic;
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wbm_i : in cpu_wbm_i_type;
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wbm_o : out cpu_wbm_o_type;
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rom_wbs_i : in mblite_rom_wbs_i_type;
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rom_wbs_o : out mblite_rom_wbs_o_type
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);
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end mblite_wrapper;
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architecture Mixed of mblite_wrapper is
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signal mb_imem_o : imem_out_type;
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signal mb_imem_i : imem_in_type;
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signal mb_wb_o : wb_mst_out_type;
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signal mb_wb_i : wb_mst_in_type;
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begin
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mb_wb_i.clk_i <= clk_i;
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mb_wb_i.rst_i <= rst_i;
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mblite_inst : entity mblite.core_wb
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port map (
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imem_o => mb_imem_o,
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imem_i => mb_imem_i,
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wb_o => mb_wb_o,
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wb_i => mb_wb_i
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);
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mblite_rom_inst : entity work.mblite_rom
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port map (
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clka => clk_i,
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ena => mb_imem_o.ena_o,
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addra => mb_imem_o.adr_o(13 downto 2),
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douta => mb_imem_i.dat_i,
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wbs_i => rom_wbs_i,
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wbs_o => rom_wbs_o
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);
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wb_reg : process(clk_i)
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begin
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if rising_edge(clk_i) then
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wbm_o.adr_o <= mb_wb_o.adr_o;
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wbm_o.we_o <= mb_wb_o.we_o;
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wbm_o.sel_o <= mb_wb_o.sel_o;
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end if;
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end process wb_reg;
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wbm_o.dat_o <= mb_wb_o.dat_o;
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wbm_o.stb_o <= mb_wb_o.stb_o;
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wbm_o.cyc_o <= mb_wb_o.cyc_o;
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mb_wb_i.dat_i <= wbm_i.dat_i;
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mb_wb_i.ack_i <= wbm_i.ack_i;
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mb_wb_i.int_i <= '0';
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end Mixed;
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