2d_display_engine-new/src/toplevel.vhd

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-- Company: 
-- Engineer: 
-- 
-- Create Date: 11/02/2012 03:48:47 PM
-- Design Name: 
-- Module Name: toplevel - Mixed
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

use work.intercon_package.all;

entity toplevel is
  generic (
    dontcare : std_logic := '-'
  );
  Port (
    -- global signals
    clkin_50MHz : IN std_ulogic;
    clkin_133MHz : IN std_ulogic;
    reset : IN std_ulogic;
    
    -- VGA port
    vga_r, vga_g, vga_b : OUT std_logic_vector(3 downto 0);
    vga_vsync, vga_hsync : OUT std_logic;
    
    -- spi flash
    dataflash_mosi, dataflash_sck, dataflash_ss, dataflash_wp, dataflash_rst : OUT std_ulogic;
    dataflash_miso : IN std_ulogic;
    
    -- LEDs
    led : OUT std_logic_vector(7 downto 0);
    
    -- DDR2 SDRAM
    ddr2_dq                : inout std_logic_vector(15 downto 0);
    ddr2_a                 : out   std_logic_vector(12 downto 0);
    ddr2_ba                : out   std_logic_vector(1 downto 0);
    ddr2_cke               : out   std_logic;
    ddr2_cs_n              : out   std_logic;
    ddr2_ras_n             : out   std_logic;
    ddr2_cas_n             : out   std_logic;
    ddr2_we_n              : out   std_logic;
    ddr2_odt               : out   std_logic;
    ddr2_dm                : out   std_logic_vector(1 downto 0);
    rst_dqs_div_in         : in    std_logic;
    rst_dqs_div_out        : out   std_logic;
    ddr2_dqs               : inout std_logic_vector(1 downto 0);
    ddr2_dqs_n             : inout std_logic_vector(1 downto 0);
    ddr2_ck                : out   std_logic_vector(0 downto 0);
    ddr2_ck_n              : out   std_logic_vector(0 downto 0);

    -- RS232
    rs232_txd : out std_logic;
    rs232_rxd : in std_logic;

    sd_miso : in std_logic;
    sd_mosi : out std_logic;
    sd_cs : out std_logic;
    sd_sck : out std_logic
    );
end toplevel;

architecture Mixed of toplevel is
  signal sysClk, sysRst, vgaClk : std_logic;

  signal cpu_wbm_o        : cpu_wbm_o_type;
  signal cpu_wbm_i        : cpu_wbm_i_type;
  signal ram_wbs_o        : ram_wbs_o_type;
  signal ram_wbs_i        : ram_wbs_i_type;
  signal rom_wbs_o        : mblite_rom_wbs_o_type;
  signal rom_wbs_i        : mblite_rom_wbs_i_type;
  signal pio_led_wbs_i : pio_led_wbs_i_type;
  signal pio_led_wbs_o : pio_led_wbs_o_type;
  signal uart_wbs_i : uart_wbs_i_type;
  signal uart_wbs_o : uart_wbs_o_type;
  signal spi_sd_wbs_i : spi_wbs_i_type;
  signal spi_sd_wbs_o : spi_wbs_o_type;
  signal mem_bridge_wbs_o : mem_bridge_wbs_o_type;
  signal mem_bridge_wbs_i : mem_bridge_wbs_i_type;
  
  signal vga_mem_rdrq  : std_logic;
  signal vga_mem_adr   : std_logic_vector(19 downto 0);
  signal vga_mem_ack   : std_logic;
  signal vga_mem_dat_i : std_logic_vector(63 downto 0);

  signal wb_mem_rdrq   : std_logic;
  signal wb_mem_wrrq   : std_logic;
  signal wb_mem_adr    : std_logic_vector(19 downto 0);
  signal wb_mem_dat_o  : std_logic_vector(63 downto 0);
  signal wb_mem_sel    : std_logic_vector(7 downto 0);
  signal wb_mem_ack    : std_logic;
  signal wb_mem_dat_i  : std_logic_vector(63 downto 0);
  
  signal reset_int : std_logic;

  signal fb_flip, fb_flip_ack, fb_in_use : std_logic;

  signal pio_led_out : std_logic_vector(7 downto 0);
begin
reset_int <= reset;
  
sys_clk_rst : entity work.clk_reset
  port map (
    clkIn50 => clkin_50MHz,
    rstIn => reset_int,
    sysClk50 => sysClk,
    sysClk25 => vgaClk,
    sysRst50 => sysRst
  );

ddr_ctrl0 : entity work.wb_ddr_ctrl
  generic map (
    dontcare => dontcare
  )
  port map (
    -- DDR2 control
    ddr2_clock => clkin_133MHz,
    ddr2_reset => reset_int,
    
    -- DDR2 SDRAM
    ddr2_dq => ddr2_dq,
    ddr2_a => ddr2_a,
    ddr2_ba => ddr2_ba,
    ddr2_cke => ddr2_cke,
    ddr2_cs_n => ddr2_cs_n,
    ddr2_ras_n => ddr2_ras_n,
    ddr2_cas_n => ddr2_cas_n,
    ddr2_we_n => ddr2_we_n,
    ddr2_odt => ddr2_odt,
    ddr2_dm => ddr2_dm,
    rst_dqs_div_in => rst_dqs_div_in,
    rst_dqs_div_out => rst_dqs_div_out,
    ddr2_dqs => ddr2_dqs,
    ddr2_dqs_n => ddr2_dqs_n,
    ddr2_ck => ddr2_ck,
    ddr2_ck_n => ddr2_ck_n,

    clk_i => sysClk,
    rst_i => sysRst,

    vga_mem_rdrq => vga_mem_rdrq,
    vga_mem_adr => vga_mem_adr,
    vga_mem_ack => vga_mem_ack,
    vga_mem_dat_i => vga_mem_dat_i,

    wb_mem_rdrq => wb_mem_rdrq,
    wb_mem_wrrq => wb_mem_wrrq,
    wb_mem_adr => wb_mem_adr,
    wb_mem_dat_o => wb_mem_dat_o,
    wb_mem_sel => wb_mem_sel,
    wb_mem_ack => wb_mem_ack,
    wb_mem_dat_i => wb_mem_dat_i
    );

vga_1: entity work.vga
  generic map (
    h_total_pixels    => 800,
    h_front_porch     => 16,
    h_back_porch      => 48,
    h_sync_pulse      => 96,
    h_sync_pos        => false,
    h_active_pixels   => 640,
    v_total_lines     => 525,
    v_front_porch     => 10,
    v_back_porch      => 33,
    v_sync_pulse      => 2,
    v_sync_pos        => false,
    v_active_lines    => 480,
    framebuffer0_base => 0,
    burst_length      => 8,
    burst_length_ln2  => 3,
    addr_width        => 24,
    dontcare          => dontcare)
  port map (
    clk_in    => sysClk,
    clk_vga   => vgaClk,
    rst       => sysRst,
    
    mem_rdrq  => vga_mem_rdrq,
    mem_adr   => vga_mem_adr,
    mem_ack   => vga_mem_ack,
    mem_dat_i => vga_mem_dat_i,
    
    red       => vga_r,
    green     => vga_g,
    blue      => vga_b,
    vsync     => vga_vsync,
    hsync     => vga_hsync,

    fb_in_use => fb_in_use,
    fb_flip   => fb_flip,
    fb_flip_ack => fb_flip_ack);

wb_ram_inst: entity work.wb_ram
  port map (
    clk_i => sysClk,
    wbs_i => ram_wbs_i,
    wbs_o => ram_wbs_o);

pio_led: entity work.pio
  port map (
    clk_i => sysClk,
    rst_i => sysRst,

    dat_i => pio_led_wbs_i.dat_i,
    we_i => pio_led_wbs_i.we_i,
    sel_i => pio_led_wbs_i.sel_i,
    cyc_i => pio_led_wbs_i.cyc_i,
    stb_i => pio_led_wbs_i.stb_i,

    dat_o => pio_led_wbs_o.dat_o,
    ack_o => pio_led_wbs_o.ack_o,

    pio_out => pio_led_out
  );

uart_inst: entity work.uart_wbc
  generic map (
    dontcare => dontcare
  )
  port map (
    CLK_I => sysClk,
    RST_I => sysRst,

    DAT_O => uart_wbs_o.dat_o(7 downto 0),
    DAT_I => uart_wbs_i.dat_i(7 downto 0),
    ACK_O => uart_wbs_o.ack_o,
    STB_I => uart_wbs_i.stb_i,
    WE_I => uart_wbs_i.we_i,
    ADR_I => uart_wbs_i.adr_i,

    SERIALIN => rs232_rxd,
    SERIALOUT => rs232_txd
  );

spi_sd_inst : entity work.spi
  port map (
    clk_i => sysClk,
    rst_i => sysRst,

    wbs_i => spi_sd_wbs_i,
    wbs_o => spi_sd_wbs_o,

    miso => sd_miso,
    mosi => sd_mosi,
    ss => sd_cs,
    sclk => sd_sck
  );

mem_bridge_inst : entity work.wb_mem_bridge
  port map (
    clk_i => sysClk,
    rst_i => sysRst,

    wbs_i => mem_bridge_wbs_i,
    wbs_o => mem_bridge_wbs_o,

    wb_mem_rdrq => wb_mem_rdrq,
    wb_mem_wrrq => wb_mem_wrrq,
    wb_mem_adr => wb_mem_adr,
    wb_mem_dat_o => wb_mem_dat_o,
    wb_mem_sel => wb_mem_sel,
    wb_mem_ack => wb_mem_ack,
    wb_mem_dat_i => wb_mem_dat_i
  );

cpu_inst : entity work.mblite_wrapper
  port map (
    clk_i => sysClk,
    rst_i => sysRst,

    wbm_i => cpu_wbm_i,
    wbm_o => cpu_wbm_o,

    rom_wbs_i => rom_wbs_i,
    rom_wbs_o => rom_wbs_o
  );

fb_flip <= '0';

intercon_1: entity work.interconnect
  port map (
    cpu_wbm_i        => cpu_wbm_i,
    cpu_wbm_o        => cpu_wbm_o,
    mblite_rom_wbs_i => rom_wbs_i,
    mblite_rom_wbs_o => rom_wbs_o,
    ram_wbs_i        => ram_wbs_i,
    ram_wbs_o        => ram_wbs_o,
    mem_bridge_wbs_i => mem_bridge_wbs_i,
    mem_bridge_wbs_o => mem_bridge_wbs_o,
    pio_led_wbs_o => pio_led_wbs_o,
    pio_led_wbs_i => pio_led_wbs_i,
    uart_wbs_o => uart_wbs_o,
    uart_wbs_i => uart_wbs_i,
    spi_sd_wbs_o => spi_sd_wbs_o,
    spi_sd_wbs_i => spi_sd_wbs_i,
    clk              => sysClk,
    reset            => sysRst);

dataflash_mosi <= 'Z';
dataflash_sck <= 'Z';
dataflash_ss <= 'Z';
dataflash_wp <= 'Z';
dataflash_rst <= 'Z';

led <= pio_led_out;

end Mixed;