Matthias Blankertz
321ea30ed8
- Added ZPU processor - Optimized wb_ddr_ctrl_wb_dc* to meet timing - Added cache frontend
148 lines
5.2 KiB
Makefile
Executable File
148 lines
5.2 KiB
Makefile
Executable File
COMMON_INFILES=ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_parameters_0.vhd \
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ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_infrastructure_top.vhd \
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ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_clk_dcm.vhd \
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ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_cal_top.vhd \
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ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_cal_ctl.vhd \
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ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_tap_dly.vhd \
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ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_top_0.vhd \
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ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_controller_0.vhd \
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ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_data_path_0.vhd \
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ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_data_read_0.vhd \
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ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_rd_gray_cntr.vhd \
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ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_ram8d_0.vhd \
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ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_ram8d_1.vhd \
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ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_data_read_controller_0.vhd \
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ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_dqs_delay_0.vhd \
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ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_fifo_0_wr_en_0.vhd \
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ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_fifo_1_wr_en_0.vhd \
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ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_wr_gray_cntr.vhd \
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ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_data_write_0.vhd \
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ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_infrastructure.vhd \
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ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_iobs_0.vhd \
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ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_infrastructure_iobs_0.vhd \
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ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_controller_iobs_0.vhd \
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ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_data_path_iobs_0.vhd \
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ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_s3_dm_iob.vhd \
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ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_s3_dqs_iob.vhd \
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ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_s3_dq_iob.vhd \
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src/wb_interconnect.vhd \
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src/clk_reset.vhd src/wb_ddr_ctrl.vhd src/wb_ddr_ctrl_ddrwrap.vhd \
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src/wb_ddr_ctrl_wb.vhd src/wb_ddr_ctrl_wb_dc_fsm.vhd src/wb_ddr_ctrl_wb_dc.vhd \
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src/wb_ddr_ctrl_wb_sc_fe_fsm.vhd src/wb_ddr_ctrl_wb_sc_fe.vhd \
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src/wb_ddr_ctrl_wb_sc.vhd src/vga_syncgen.vhd src/vga_pixelgen.vhd \
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src/vga_pixelreader.vhd src/vga.vhd \
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zy2000/zpu_config.vhd zy2000/zpupkg.vhd zy2000/zpu_core.vhd zy2000/zpu_wb_bridge.vhd \
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zy2000/zpu_system.vhd \
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src/toplevel.vhd
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SYN_INFILES=
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PSMFILES=
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CORES=wb_ddr_ctrl_wb_from_ddr wb_ddr_ctrl_wb_to_ddr vga_pixeldata_fifo
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PRJNAME=2d_display_engine
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NGCFILE=$(PRJNAME).ngc
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XSTFILE=$(PRJNAME).xst
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XCF=constr/$(PRJNAME).xcf
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UCF=constr/$(PRJNAME).ucf constr/vhdl_bl4.ucf
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PCFFILE=$(PRJNAME).pcf
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NGDFILE=$(PRJNAME).ngd
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NCDFILE=$(PRJNAME).ncd
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NCDFILE_R=$(PRJNAME)_routed.ncd
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BITFILE=$(PRJNAME).bit
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TWRFILE=$(PRJNAME).twr
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PRJFILE=$(PRJNAME).prj
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PART=xc3s700an-fgg484-4
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NGDOPTS=-p $(PART) -aul -aut $(addprefix -uc ,$(UCF)) -sd coregen/
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MAPOPTS=-p $(PART) -cm balanced -timing -ol high -logic_opt on
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PAROPTS=-ol high
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BITGENOPTS=
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TRACEOPTS=-v -u 100
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SIM_INFILES=src/sim_bmppack.vhd
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SIM_INFILES_VLOG=ddr2_sdram/vhdl_bl4/example_design/sim/ddr2_model.v
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GHDLOPTS=--workdir=ghdl -Pghdl --ieee=synopsys -fexplicit
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VLOGCOMPOPTS=-d x512Mb -d sg5E -d x16 -d MAX_MEM
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SYNALLFILES=$(COMMON_INFILES) $(SYN_INFILES)
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SIMALLFILES=$(SIM_INFILES) $(COMMON_INFILES)
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SIMALLFILESXDB=isim/ieee_proposed/std_logic_1164_additions.vdb \
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$(addprefix isim/work/,$(notdir $(SIMALLFILES:.vhd=.vdb))) \
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$(addprefix isim/work/,$(notdir $(SIM_INFILES_VLOG:.v=.sdb)))
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CORESVDB=$(addprefix isim/work/,$(addsuffix .vdb,$(CORES)))
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XILPATH=
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XST=$(XILPATH)xst
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NGDBUILD=$(XILPATH)ngdbuild
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MAP=$(XILPATH)map
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PAR=$(XILPATH)par
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BITGEN=$(XILPATH)bitgen
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TRCE=$(XILPATH)trce
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VHPCOMP=$(XILPATH)vhpcomp
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VLOGCOMP=$(XILPATH)vlogcomp
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FUSE=$(XILPATH)fuse
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.SECONDARY:
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all: $(BITFILE)
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synth: $(NGCFILE)
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impl: $(NCDFILE_R)
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timing: $(TWRFILE)
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#%.vhd: %.psm
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# ../tools/picoasm/picoasm -t ../tools/picoasm/ROM_form.vhd -i $<
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src/wb_interconnect.vhd: src/wishbone.defines
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cd src && ../tools/wishbone.pl -nogui wishbone.defines
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$(PRJFILE): Makefile
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rm -f $(PRJFILE); for i in $(SYNALLFILES); do echo "vhdl work" $$i >> $(PRJFILE); done
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$(NGCFILE): $(SYNALLFILES) $(PRJFILE) $(XSTFILE) $(XCF)
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$(XST) -ifn $(XSTFILE)
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$(NGDFILE): $(NGCFILE) $(UCF)
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$(NGDBUILD) $(NGDOPTS) $(NGCFILE) $(NGDFILE)
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$(PCFFILE) $(NCDFILE) : $(NGDFILE)
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$(MAP) $(MAPOPTS) -o $(NCDFILE) $(NGDFILE) $(PCFFILE)
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$(NCDFILE_R): $(PCFFILE) $(NCDFILE)
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$(PAR) -w $(PAROPTS) $(NCDFILE) $(NCDFILE_R) $(PCFFILE)
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$(BITFILE): $(NCDFILE_R) $(PCFFILE)
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$(BITGEN) -w $(BITGENOPTS) $(NCDFILE_R) $(BITFILE) $(PCFFILE)
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$(TWRFILE): $(NCDFILE_R) $(PCFFILE)
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$(TRCE) $(TRACEOPTS) -o $(TWRFILE) $(NCDFILE_R) $(PCFFILE)
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isim/ieee_proposed/std_logic_1164_additions.vdb: tools/std_logic_1164_additions.vhdl
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$(VHPCOMP) --work ieee_proposed $<
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isim/work/%.vdb: src/%.vhd
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$(VHPCOMP) $<
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isim/work/%.vdb: zy2000/%.vhd
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$(VHPCOMP) $<
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isim/work/%.vdb: ddr2_sdram/vhdl_bl4/example_design/rtl/%.vhd
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$(VHPCOMP) $<
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isim/work/%.sdb: ddr2_sdram/vhdl_bl4/example_design/sim/%.v
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$(VLOGCOMP) $< $(VLOGCOMPOPTS)
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isim/work/%.vdb: tb/%.vhd
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$(VHPCOMP) $<
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isim/work/%.vdb: coregen/%.vhd
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$(VHPCOMP) $<
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%.exe: isim/work/%.vdb $(SIMALLFILESXDB) $(CORESVDB)
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$(FUSE) work.$(@:.exe=) -o $@
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clean:
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rm -f $(NGCFILE) $(PCFFILE) $(NGDFILE) $(NCDFILE) $(NCDFILE_R) $(BITFILE) $(SIMALLFILESXDB) $(CORESVDB)
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.PSEUDO=all synth impl timing clean
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