Matthias Blankertz
90631f89bd
- Started changing DDR controller interface to 64 bit bus width - Debugging
87 lines
2.1 KiB
VHDL
87 lines
2.1 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 11/06/2012 03:04:35 PM
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-- Design Name:
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-- Module Name: vga_pixelgen - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description: VGA pixel generator
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity vga_pixelgen is
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port (
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clk : in std_logic;
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-- from syncgen
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vid_en : in std_logic;
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-- from fifo
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pixeldata : in std_logic_vector(15 downto 0);
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fifo_read : out std_logic;
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fifo_empty : in std_logic;
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-- to vga
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red : out std_logic_vector(3 downto 0);
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green : out std_logic_vector(3 downto 0);
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blue : out std_logic_vector(3 downto 0)
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);
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end vga_pixelgen;
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architecture Behavioral of vga_pixelgen is
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signal empty_dly : std_logic := '0';
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signal data_valid : std_logic := '0';
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begin
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fifo_read <= vid_en;
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pixelgen : process(clk)
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-- synthesis translate_off
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variable firstframe : boolean := true;
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variable underflowing : boolean := false;
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-- synthesis translate_on
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begin
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if rising_edge(clk) then
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data_valid <= not fifo_empty and vid_en;
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empty_dly <= fifo_empty;
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if data_valid = '1' then
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assert empty_dly = '0' report "Video output FIFO underflow" severity warning;
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end if;
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if data_valid = '1' and empty_dly = '0' then
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red <= pixeldata(11 downto 8);
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green <= pixeldata(7 downto 4);
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blue <= pixeldata(3 downto 0);
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else
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red <= (others => '0');
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green <= (others => '0');
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blue <= (others => '0');
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end if;
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end if;
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end process pixelgen;
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end Behavioral;
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