2d_display_engine-new/src/wb_ddr_ctrl_wb_sc.vhd

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-- Company: 
-- Engineer: 
-- 
-- Create Date: 11/06/2012 03:04:35 PM
-- Design Name: 
-- Module Name: wb_ddr_ctrl_wb_sc - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: Memory controller - system clock domain
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

use work.intercon_package.all;

entity wb_ddr_ctrl_wb_sc is
  generic (
    burst_length : integer := 16;
    dontcare : std_logic := '-'
  );
  port (
    -- Wishbone slave
    clk_i : in std_ulogic;
    rst_i : in std_ulogic;
    wbs_i : in  sdram_ctrl_wbs_i_type;
    wbs_o : out sdram_ctrl_wbs_o_type;
    wbs_cc_i  : in  sdram_ctrl_cc_wbs_i_type;
    wbs_cc_o  : out sdram_ctrl_cc_wbs_o_type;
    
     -- Direct memctrl access for VGA
    vga_mem_rdrq  : in  std_logic;
    vga_mem_adr   : in  std_logic_vector(19 downto 0);
    vga_mem_ack   : out std_logic;
    vga_mem_dat_i : out std_logic_vector(63 downto 0);
    
    -- To/from ddr clock domain
    ddr_din : out std_logic_vector(63 downto 0);
    ddr_dout : in std_logic_vector(63 downto 0);
    ddr_adr : out std_logic_vector(22 downto 0);
    ddr_we : out std_ulogic;
    ddr_be : out std_logic_vector(7 downto 0);
    
    fifo_to_ddr_write : out std_ulogic;
    fifo_from_ddr_read : out std_ulogic;
    fifo_to_ddr_full : in std_ulogic;
    fifo_from_ddr_empty : in std_ulogic 
  );
end wb_ddr_ctrl_wb_sc;

architecture Behavioral of wb_ddr_ctrl_wb_sc is
  component wb_ddr_ctrl_wb_sc_fe
    generic (
      line_size     : integer;
      lines         : integer;
      assoc         : integer;
      line_size_ln2 : integer;
      lines_ln2     : integer;
      assoc_ln2     : integer;
      addr_width    : integer);
    port (
      clk_i     : in  std_logic;
      rst_i     : in  std_logic;
      wbs_i     : in  sdram_ctrl_wbs_i_type;
      wbs_o     : out sdram_ctrl_wbs_o_type;
      wbs_cc_i  : in  sdram_ctrl_cc_wbs_i_type;
      wbs_cc_o  : out sdram_ctrl_cc_wbs_o_type;
      mem_adr   : out std_logic_vector(addr_width-line_size_ln2-1 downto 0);
      mem_rdrq  : out std_logic;
      mem_wrrq  : out std_logic;
      mem_dat_o : out std_logic_vector(31 downto 0);
      mem_ack   : in  std_logic;
      mem_dat_i : in  std_logic_vector(31 downto 0));
  end component;

  type states is (S_IDLE);
  signal state : states := S_IDLE;
  
  signal cfe_mem_adr   : std_logic_vector(addr_width-line_size_ln2-1 downto 0);
  signal cfe_mem_rdrq  : std_logic;
  signal cfe_mem_wrrq  : std_logic;
  signal cfe_mem_dat_o : std_logic_vector(63 downto 0);
  signal cfe_mem_ack   : std_logic;
  signal cfe_mem_dat_i : std_logic_vector(63 downto 0));

  signal vga_active, cfe_active, burst_ctr_inc, burst_ctr_rst : std_logic := '1';
  signal in_ctr, out_ctr : unsigned(2 downto 0) := to_unsigned(0, 3);
  signal in_complete, out_complete, rq_complete : std_logic := '1';
begin
  wb_ddr_ctrl_wb_sc_fe_1: wb_ddr_ctrl_wb_sc_fe
    port map (
      clk_i     => clk_i,
      rst_i     => rst_i,
      wbs_i     => wbs_i,
      wbs_o     => wbs_o,
      wbs_cc_i  => wbs_cc_i,
      wbs_cc_o  => wbs_cc_o,
      mem_adr   => cfe_mem_adr,
      mem_rdrq  => cfe_mem_rdrq,
      mem_wrrq  => cfe_mem_wrrq,
      mem_dat_o => cfe_mem_dat_o,
      mem_ack   => cfe_mem_ack,
      mem_dat_i => cfe_mem_dat_i);

  cfe_mem_dat_i <= ddr_din;
  vga_mem_dat_i <= ddr_din;

  ddr_adr(22 downto 3) <= vga_mem_adr when vga_active = '1' else
                          cfe_mem_adr when cfe_active = '1' else
                          (others => dontcare);
  ddr_adr(2 downto 0) <= std_logic_vector(burst_ctr);
  
  ddr_we <= '0' when vga_active = '1' else
            dontcare;

  fifo_to_ddr_write <= '1' when out_complete = '0' and fifo_to_ddr_full = '0' and
                                state /= S_IDLE else
                       '0';
  
  mem_if : process(clk_i)
  begin
    if rising_edge(clk_i) then
      fifo_to_ddr_write <= '0';
      
      case state is
        when S_IDLE =>
          if fifo_to_ddr_full = '0' then
            if vga_mem_rdrq = '1' then
              fifo_to_ddr_write <= '1';
              state <= S_VGA_RDRQ;
            elsif cfe_mem_rdrq = '1' then
            elsif cfe_mem_wrrq = '1' then
            end if;
          end if;
        when S_VGA_RDRQ_SEND =>
          if rq_complete = '1' then
            state <= S_IDLE;
          end if;
      end case;
    end if;
  end process mem_if;

  vga_active <= '1' when state = S_VGA_RDRQ else
                '0';
  cfe_active <= '1' when state = S_CFE_RDRQ or state = S_CFE_WRRQ else
                '0';

  out_ctr_in <= '1' when fifo_to_ddr_write = '1' and out_complete = '0' else
                '0';

  out_ctr_rst <= '1' when fifo_to_ddr_full = '0' and (vga_mem_rdrq = '1' or cfe_mem_rdrq = '1' or
                                                      cfe_mem_rdrq = '1') and state = S_IDLE else
                 '0';

  rq_complete <= in_complete and out_complete;
  
  out_ctr_p : process(clk_i)
  begin
    if rising_edge(clk_i) then
      if out_ctr_rst = '1' then
        out_ctr <= to_unsigned(0, 3);
      elsif out_ctr_inc = '1' then
        out_ctr <= out_ctr + 1;
      end if;
    end if;
  end process burst_ctr_p;

  out_complete_p : process(clk_i)
  begin
    if rising_edge(clk_i) then
      if out_ctr_rst = '1' then
        out_complete <= '0';
      elsif fifo_to_ddr_write = '1' and out_ctr = 7 then
        out_complete <= '1';
      end if;
    end if;
  end process out_complete_p;

  in_complete_p : process(clk_i)
  begin
    if rising_edge(clk_i) then
      if out_ctr_rst = '1' then
        
  
end Behavioral;