diff --git a/2d_display_engine.data/runs/runs.xml b/2d_display_engine.data/runs/runs.xml
index 9940b06..d885de1 100644
--- a/2d_display_engine.data/runs/runs.xml
+++ b/2d_display_engine.data/runs/runs.xml
@@ -1,6 +1,14 @@
-
+
+
+
+
+
+
+
+
+
diff --git a/2d_display_engine.data/runs/synth_1/sources.xml b/2d_display_engine.data/runs/synth_1/sources.xml
index 1630931..9bb04b2 100644
--- a/2d_display_engine.data/runs/synth_1/sources.xml
+++ b/2d_display_engine.data/runs/synth_1/sources.xml
@@ -164,6 +164,12 @@
+
+
+
+
+
+
diff --git a/2d_display_engine.data/sources_1/fileset.xml b/2d_display_engine.data/sources_1/fileset.xml
index 8d02cab..c3826b1 100755
--- a/2d_display_engine.data/sources_1/fileset.xml
+++ b/2d_display_engine.data/sources_1/fileset.xml
@@ -164,6 +164,12 @@
+
+
+
+
+
+
diff --git a/2d_display_engine.data/wt/java_command_handlers.wdf b/2d_display_engine.data/wt/java_command_handlers.wdf
index a37517e..7772c4d 100755
--- a/2d_display_engine.data/wt/java_command_handlers.wdf
+++ b/2d_display_engine.data/wt/java_command_handlers.wdf
@@ -1,6 +1,6 @@
version:1
70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464636f7265:31:00:00
-70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464737263:38:00:00
+70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464737263:39:00:00
70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636865636b666f7275706461746573:31:00:00
70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636c6f736570726f6a656374:31:00:00
70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636f726576696577:31:00:00
@@ -10,15 +10,17 @@ version:1
70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:66696c6565786974:31:00:00
70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:31:00:00
70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e66696c65:31:00:00
-70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726f6a656374:31:00:00
+70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726f6a656374:35:00:00
70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:70726f6a65637473756d6d617279:32:00:00
70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72656c6f616464657369676e:32:00:00
+70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e696d706c656d656e746174696f6e:31:00:00
70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e7265736f75726365657374696d6174696f6e:32:00:00
-70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e73796e746865736973:31:00:00
+70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e73796e746865736973:3133:00:00
70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7361766566696c6570726f787968616e646c6572:31:00:00
70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:736574746172676574756366:32:00:00
70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73686f77736f75726365:32:00:00
+70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73686f7776696577:39:00:00
70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:746f67676c65766965776e6176696761746f72:32:00:00
70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b72746c616e616c79736973:32:00:00
70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:75692e76696577732e632e652e66:31:00:00
-eof:3362552667
+eof:563318448
diff --git a/2d_display_engine.data/wt/project.wpc b/2d_display_engine.data/wt/project.wpc
index 6888ede..de67d9c 100755
--- a/2d_display_engine.data/wt/project.wpc
+++ b/2d_display_engine.data/wt/project.wpc
@@ -1,3 +1,3 @@
version:1
-6d6f64655f636f756e7465727c4755494d6f6465:2
+6d6f64655f636f756e7465727c4755494d6f6465:3
eof:
diff --git a/2d_display_engine.data/wt/webtalk_pa.xml b/2d_display_engine.data/wt/webtalk_pa.xml
index 80ac715..ee0d273 100755
--- a/2d_display_engine.data/wt/webtalk_pa.xml
+++ b/2d_display_engine.data/wt/webtalk_pa.xml
@@ -3,7 +3,7 @@
-
+
@@ -18,7 +18,7 @@ This means code written to parse this file will need to be revisited each subseq
-
-
+
@@ -28,14 +28,16 @@ This means code written to parse this file will need to be revisited each subseq
-
+
+
-
+
+
diff --git a/2d_display_engine.srcs/sources_1/new/toplevel.vhd b/2d_display_engine.srcs/sources_1/new/toplevel.vhd
index c799641..1eb56fd 100755
--- a/2d_display_engine.srcs/sources_1/new/toplevel.vhd
+++ b/2d_display_engine.srcs/sources_1/new/toplevel.vhd
@@ -72,11 +72,40 @@ entity toplevel is
end toplevel;
architecture Mixed of toplevel is
+component wb_ddr_ctrl is
+ Port (
+ -- System control
+ sys_clock : in std_ulogic;
+ sys_reset : in std_ulogic;
+
+ -- DDR2 control
+ ddr2_clock : in std_ulogic;
+ ddr2_reset : in std_ulogic;
+
+ -- DDR2 SDRAM
+ ddr2_dq : inout std_logic_vector(15 downto 0);
+ ddr2_a : out std_logic_vector(12 downto 0);
+ ddr2_ba : out std_logic_vector(1 downto 0);
+ ddr2_cke : out std_logic;
+ ddr2_cs_n : out std_logic;
+ ddr2_ras_n : out std_logic;
+ ddr2_cas_n : out std_logic;
+ ddr2_we_n : out std_logic;
+ ddr2_odt : out std_logic;
+ ddr2_dm : out std_logic_vector(1 downto 0);
+ rst_dqs_div_in : in std_logic;
+ rst_dqs_div_out : out std_logic;
+ ddr2_dqs : inout std_logic_vector(1 downto 0);
+ ddr2_dqs_n : inout std_logic_vector(1 downto 0);
+ ddr2_ck : out std_logic_vector(0 downto 0);
+ ddr2_ck_n : out std_logic_vector(0 downto 0)
+ );
+end component;
begin
ddr_crtl0 : wb_ddr_ctrl
port map (
- sys_clock => clk_50MHz,
+ sys_clock => clkin_50MHz,
sys_reset => reset,
-- DDR2 control
@@ -86,7 +115,7 @@ ddr_crtl0 : wb_ddr_ctrl
-- DDR2 SDRAM
ddr2_dq => ddr2_dq,
ddr2_a => ddr2_a,
- ddr2_ba => dr2_ba,
+ ddr2_ba => ddr2_ba,
ddr2_cke => ddr2_cke,
ddr2_cs_n => ddr2_cs_n,
ddr2_ras_n => ddr2_ras_n,
diff --git a/2d_display_engine.srcs/sources_1/new/wb_ddr_ctrl.vhd b/2d_display_engine.srcs/sources_1/new/wb_ddr_ctrl.vhd
index 7777d56..1672237 100755
--- a/2d_display_engine.srcs/sources_1/new/wb_ddr_ctrl.vhd
+++ b/2d_display_engine.srcs/sources_1/new/wb_ddr_ctrl.vhd
@@ -64,11 +64,86 @@ entity wb_ddr_ctrl is
end wb_ddr_ctrl;
architecture Behavioral of wb_ddr_ctrl is
+component wb_ddr_ctrl_ddrwrap is
+ Port (
+ -- DDR2 control
+ ddr2_clock_in : in std_ulogic;
+ ddr2_reset : in std_ulogic;
+
+ -- DDR2 ctrl to system
+ ctrl_input_data : in std_logic_vector(31 downto 0);
+ ctrl_data_mask : in std_logic_vector(3 downto 0);
+ ctrl_output_data : out std_logic_vector(31 downto 0) := (others => 'Z');
+ ctrl_data_valid : out std_logic;
+ ctrl_input_address : in std_logic_vector(((13 + 10 + 2)-1) downto 0);
+ ctrl_command_register : in std_logic_vector(2 downto 0);
+ ctrl_burst_done : in std_logic;
+ ctrl_auto_ref_req : out std_logic;
+ ctrl_cmd_ack : out std_logic;
+ ctrl_init_done : out std_logic;
+ ctrl_ar_done : out std_logic;
+
+ -- DDR2 SDRAM
+ ddr2_dq : inout std_logic_vector(15 downto 0);
+ ddr2_a : out std_logic_vector(12 downto 0);
+ ddr2_ba : out std_logic_vector(1 downto 0);
+ ddr2_cke : out std_logic;
+ ddr2_cs_n : out std_logic;
+ ddr2_ras_n : out std_logic;
+ ddr2_cas_n : out std_logic;
+ ddr2_we_n : out std_logic;
+ ddr2_odt : out std_logic;
+ ddr2_dm : out std_logic_vector(1 downto 0);
+ rst_dqs_div_in : in std_logic;
+ rst_dqs_div_out : out std_logic;
+ ddr2_dqs : inout std_logic_vector(1 downto 0);
+ ddr2_dqs_n : inout std_logic_vector(1 downto 0);
+ ddr2_ck : out std_logic_vector(0 downto 0);
+ ddr2_ck_n : out std_logic_vector(0 downto 0);
+
+ -- Clock out
+ ddr2_clk0 : out std_ulogic;
+ ddr2_clk90 : out std_ulogic
+ );
+end component;
+
+component wb_ddr_ctrl_wb is
+ Port (
+ -- Control signals
+ sys_clock : in std_ulogic;
+ ddr2_clk0 : in std_ulogic;
+ ddr2_clk90 : in std_ulogic;
+ sys_reset : in std_ulogic;
+ ddr2_reset : in std_ulogic;
+
+ -- to DDR2 controller
+ ctrl_input_data : out std_logic_vector(31 downto 0);
+ ctrl_data_mask : out std_logic_vector(3 downto 0);
+ ctrl_output_data : in std_logic_vector(31 downto 0) := (others => 'Z');
+ ctrl_data_valid : in std_logic;
+ ctrl_input_address : out std_logic_vector(((13 + 10 + 2)-1) downto 0);
+ ctrl_command_register : out std_logic_vector(2 downto 0);
+ ctrl_burst_done : out std_logic;
+ ctrl_auto_ref_req : in std_logic;
+ ctrl_cmd_ack : in std_logic;
+ ctrl_init_done : in std_logic;
+ ctrl_ar_done : in std_logic
+ );
+end component;
+
+signal ddr2_clk0, ddr2_clk90 : std_ulogic;
+signal ctrl_input_data : std_logic_vector(31 downto 0);
+signal ctrl_data_mask : std_logic_vector(3 downto 0);
+signal ctrl_output_data : std_logic_vector(31 downto 0) := (others => 'Z');
+signal ctrl_data_valid : std_logic;
+signal ctrl_input_address : std_logic_vector(((13 + 10 + 2)-1) downto 0);
+signal ctrl_command_register : std_logic_vector(2 downto 0);
+signal ctrl_burst_done, ctrl_auto_ref_req, ctrl_cmd_ack, ctrl_init_done, ctrl_ar_done : std_logic;
begin
ddr_0 : wb_ddr_ctrl_ddrwrap
port map (
- ddr2_clock => ddr2_clock,
+ ddr2_clock_in => ddr2_clock,
ddr2_reset => ddr2_reset,
ddr2_dq => ddr2_dq,
@@ -86,8 +161,44 @@ ddr_0 : wb_ddr_ctrl_ddrwrap
ddr2_dqs => ddr2_dqs,
ddr2_dqs_n => ddr2_dqs_n,
ddr2_ck => ddr2_ck,
- ddr2_ck_n => ddr2_ck_n
+ ddr2_ck_n => ddr2_ck_n,
+
+ ddr2_clk0 => ddr2_clk0,
+ ddr2_clk90 => ddr2_clk90,
+
+ ctrl_input_data => ctrl_input_data,
+ ctrl_data_mask => ctrl_data_mask,
+ ctrl_output_data => ctrl_output_data,
+ ctrl_data_valid => ctrl_data_valid,
+ ctrl_input_address => ctrl_input_address,
+ ctrl_command_register => ctrl_command_register,
+ ctrl_burst_done => ctrl_burst_done,
+ ctrl_auto_ref_req => ctrl_auto_ref_req,
+ ctrl_cmd_ack => ctrl_cmd_ack,
+ ctrl_init_done => ctrl_init_done,
+ ctrl_ar_done => ctrl_ar_done
);
+wb_0 : wb_ddr_ctrl_wb
+ port map (
+ sys_clock => sys_clock,
+ sys_reset => sys_reset,
+
+ ddr2_clk0 => ddr2_clk0,
+ ddr2_clk90 => ddr2_clk90,
+ ddr2_reset => ddr2_reset,
+
+ ctrl_input_data => ctrl_input_data,
+ ctrl_data_mask => ctrl_data_mask,
+ ctrl_output_data => ctrl_output_data,
+ ctrl_data_valid => ctrl_data_valid,
+ ctrl_input_address => ctrl_input_address,
+ ctrl_command_register => ctrl_command_register,
+ ctrl_burst_done => ctrl_burst_done,
+ ctrl_auto_ref_req => ctrl_auto_ref_req,
+ ctrl_cmd_ack => ctrl_cmd_ack,
+ ctrl_init_done => ctrl_init_done,
+ ctrl_ar_done => ctrl_ar_done
+ );
end Behavioral;
diff --git a/2d_display_engine.srcs/sources_1/new/wb_ddr_ctrl_ddrwrap.vhd b/2d_display_engine.srcs/sources_1/new/wb_ddr_ctrl_ddrwrap.vhd
index 46c8b1f..973b7a7 100755
--- a/2d_display_engine.srcs/sources_1/new/wb_ddr_ctrl_ddrwrap.vhd
+++ b/2d_display_engine.srcs/sources_1/new/wb_ddr_ctrl_ddrwrap.vhd
@@ -31,7 +31,7 @@ use IEEE.STD_LOGIC_1164.ALL;
--library UNISIM;
--use UNISIM.VComponents.all;
-use work.all;
+use work.vhdl_bl4_parameters_0.all;
entity wb_ddr_ctrl_ddrwrap is
Port (
@@ -77,6 +77,83 @@ entity wb_ddr_ctrl_ddrwrap is
end wb_ddr_ctrl_ddrwrap;
architecture Behavioral of wb_ddr_ctrl_ddrwrap is
+component vhdl_bl4_infrastructure_top is
+ port(
+ reset_in_n : in std_logic;
+ sys_clk : in std_logic;
+ sys_clkb : in std_logic;
+ sys_clk_in : in std_logic;
+ delay_sel_val1_val : out std_logic_vector(4 downto 0);
+ sys_rst_val : out std_logic;
+ sys_rst90_val : out std_logic;
+ clk_int_val : out std_logic;
+ clk90_int_val : out std_logic;
+ sys_rst180_val : out std_logic;
+ wait_200us : out std_logic;
+ -- debug signals
+ dbg_phase_cnt : out std_logic_vector(4 downto 0);
+ dbg_cnt : out std_logic_vector(5 downto 0);
+ dbg_trans_onedtct : out std_logic;
+ dbg_trans_twodtct : out std_logic;
+ dbg_enb_trans_two_dtct : out std_logic
+ );
+
+end component;
+
+component vhdl_bl4_top_0 is
+ port(
+ wait_200us : in std_logic;
+ rst_dqs_div_in : in std_logic;
+ rst_dqs_div_out : out std_logic;
+
+ user_input_data : in std_logic_vector(((2*DATA_WIDTH)-1) downto 0);
+ user_data_mask : in std_logic_vector(((DATA_MASK_WIDTH*2)-1) downto 0);
+ user_output_data : out std_logic_vector(((2*DATA_WIDTH)-1)
+ downto 0) := (others => 'Z');
+ user_data_valid : out std_logic;
+ user_input_address : in std_logic_vector(((ROW_ADDRESS +
+ COLUMN_ADDRESS + BANK_ADDRESS)-1) downto 0);
+ user_command_register : in std_logic_vector(2 downto 0);
+ burst_done : in std_logic;
+ auto_ref_req : out std_logic;
+ user_cmd_ack : out std_logic;
+ init_done : out std_logic;
+ ar_done : out std_logic;
+ ddr2_dqs : inout std_logic_vector((DATA_STROBE_WIDTH -1) downto 0);
+ ddr2_dqs_n : inout std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
+
+ ddr2_dq : inout std_logic_vector((DATA_WIDTH-1) downto 0)
+ := (others => 'Z');
+ ddr2_cke : out std_logic;
+ ddr2_cs_n : out std_logic;
+ ddr2_ras_n : out std_logic;
+ ddr2_cas_n : out std_logic;
+ ddr2_we_n : out std_logic;
+ ddr2_dm : out std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
+ ddr2_ba : out std_logic_vector((BANK_ADDRESS-1) downto 0);
+ ddr2_a : out std_logic_vector((ROW_ADDRESS-1) downto 0);
+ ddr2_odt : out std_logic;
+ ddr2_ck : out std_logic_vector((CLK_WIDTH-1) downto 0);
+ ddr2_ck_n : out std_logic_vector((CLK_WIDTH-1) downto 0);
+
+ clk_int : in std_logic;
+ clk90_int : in std_logic;
+ delay_sel_val : in std_logic_vector(4 downto 0);
+ sys_rst : in std_logic;
+ sys_rst90 : in std_logic;
+ sys_rst180 : in std_logic;
+ -- debug signals
+ dbg_delay_sel : out std_logic_vector(4 downto 0);
+ dbg_rst_calib : out std_logic;
+ dbg_controller : out std_logic_vector(2 downto 0);
+ vio_out_dqs : in std_logic_vector(4 downto 0);
+ vio_out_dqs_en : in std_logic;
+ vio_out_rst_dqs_div : in std_logic_vector(4 downto 0);
+ vio_out_rst_dqs_div_en : in std_logic
+ );
+
+end component;
+
signal ddr2_rst0, ddr2_rst90, ddr2_rst180 : std_logic;
signal ddr2_clk0_int, ddr2_clk90_int : std_logic;
signal wait_200us : std_logic;
@@ -119,8 +196,6 @@ top_0 : vhdl_bl4_top_0
ddr2_we_n => ddr2_we_n,
ddr2_odt => ddr2_odt,
ddr2_dm => ddr2_dm,
- rst_dqs_div_in => rst_dqs_div_in,
- rst_dqs_div_out => rst_dqs_div_out,
ddr2_dqs => ddr2_dqs,
ddr2_dqs_n => ddr2_dqs_n,
ddr2_ck => ddr2_ck,
@@ -132,6 +207,7 @@ top_0 : vhdl_bl4_top_0
sys_rst => ddr2_rst0,
sys_rst90 => ddr2_rst90,
sys_rst180 => ddr2_rst180,
+ wait_200us => wait_200us,
user_input_data => ctrl_input_data,
user_data_mask => ctrl_data_mask,
diff --git a/2d_display_engine.srcs/sources_1/new/wb_ddr_ctrl_wb.vhd b/2d_display_engine.srcs/sources_1/new/wb_ddr_ctrl_wb.vhd
new file mode 100644
index 0000000..38ae24b
--- /dev/null
+++ b/2d_display_engine.srcs/sources_1/new/wb_ddr_ctrl_wb.vhd
@@ -0,0 +1,107 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 11/03/2012 10:51:41 PM
+-- Design Name:
+-- Module Name: wb_ddr_ctrl_wb - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool Versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity wb_ddr_ctrl_wb is
+ Port (
+ -- Control signals
+ sys_clock : in std_ulogic;
+ ddr2_clk0 : in std_ulogic;
+ ddr2_clk90 : in std_ulogic;
+ sys_reset : in std_ulogic;
+ ddr2_reset : in std_ulogic;
+
+ -- to DDR2 controller
+ ctrl_input_data : out std_logic_vector(31 downto 0);
+ ctrl_data_mask : out std_logic_vector(3 downto 0);
+ ctrl_output_data : in std_logic_vector(31 downto 0) := (others => 'Z');
+ ctrl_data_valid : in std_logic;
+ ctrl_input_address : out std_logic_vector(((13 + 10 + 2)-1) downto 0);
+ ctrl_command_register : out std_logic_vector(2 downto 0);
+ ctrl_burst_done : out std_logic;
+ ctrl_auto_ref_req : in std_logic;
+ ctrl_cmd_ack : in std_logic;
+ ctrl_init_done : in std_logic;
+ ctrl_ar_done : in std_logic
+ );
+end wb_ddr_ctrl_wb;
+
+architecture Behavioral of wb_ddr_ctrl_wb is
+
+-- DDR2 Controller commands
+constant ctrl_command_nop : std_logic_vector(2 downto 0) := "000";
+constant ctrl_command_initialize : std_logic_vector(2 downto 0) := "010";
+constant ctrl_command_write : std_logic_vector(2 downto 0) := "100";
+constant ctrl_command_read : std_logic_vector(2 downto 0) := "110";
+
+-- DDR-side FSM
+type ctrl_states is (S_RESET, S_INITIALIZE, S_WAITINITDONE, S_IDLE, S_REFRESH);
+signal ctrl_state : ctrl_states := S_RESET;
+
+begin
+
+ ctrl_fsm : process(ddr2_clk0)
+ begin
+ if falling_edge(ddr2_clk0) then
+ if ddr2_reset = '0' then
+ ctrl_state <= S_RESET;
+ ctrl_input_data <= (others => '-');
+ ctrl_data_mask <= (others => '0');
+ ctrl_input_address <= (others => '-');
+ ctrl_burst_done <= '0';
+ ctrl_command_register <= ctrl_command_nop;
+ else
+ ctrl_command_register <= ctrl_command_nop;
+ case ctrl_state is
+ when S_RESET =>
+ ctrl_state <= S_INITIALIZE;
+ when S_INITIALIZE =>
+ ctrl_command_register <= ctrl_command_initialize;
+ ctrl_state <= S_WAITINITDONE;
+ when S_WAITINITDONE =>
+ if ctrl_init_done = '1' then
+ ctrl_state <= S_IDLE;
+ end if;
+ when S_IDLE =>
+ if ctrl_auto_ref_req = '1' then
+ ctrl_state <= S_REFRESH;
+ end if;
+ when S_REFRESH =>
+ if ctrl_ar_done = '1' then
+ ctrl_state <= S_IDLE;
+ end if;
+ end case;
+ end if;
+ end if;
+ end process ctrl_fsm;
+
+end Behavioral;