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-- Company: 
-- Engineer: 
-- 
-- Create Date:    14:10:50 12/28/2008 
-- Design Name: 
-- Module Name:    fifo16x8 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity fifo16x8 is
    Port ( DATAIN : in  STD_LOGIC_VECTOR (7 downto 0);
           WRITESTB : in  STD_LOGIC;
           DATAOUT : out  STD_LOGIC_VECTOR (7 downto 0);
           READSTB : in  STD_LOGIC;
           CLK : in  STD_LOGIC;
           FULL : out  STD_LOGIC;
           EMPTY : out  STD_LOGIC);
end fifo16x8;

architecture Behavioral of fifo16x8 is
signal counter: std_logic_vector(3 downto 0) := "1111";
begin

shift:	for i in 0 to 7 generate
  srl16e_inst:	SRL16E port map(
    Q => DATAOUT(i),
    A0 => counter(0),
    A1 => counter(1),
    A2 => counter(2),
    A3 => counter(3),
    CE => WRITESTB,
    CLK => CLK,
    D => DATAIN(i));
end generate;
	
fifo:	process(CLK)
	begin
          if rising_edge(CLK) then
            if (WRITESTB = '0') and (READSTB = '1') then
              counter <= counter - 1;
            elsif (WRITESTB = '1') and (READSTB = '0') then
              counter <= counter + 1;
            else
              counter <= counter;
            end if;
          end if;
	end process;

FULL <= '1' when counter = "1110" else '0';
EMPTY <= '1' when counter = "1111" else '0';
end Behavioral;

