----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:37:34 12/08/2008 
-- Design Name: 
-- Module Name:    syncgen - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity syncgen is
    Port ( CLKPIXEL : in  STD_LOGIC;
           VSYNC : out  STD_LOGIC;
           HSYNC : out  STD_LOGIC;
           COLUMN : out  STD_LOGIC_VECTOR (9 downto 0);
           ROW : out  STD_LOGIC_VECTOR (9 downto 0));
end syncgen;

architecture Behavioral of syncgen is
signal hsync_i, hsync_i_old: std_logic := '1';
signal vsync_i: std_logic := '1';
signal row_i: std_logic_vector(9 downto 0) := "0000000000";
signal column_i: std_logic_vector(9 downto 0) := "0000000000";
begin
  hsync_p: process(CLKPIXEL)
  begin
    if rising_edge(CLKPIXEL) then
      if column_i = 799 then
        column_i <= "0000000000";
      else
        column_i <= column_i + 1;
      end if;
      
      if column_i >= 658 and column_i <= 753 then -- generate hsync pulse (one clock early, it is delayed later)
        hsync_i <= '0'; -- hsync is low active
      else
        hsync_i <= '1';
      end if;
      
      HSYNC <= hsync_i; -- delay hsync 1 clock
    end if;
  end process;

  vsync_p: process(CLKPIXEL)
  begin
    if rising_edge(CLKPIXEL) then
      if (hsync_i = '0') and (hsync_i_old = '1') then
        if row_i = 524 then
          row_i <= "0000000000";
        else
          row_i <= row_i + 1;
        end if;
					
        if row_i = 493 then -- generate vsync pulse
          vsync_i <= '0'; -- vsync is low active
        else
          vsync_i <= '1';
        end if;
      end if;
      hsync_i_old <= hsync_i;
    end if;
  end process;
					
COLUMN <= column_i;
ROW <= row_i;
VSYNC <= vsync_i;
end Behavioral;

