-------------------------------------------------------------------------------
-- Title      : Testbench for design "toplevel"
-- Project    : 
-------------------------------------------------------------------------------
-- File       : toplevel_tb.vhd
-- Author     : U-MATTHIAS-THINKP\Matthias  <Matthias@matthias-thinkp>
-- Company    : 
-- Created    : 2009-01-03
-- Last update: 2009-01-03
-- Platform   : 
-- Standard   : VHDL'87
-------------------------------------------------------------------------------
-- Description: 
-------------------------------------------------------------------------------
-- Copyright (c) 2009 
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author  Description
-- 2009-01-03  1.0      Matthias	Created
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

use work.sim_bmppack.all;

-------------------------------------------------------------------------------

entity toplevel_tb is

end toplevel_tb;

-------------------------------------------------------------------------------

architecture tb of toplevel_tb is

  component toplevel
    port (
       -- Clock (50 MHz)
      CLKIN_50M : in  STD_LOGIC;
      -- NASBUS
      ADDR : out  STD_LOGIC_VECTOR (15 downto 0);
      DATA : inout  STD_LOGIC_VECTOR (7 downto 0);
      M1_n : out STD_LOGIC;
      MREQ_n : out STD_LOGIC;
      IORQ_n : out  STD_LOGIC;
      WR_n : out  STD_LOGIC;
      RD_n : out  STD_LOGIC;
      RFSH_n : out STD_LOGIC;
      HALT_n : out STD_LOGIC;
      BUSAK_n : out STD_LOGIC;
      RESET_n : in STD_LOGIC;
      WAIT_n : in STD_LOGIC;
      INT_n : in STD_LOGIC;
      NMI_n : in STD_LOGIC;
      BUSRQ_n : in STD_LOGIC;
      -- VGA out
      RED, GREEN, BLUE : out STD_LOGIC_VECTOR(3 downto 0);
      HSYNC, VSYNC : out STD_LOGIC
      );
  end component;

  -- component ports
  signal CLKIN_50M     : STD_LOGIC := '0';
  signal ADDR    : STD_LOGIC_VECTOR (15 downto 0);
  signal DATA    : STD_LOGIC_VECTOR (7 downto 0);
  signal M1_n    : STD_LOGIC;
  signal MREQ_n  : STD_LOGIC;
  signal IORQ_n  : STD_LOGIC;
  signal WR_n    : STD_LOGIC;
  signal RD_n    : STD_LOGIC;
  signal RFSH_n  : STD_LOGIC;
  signal HALT_n  : STD_LOGIC;
  signal BUSAK_n : STD_LOGIC;
  signal RESET_n : STD_LOGIC := '0';
  signal WAIT_n  : STD_LOGIC := '1';
  signal INT_n   : STD_LOGIC := '1';
  signal NMI_n   : STD_LOGIC := '1';
  signal BUSRQ_n : STD_LOGIC := '1';
  signal RED, GREEN, BLUE : std_logic_vector(3 downto 0);
  signal VSYNC, HSYNC : std_logic;

begin  -- tb

  -- component instantiation
  DUT: toplevel
    port map (
      CLKIN_50M     => CLKIN_50M,
      ADDR    => ADDR,
      DATA    => DATA,
      M1_n    => M1_n,
      MREQ_n  => MREQ_n,
      IORQ_n  => IORQ_n,
      WR_n    => WR_n,
      RD_n    => RD_n,
      RFSH_n  => RFSH_n,
      HALT_n  => HALT_n,
      BUSAK_n => BUSAK_n,
      RESET_n => RESET_n,
      WAIT_n  => WAIT_n,
      INT_n   => INT_n,
      NMI_n   => NMI_n,
      BUSRQ_n => BUSRQ_n,
      RED     => RED,
      GREEN   => GREEN,
      BLUE    => BLUE,
      VSYNC   => VSYNC,
      HSYNC   => HSYNC
      );

  -- clock generation
  CLKIN_50M <= not CLKIN_50M after 10 ns;

  -- waveform generation
  WaveGen_Proc: process
  begin
    -- insert signal assignments here
    wait for 100 ns;
    RESET_n <= '1';
    wait;
  end process WaveGen_Proc;

  VGARead: process
  variable i: integer := 0;
  variable pixeldata : std_logic_vector(23 downto 0);
  begin
    ReadFile("vga.bmp");
    wait until CLKIN_50M = '1';       -- wait for uut to stat
    wait for 260 ns;                  -- wait for vga frame to start (depends
                                        -- on latency of UUT)
    while true loop
      for y in 479 downto 0 loop
        for x in 0 to 639 loop
          pixeldata := RED & "0000" & GREEN & "0000" & BLUE & "0000";
          SetPixel(x, y, pixeldata);
          wait for 40 ns;
        end loop;  -- x
        wait for 6400 ns;
      end loop;  -- x
      wait for 1440 us;
      WriteFile("vga" & integer'image(i) & ".bmp");
      i := i + 1;
    end loop;
  end process;

end tb;

-------------------------------------------------------------------------------

configuration toplevel_tb_tb_cfg of toplevel_tb is
  for tb
  end for;
end toplevel_tb_tb_cfg;

-------------------------------------------------------------------------------
