commit a5dbc23f5ea8f2a9f2b4bae9a24fadd6ab441f7b Author: matthias <> Date: Thu Jan 15 19:17:56 2009 +0000 Initial commit diff --git a/Basic.coe b/Basic.coe new file mode 100755 index 0000000..c98f8c8 --- /dev/null +++ b/Basic.coe @@ -0,0 +1,1026 @@ +memory_initialization_radix = 16; +memory_initialization_vector = +C3, 03, E0, F3, DD, 21, 00, 00, +C3, 12, E0, 8B, E9, F2, F0, C3, +3C, E7, 21, 00, 10, F9, C3, BB, +FE, 11, DF, E2, 06, 63, 21, 00, +10, 1A, 77, 23, 13, 05, C2, 21, +E0, F9, CD, DF, E4, CD, 81, EB, +32, AA, 10, 32, F9, 10, 21, 03, +E1, CD, 10, F2, CD, FC, E4, CD, +36, E8, B7, C2, 5B, E0, 21, 5D, +11, 23, 7C, B5, CA, 6D, E0, 7E, +47, 2F, 77, BE, 70, CA, 49, E0, +C3, 6D, E0, CD, A5, E9, B7, C2, +AD, E3, EB, 2B, 3E, D9, 46, 77, +BE, 70, C2, 36, E0, 2B, 11, 5C, +11, CD, 8A, E6, DA, 36, E0, 00, +00, 00, 00, 00, 00, 00, 00, 00, +11, CE, FF, 22, AF, 10, 19, 22, +5A, 10, CD, BA, E4, 2A, 5A, 10, +11, EF, FF, 19, 11, F9, 10, 7D, +93, 6F, 7C, 9A, 67, E5, 21, C5, +E0, CD, 10, F2, E1, CD, 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+10, FE, FF, C2, 06, E9, C3, 10, +E9, CD, 81, EB, C3, F2, E5, CD, +81, EB, C3, F2, E5, F5, A0, C1, +B8, 3E, 00, C9, CD, 9B, E6, C3, +81, EB, C3, DE, FD, C3, B1, E0; \ No newline at end of file diff --git a/KCPSM3.EXE b/KCPSM3.EXE new file mode 100755 index 0000000..fb0035d Binary files /dev/null and b/KCPSM3.EXE differ diff --git a/Makefile b/Makefile new file mode 100755 index 0000000..d36feef --- /dev/null +++ b/Makefile @@ -0,0 +1,45 @@ +XILINX=C:/Xilinx92i +XILPATH=$(XILINX)/bin/nt +INFILES=toplevel.vhd memory.vhd coregen/charrom.vhd coregen/monitorrom.vhd coregen/basic_rom.vhd coregen/ram2kx8.vhd coregen/dcm_in50.vhd T80_Pack.vhd T80_ALU.vhd T80_MCode.vhd T80_RegX.vhd T80.vhd T80a.vhd T80se.vhd video.vhd videogen.vhd syncgen.vhd keyboard.vhd uart.vhd kcpsm3.vhd uartprog.vhd fifo16x8.vhd spi.vhd +NGCFILE=nascom2.ngc +XSTFILE=nascom2.xst +UCF=nascom2.ucf +PCFFILE=nascom2.pcf +NGDFILE=nascom2.ngd +NCDFILE=nascom2.ncd +NCDFILE_R=nascom2_routed.ncd +BITFILE=nascom2.bit +TWRFILE=nascom2.twr + +PART=xc3s700an-fgg484-4 +NGDOPTS=-p $(PART) -aul -uc $(UCF) -sd coregen/ +MAPOPTS=-p $(PART) -cm area +PAROPTS=-rl high -pl high +BITGENOPTS= +TRACEOPTS=-v -u 100 + +all: $(BITFILE) + +%.vhd: %.psm + KCPSM3.exe $< + +$(NGCFILE): $(INFILES) + $(XILPATH)/xst -ifn $(XSTFILE) + +$(NGDFILE): $(NGCFILE) $(UCF) + $(XILPATH)/ngdbuild $(NGDOPTS) $(NGCFILE) $(NGDFILE) + +$(PCFFILE) $(NCDFILE) : $(NGDFILE) + $(XILPATH)/map $(MAPOPTS) -o $(NCDFILE) $(NGDFILE) $(PCFFILE) + +$(NCDFILE_R): $(PCFFILE) $(NCDFILE) + $(XILPATH)/par -w $(PAROPTS) $(NCDFILE) $(NCDFILE_R) $(PCFFILE) + +$(BITFILE): $(NCDFILE_R) $(PCFFILE) + $(XILPATH)/bitgen -w $(BITGENOPTS) $(NCDFILE_R) $(BITFILE) $(PCFFILE) + +$(TWRFILE): $(NCDFILE_R) $(PCFFILE) + $(XILPATH)/trce $(TRACEOPTS) -o $(TWRFILE) $(NCDFILE_R) $(PCFFILE) + +clean: + rm -f $(NGCFILE) $(PCFFILE) $(NGDFILE) $(NCDFILE) $(NCDFILE_R) $(BITFILE) diff --git a/NASSYSI.coe b/NASSYSI.coe new file mode 100755 index 0000000..a9cccf5 --- /dev/null +++ b/NASSYSI.coe @@ -0,0 +1,258 @@ +memory_initialization_radix=16; +memory_initialization_vector= +31, 00, 10, D7, 08, C3, B2, 03, +DF, 62, D8, 18, FB, C3, 9A, 03, +E5, F5, 37, 21, 08, 00, 18, 05, +E5, F5, A7, 18, F6, C3, 70, 05, +E3, 2B, E3, C3, 1A, 04, 00, 00, +E3, 7E, 23, B7, 20, 06, E3, C9, +E5, C3, 5A, 07, F7, 18, F2, 00, +3D, C8, F5, F1, 18, FA, AF, 47, +FF, FF, 10, FC, C9, E5, 21, 00, +0C, AE, D3, 00, 7E, D3, 00, E1, +C9, 3E, 10, E5, 21, 00, 0C, AE, +77, 18, F2, F5, D3, 01, DB, 02, +CB, 77, 28, FA, F1, C9, C3, 7D, +0C, 1E, C0, DF, 62, D8, 1D, 20, +FA, C9, 2A, 29, 0C, 56, 36, 5F, +D7, EF, 72, D8, D7, EB, 30, F2, +C9, DB, 02, 17, D0, DB, 01, C9, +3E, 02, CD, 45, 00, 21, 01, 0C, +DB, 00, 2F, 77, 06, 08, 3E, 01, +CD, 45, 00, 23, DB, 00, 2F, 57, +AE, 20, 04, 10, F1, B7, C9, AF, +FF, DB, 00, 2F, 5F, 7A, AE, 0E, +FF, 16, 00, 37, CB, 12, 0C, 1F, +30, FA, 7A, A3, 5F, 7E, A2, BB, +28, E1, 7E, AA, 77, 7B, B7, 28, +DA, 3A, 01, 0C, E6, 10, B0, 87, +87, 87, B1, D7, 5B, 28, 06, E6, +7F, D7, 55, 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0C, 19, 19, +5E, 23, 56, EB, 18, E8, FF, FF, +FF, FF, FF, FF, FF, FF, 08, FF, +8E, FF, 88, 09, FF, FF, FF, 3E, +2E, 46, 36, BE, AE, 0E, FF, FF, +FF, 89, FF, FF, FF, FF, 14, 9C, +9B, A3, 92, C2, BA, B2, AA, A2, +98, A0, 29, 0A, 21, 19, 1A, 1C, +1B, 23, 12, 42, 3A, 32, 2A, 22, +18, 20, A9, 8A, A1, 99, 0D, 2C, +41, 13, 3B, 33, 43, 10, 40, 2D, +38, 30, 28, 31, 39, 25, 1D, 24, +15, 34, 45, 35, 11, 2B, 44, 3D, +3C, 1E, 9E, 16, 9A, 96, 7D, 32, +27, 0C, C9, 22, 23, 0C, C9, 44, +4D, ED, 59, C9, 44, 4D, ED, 78, +DF, 68, C3, 11, 03, ED, 4B, 10, +0C, ED, 5B, 0E, 0C, 2A, 0C, 0C, +C9, 21, 7A, 07, DF, 71, E5, 21, +4C, 06, 06, 06, 7E, F7, 0E, 14, +AF, FF, 0D, 20, FC, 23, 10, F4, +DF, 57, AF, FF, 3E, 45, F7, 2A, +10, 0C, DF, 66, 3E, 0D, F7, E1, +22, 73, 0C, C9, 0D, 45, 30, 0D, +52, 0D, 0E, 00, 7E, 81, 4F, 7E, +DF, 6F, 23, 10, F7, C9, DF, 5F, +DF, 77, E5, DF, 78, E5, CF, FE, +FF, 20, 0B, 06, 03, CF, FE, FF, +20, 04, 10, F9, 18, 1B, FE, 1B, +20, EC, 06, 03, CF, FE, 1B, 20, +E6, 10, F9, EF, 18, 00, E1, 22, +75, 0C, E1, 22, 73, 0C, C3, 51, +00, CF, 6F, CF, 67, CF, 5F, CF, +57, 0E, 00, DF, 6C, CF, B9, 20, +1E, 43, 0E, 00, 3A, 2B, 0C, FE, +52, 28, 03, CF, 18, 02, CF, 77, +E5, 2A, 29, 0C, 77, E1, 81, 4F, +23, 10, E9, CF, B9, 28, 06, EF, +3F, 20, 00, 18, A1, EF, 2E, 20, +00, AF, BA, 20, 99, 18, B4, 21, +81, 07, DF, 72, 21, 7E, 07, DF, +71, C9, 7D, 32, 28, 0C, 21, 85, +07, DF, 72, 21, 7D, 07, DF, 71, +C9, DF, 70, D0, E6, 7F, F5, 21, +28, 0C, CB, 6E, CC, 21, 07, D7, +20, F1, FE, 7F, 20, 01, AF, FE, +1B, 28, 05, B7, 28, 02, CB, FE, +37, C9, F5, 21, 28, 0C, CB, 7E, +CC, 17, 07, CB, BE, F1, C9, D7, +08, FE, 0D, C0, CB, 66, C0, 3E, +0A, B7, C8, F5, EA, 29, 07, EE, +80, CB, 46, 28, 02, EE, 80, DF, +6F, F1, C9, DF, 7B, F7, 18, FB, +DF, 78, 21, 7F, 07, E5, 2A, 73, +0C, E3, 22, 73, 0C, E1, C9, 21, +82, 07, E5, 2A, 75, 0C, E3, 22, +75, 0C, E1, C9, E5, 21, 75, 0C, +18, 03, 21, 73, 0C, D5, C5, 5E, +23, 56, F5, 1A, 13, B7, 28, 0D, +32, 0A, 0C, F1, D5, B7, CD, 8A, +05, D1, 30, EE, F5, F1, C1, D1, +E1, C9, 65, 6F, 00, 6E, 75, 65, +00, 76, 61, 70, 00, 74, 61, 00, +47, 05, 03, 06, 44, 05, 0A, 03, +F4, 03, 0A, 03, 21, 06, 33, 07, +35, 05, FA, FF, FE, 05, 94, 04, +40, 02, 38, 07, 07, 06, 0A, 03, +0C, 06, 5E, 06, F9, 03, C7, 02, +CF, 06, 5E, 06, E8, 04, DA, 06, +0A, 03, FD, FF, B2, 03, 8A, 05, +3E, 00, 45, 00, 51, 00, 15, 06, +88, 00, 54, 07, B5, 02, 33, 03, +4F, 01, 00, 03, 15, 03, 19, 03, +06, 03, 11, 03, 0A, 03, 2D, 03, +52, 06, 0A, 07, 5B, 00, 81, 00, +3D, 07, 4A, 07, 5D, 07, E9, 06, +77, 0C, 7A, 0C, 3A, 07, 47, 07, +6C, 03, 21, 03, 72, 00, 34, 02; \ No newline at end of file diff --git a/Nasbugt2.coe b/Nasbugt2.coe new file mode 100755 index 0000000..ca7aa5e --- /dev/null +++ b/Nasbugt2.coe @@ -0,0 +1,130 @@ +memory_initialization_radix = 16; +memory_initialization_vector = +31, 33, 0C, 21, 00, 0C, 06, 15, +36, 00, 23, 10, FB, 21, 28, 01, +11, 3D, 0C, 01, 13, 00, ED, B0, +3E, 1E, CD, 3B, 01, C3, 59, 03, +F5, E5, D5, C3, 26, 03, 00, 00, +E3, 7E, 23, B7, 28, 05, CD, 4A, +0C, 18, F6, E3, C9, AF, F5, F1, +F5, F1, 3D, 20, F9, C9, CD, 4D, +0C, D8, DB, 02, 17, 30, F7, DB, +01, C9, F5, CD, 53, 00, F1, 18, +02, 3E, 10, E5, 21, 00, 0C, AE, +D3, 00, 77, E1, C9, D3, 01, DB, +02, 87, F8, 18, FA, 00, C3, 47, +0C, C5, D5, E5, 3E, 02, CD, 4A, +00, 21, 01, 0C, DB, 00, 2F, 77, +06, 08, 3E, 01, CD, 4A, 00, 23, +DB, 00, 2F, 57, AE, 20, 07, 10, +F1, B7, E1, D1, C1, C9, CD, 35, +00, DB, 00, 2F, 5F, 7A, AE, 0E, +FF, 16, 00, 37, CB, 12, 0C, 1F, +30, FA, 7A, A3, 5F, 7E, A2, BB, +28, DD, 7E, AA, 77, 7B, B7, 28, +D6, 3A, 01, 0C, E6, 10, B0, 87, +87, 87, B1, ED, 4B, 3F, 0C, 2A, +43, 0C, ED, B1, 28, 0B, 2A, 43, +0C, ED, 4B, 3F, 0C, E6, 7F, ED, +B1, 20, B6, ED, 4B, 43, 0C, 37, +ED, 42, ED, 4B, 41, 0C, 09, 7D, +37, 18, A7, 2A, 0C, 0C, 22, 15, +0C, C9, 08, 88, 09, 14, 9C, 9B, +A3, 92, C2, BA, B2, AA, A2, 98, +A0, 29, 0A, 21, 19, 1A, 1C, 1B, +23, 12, 42, 3A, 32, 2A, 22, 18, +20, B1, 8A, B9, 99, 0D, 2C, 41, +13, 3B, 33, 43, 10, 40, 2D, 38, +30, 28, 31, 39, 25, 1D, 24, 15, +34, 45, 35, 11, 2B, 44, 3D, 3C, +00, 10, 3E, 00, 1D, 00, EA, 00, +63, 03, C3, 05, 03, C3, 3B, 01, +C3, 69, 00, B7, C8, F5, C5, D5, +E5, FE, 1E, 20, 2F, 21, 09, 08, +36, FF, 23, 06, 30, 36, 20, 23, +10, FB, 06, 10, 36, 00, 23, 10, +FB, EB, 21, 0A, 08, 01, B0, 03, +ED, B0, 3E, FF, 32, BA, 0B, 21, +8A, 0B, 36, 5F, 22, 18, 0C, E1, +D1, C1, F1, C9, 2A, 18, 0C, 36, +20, FE, 1D, 20, 0B, 2B, 7E, B7, +28, FB, 3C, 20, E5, 23, 18, E2, +FE, 1F, 28, 09, 77, 23, 7E, B7, +28, FB, 3C, 20, D5, 11, 0A, 08, +21, 4A, 08, 01, 70, 03, ED, B0, +21, 10, 00, 19, 06, 30, 36, 20, +23, 10, FB, 18, BA, 2A, 0C, 0C, +CD, 32, 02, 7E, CD, 44, 02, CD, +DB, 01, 11, 52, 0B, 06, 00, E5, +CD, 5A, 02, 7E, B7, 28, 08, 23, +7E, E1, 77, 04, 23, 18, F0, E1, +1A, FE, 2E, C8, 78, B7, 20, 01, +23, 18, D5, EF, 3E, 00, CD, 3E, +00, FE, 1D, 28, 09, FE, 1F, 28, +57, CD, 4A, 0C, 18, F0, ED, 5B, +18, 0C, 1B, 1A, FE, 3E, 28, E6, +3E, 1D, 18, ED, 2A, 0C, 0C, ED, +5B, 0E, 0C, E5, B7, ED, 52, E1, +38, 05, EF, 2E, 1F, 00, C9, 0E, +00, CD, 32, 02, 06, 08, 7E, CD, +2B, 02, 23, CD, 3C, 02, 10, F6, +79, CD, 44, 02, EF, 1D, 1D, 1F, +00, 18, D4, 57, 81, 4F, 7A, C3, +44, 02, 7C, CD, 2B, 02, 7D, CD, +2B, 02, 18, 00, 3E, 20, 18, 17, +3E, 1F, 18, 13, F5, 1F, 1F, 1F, +1F, CD, 4D, 02, F1, E6, 0F, C6, +30, FE, 3A, 38, 02, C6, 07, C3, +4A, 0C, 1A, FE, 20, 13, 28, FA, +1B, AF, 21, 12, 0C, 77, 23, 77, +23, 77, 1A, 2B, 2B, D6, 30, F8, +FE, 0A, 38, 08, D6, 07, FE, 0A, +F8, FE, 10, F0, 13, 34, 23, ED, +6F, 23, ED, 6F, 18, E4, CD, DB, +01, 11, 4B, 0B, 01, 0A, 0C, 1A, +FE, 20, 20, 05, 0A, FE, 53, 20, +ED, 02, 03, 13, AF, 02, 03, CD, +5A, 02, 7E, B7, 28, 0D, 23, 7E, +02, 23, 03, 7E, 02, 21, 0B, 0C, +34, 18, EB, ED, 4B, 0A, 0C, 2A, +45, 0C, 7E, B7, 28, C8, 23, B9, +28, 05, 00, 23, 23, 18, F3, 5E, +23, 56, 21, 86, 02, E5, EB, E9, +3E, FF, 32, 1A, 0C, 21, 05, 03, +22, 48, 0C, E1, 3A, 0B, 0C, B7, +28, 06, 2A, 0C, 0C, 22, 3B, 0C, +C1, D1, F1, F1, 2A, 3D, 0C, F9, +2A, 3B, 0C, E5, 2A, 37, 0C, F5, +3E, 08, D3, 00, F1, ED, 45, AF, +32, 1A, 0C, 18, D0, E3, 23, E3, +F5, E5, 3A, 00, 0C, D3, 00, 3A, +1A, 0C, B7, 28, 10, 2A, 15, 0C, +7E, 32, 17, 0C, 36, E7, E1, F1, +E3, 2B, E3, ED, 45, D5, C5, 21, +00, 00, 39, 11, 33, 0C, 31, 33, +0C, 01, 08, 00, ED, B0, 5E, 23, +56, 23, 1B, ED, 53, 3B, 0C, 22, +3D, 0C, 21, 3F, 0C, 06, 06, 2B, +7E, CD, 44, 02, 2B, 7E, CD, 44, +02, CD, 3C, 02, 10, F1, CD, 40, +02, 2A, 15, 0C, 3A, 17, 0C, 77, +C3, 86, 02, 4D, AD, 01, 43, EF, +03, 45, D0, 02, 53, FF, 02, 54, +FC, 01, 42, E3, 00, 4C, 7C, 03, +44, D1, 03, 00, CD, 51, 00, 21, +8A, 0B, 22, 18, 0C, CD, 3E, 00, +FE, 1D, 28, F9, FE, 1F, 28, 05, +CD, 4A, 0C, 20, F0, 11, 8A, 0B, +06, 08, 1A, FE, 2E, CA, 51, 00, +CD, 5A, 02, 2A, 13, 0C, 7D, 84, +4F, E5, 21, 00, 08, E5, E5, CD, +5A, 02, 23, 7E, E1, 77, 23, 81, +4F, 10, F3, CD, 5A, 02, 23, 7E, +B9, E1, D1, 20, 07, 01, 08, 00, +ED, B0, 18, B3, CD, 40, 02, 18, +AE, CD, 51, 00, 06, 00, CD, 35, +00, 10, FB, 2A, 4B, 0C, E5, 21, +5D, 00, 22, 4B, 0C, CD, FC, 01, +E1, 22, 4B, 0C, C3, 51, 00, 2A, +0C, 0C, ED, 5B, 0E, 0C, ED, 4B, +10, 0C, ED, B0, C9, 00, 00, 00; \ No newline at end of file diff --git a/Nasbugt4.coe b/Nasbugt4.coe new file mode 100755 index 0000000..e5fbd65 --- /dev/null +++ b/Nasbugt4.coe @@ -0,0 +1,258 @@ +memory_initialization_radix = 16; +memory_initialization_vector = +31, 33, 0C, C3, 57, 05, 00, 00, +31, 33, 0C, C3, 6D, 03, 00, 00, +E5, E1, E1, 23, E5, C3, B5, 05, +E5, E1, E1, 23, E5, C3, C2, 05, +E3, 2B, E3, C3, 05, 03, 00, 00, +E3, 7E, 23, B7, 20, 16, E3, C9, +C3, 4A, 0C, 00, 00, AF, F5, F1, +F5, F1, 3D, 20, F9, C9, CD, 4D, +0C, D8, 18, FA, F7, 18, E2, 00, +00, 00, F5, CD, 53, 00, F1, 18, +02, 3E, 10, E5, 21, 00, 0C, AE, +D3, 00, 77, E1, C9, F7, D3, 01, +DB, 02, 87, F8, 18, FA, C3, 47, +0C, C5, D5, E5, 3E, 02, CD, 4A, +00, 21, 01, 0C, DB, 00, 2F, 77, +06, 08, 3E, 01, CD, 4A, 00, 23, +DB, 00, 2F, 57, AE, 20, 07, 10, +F1, B7, C3, 70, 01, 00, CD, 35, +00, DB, 00, 2F, 5F, 7A, AE, 0E, +FF, 16, 00, 37, CB, 12, 0C, 1F, +30, FA, 7A, A3, 5F, 7E, A2, BB, +28, DD, 7E, AA, 77, 7B, B7, 28, +D6, 3A, 01, 0C, E6, 10, B0, 87, +87, 87, B1, ED, 4B, 3F, 0C, 2A, +43, 0C, ED, B1, 28, 0B, 2A, 43, +0C, ED, 4B, 3F, 0C, E6, 7F, ED, +B1, 20, B6, ED, 4B, 43, 0C, 37, +ED, 42, 7D, FE, 41, 38, 1E, FE, +5B, 30, 1A, 21, 01, 0C, CB, 66, +21, 41, 0C, 20, 08, CB, 46, 28, +0C, C6, 20, 18, 08, C6, 20, CB, +46, 28, 02, D6, 20, CD, DD, 04, +21, 41, 0C, CB, 56, 28, 02, EE, +80, 37, CB, 4E, CA, 8A, 00, FE, +20, 37, 28, F8, 21, 08, 0C, CB, +66, 28, F1, E1, D1, C1, CD, C6, +07, CD, 44, 02, B7, C3, 3C, 02, +00, 10, 60, 00, 00, 00, D4, 05, +55, 07, C3, 05, 03, C3, 3B, 01, +C3, F2, 04, B7, C8, C5, D5, E5, +F5, FE, 1E, 20, 2F, 21, 09, 08, +36, FF, 23, 06, 30, 36, 20, 23, +10, FB, 06, 10, 36, 00, 23, 10, +FB, EB, 21, 0A, 08, 01, B0, 03, +ED, B0, 3E, FF, 32, BA, 0B, 21, +8A, 0B, 36, 5F, 22, 18, 0C, F1, +E1, D1, C1, C9, 2A, 18, 0C, 36, +20, FE, 1D, 20, 0B, 2B, 7E, B7, +28, FB, 3C, 20, E5, 23, 18, E2, +FE, 1C, 28, DB, FE, 1F, 28, 09, +77, 23, 7E, B7, 28, FB, 3C, 20, +D1, 11, 0A, 08, 21, 4A, 08, 01, +70, 03, ED, B0, 06, 30, 2B, 36, +20, 10, FB, 18, BA, 2A, 0C, 0C, +CD, 32, 02, 7E, CD, 44, 02, CD, +81, 05, 11, 52, 0B, 06, 00, E5, +CD, 5A, 02, 7E, B7, 28, 08, 23, +7E, E1, 77, 04, 23, 18, F0, E1, +1A, FE, 2E, C8, 78, B7, C3, 8D, +05, 00, 00, EF, 3E, 00, CD, 3E, +00, FE, 1F, 28, 5B, F5, FE, 1D, +20, 06, ED, 5B, 18, 0C, 1B, 1A, +FE, 3E, 28, 04, F1, F7, 18, E6, +F1, AF, 18, F9, CD, 9B, 06, B7, +ED, 52, 19, 38, 05, EF, 2E, 1F, +00, C9, 0E, 00, EF, 20, 20, 00, +CD, 32, 02, 06, 08, 7E, CD, 2B, +02, 23, CD, 3C, 02, 10, F6, 79, +CD, 44, 02, EF, 1D, 1D, 1F, 00, +18, D5, 00, F5, 81, 4F, F1, C3, +44, 02, 7C, CD, 2B, 02, 7D, CD, +2B, 02, 00, 00, 3E, 20, 18, 17, +3E, 1F, 18, 13, F5, 1F, 1F, 1F, +1F, CD, 4D, 02, F1, E6, 0F, C6, +30, FE, 3A, 38, 02, C6, 07, C3, +4A, 0C, 1A, FE, 20, 13, 28, FA, +1B, AF, 21, 12, 0C, 77, 23, 77, +23, 77, 1A, 2B, 2B, D6, 30, F8, +FE, 0A, 38, 08, D6, 07, FE, 0A, +F8, FE, 10, F0, 13, 34, 23, ED, +6F, 23, ED, 6F, 18, E4, CD, 81, +05, 11, 4B, 0B, 01, 0A, 0C, 1A, +FE, 20, 20, 05, 0A, FE, 53, 20, +ED, 02, 03, 13, AF, 02, 03, CD, +5A, 02, 7E, B7, 28, 1C, 23, 7E, +02, 23, 03, 7E, 02, 21, 0B, 0C, +34, 7E, FE, 04, 38, E8, F5, F1, +EF, 45, 72, 72, 6F, 72, 1F, 00, +18, C4, 3A, 0A, 0C, 2A, 45, 0C, +CD, 66, 04, 11, 86, 02, D5, E9, +3E, FF, 32, 1A, 0C, 21, 05, 03, +22, 48, 0C, E1, 3A, 0B, 0C, B7, +28, 06, 2A, 0C, 0C, 22, 3B, 0C, +C1, D1, F1, F1, 2A, 3D, 0C, F9, +2A, 3B, 0C, E5, 2A, 37, 0C, F5, +3E, 08, D3, 00, F1, ED, 45, AF, +32, 1A, 0C, 18, D0, F5, E5, 3A, +00, 0C, D3, 00, 3A, 1A, 0C, B7, +28, 13, 2A, 15, 0C, 7E, 32, 17, +0C, 36, E7, AF, 32, 1A, 0C, 00, +00, E1, F1, ED, 45, D5, C5, 21, +00, 00, 39, 11, 33, 0C, 31, 33, +0C, 01, 08, 00, ED, B0, 5E, 23, +56, 23, 00, ED, 53, 3B, 0C, 22, +3D, 0C, CD, A5, 05, 06, 06, 2B, +7E, CD, 44, 02, 2B, 7E, CD, 44, +02, CD, 3C, 02, 10, F1, CD, D9, +06, 00, 00, 00, 2A, 15, 0C, 3A, +17, 0C, 77, AF, 32, 1A, 0C, CD, +A5, 05, C3, 86, 02, 2A, 28, 01, +22, 3D, 0C, 18, E7, CD, 3B, 01, +C3, 5E, 00, 00, CD, 51, 00, EF, +1C, 00, 00, CD, 3E, 00, FE, 2E, +28, 09, FE, 1F, 28, 0C, F4, 4A, +0C, 18, F0, EF, 1C, 2E, 1F, 00, +18, 63, 11, 8A, 0B, CD, 5A, 02, +7E, B7, 28, 28, 2A, 13, 0C, 7D, +84, 4F, E5, 21, 00, 08, 44, E5, +E5, CD, 5A, 02, 23, 7E, E1, 77, +23, 81, 4F, 10, F3, CD, 5A, 02, +23, 7E, B9, E1, D1, 20, 05, 4C, +ED, B0, 18, B3, CD, 40, 02, 18, +AE, CD, 51, 00, AF, 47, FF, 10, +FD, 2A, 4B, 0C, E5, 21, 75, 03, +22, 4B, 0C, CD, 40, 02, CD, FC, +01, E1, 22, 4B, 0C, 18, 0E, 2A, +0C, 0C, ED, 5B, 0E, 0C, ED, 4B, +10, 0C, ED, B0, C9, C3, 51, 00, +CD, 51, 00, AF, 47, FF, 10, FD, +2A, 0C, 0C, ED, 5B, 0E, 0C, EB, +37, ED, 52, DA, 51, 00, EB, AF, +FF, 00, 06, 05, AF, CD, 5E, 00, +3E, FF, 10, F9, AF, BA, 20, 02, +43, 04, 58, 7D, CD, 5E, 00, 7C, +CD, 5E, 00, 7B, CD, 5E, 00, 7A, +CD, 5E, 00, 0E, 00, CD, 5B, 04, +79, CD, 5E, 00, CD, CC, 06, 06, +0B, 79, CD, 5E, 00, AF, 10, FA, +CD, 40, 02, 18, B6, 1F, 45, 30, +1F, 52, 1F, CD, C6, 07, CD, 61, +04, CD, 32, 02, EB, C9, D5, 5F, +7E, 23, B7, 28, 07, BB, 28, 04, +23, 23, 18, F4, 5E, 23, 56, EB, +D1, C9, 21, CF, 07, 22, 4E, 0C, +21, BA, 04, 22, 4B, 0C, 3A, 0C, +0C, 32, 42, 0C, C9, 28, 05, B7, +28, 02, CB, FE, E1, 37, C9, 00, +2A, 45, 0C, 7E, B7, CA, 40, 02, +F7, CD, 3C, 02, 23, 23, 23, 18, +F2, 1F, 0D, 1F, 1E, 1B, 1E, 1D, +08, 1D, 1C, 0A, 00, 7F, 7F, 00, +00, 00, CD, 3B, 01, F5, CD, 02, +05, E5, 21, 42, 0C, CB, 7E, CC, +CF, 04, CB, BE, E1, F1, C9, CD, +ED, 07, FE, 0D, C0, CB, 66, C0, +3E, 0A, C3, ED, 07, 21, 01, 0C, +FE, 40, 20, 07, CB, 66, C0, F1, +C3, 89, 00, CB, 6E, 28, 02, EE, +40, C9, CD, 69, 00, D8, DB, 02, +17, D0, DB, 01, 37, C9, CD, F2, +04, D0, E5, 21, A9, 04, C3, 9A, +07, 00, 2A, 0C, 0C, 22, 45, 0C, +C9, 00, 3D, 00, CD, 97, 06, B7, +ED, 52, 19, D2, FA, 03, 0B, EB, +09, EB, 09, 03, ED, B8, C9, CD, +9B, 06, EB, E5, 19, CD, 32, 02, +E1, B7, ED, 52, CD, 32, 02, 2B, +2B, 7C, FE, FF, 20, 0A, CB, 7D, +20, 0D, EF, 3F, 3F, 1F, 00, C9, +B7, 20, F7, CB, 7D, 20, F3, 7D, +CD, 44, 02, C3, 40, 02, 00, 2A, +15, 0C, 3A, 17, 0C, 77, 21, 00, +0C, 06, 18, 36, 00, 23, 10, FB, +21, 28, 01, 11, 3D, 0C, 01, 13, +00, ED, B0, EF, 1E, 4E, 41, 53, +42, 55, 47, 20, 34, 00, C3, 63, +03, E5, 2A, 15, 0C, 7E, 32, 17, +0C, E1, C3, DB, 01, 20, 01, 23, +1A, FE, 3A, 20, 02, 2B, 2B, FE, +2F, 20, 07, 13, CD, 5A, 02, 2A, +13, 0C, C3, B0, 01, 2A, 18, 0C, +11, 8A, 0B, B7, ED, 52, 21, 3F, +0C, C2, 40, 02, C9, 2B, 3B, 3B, +F5, D5, 5E, 7B, 17, 9F, 57, 23, +18, 0D, 2B, 3B, 3B, F5, D5, 5E, +16, 00, 21, 00, 0E, 19, 19, 19, +D1, F1, E3, C9, FF, FF, FF, FF, +FF, FF, FF, FF, FF, FF, FF, FF, +FF, FF, FF, FF, FF, FF, FF, FF, +FF, FF, FF, FF, FF, FF, FF, FF, +89, 08, 88, 09, 14, 9C, 9B, A3, +92, C2, BA, B2, AA, A2, 98, A0, +29, 0A, 21, 19, 1A, 1C, 1B, 23, +12, 42, 3A, 32, 2A, 22, 18, 20, +A9, 8A, A1, 99, 0D, 2C, 41, 13, +3B, 33, 43, 10, 40, 2D, 38, 30, +28, 31, 39, 25, 1D, 24, 15, 34, +45, 35, 11, 2B, 44, 3D, 3C, FF, +FF, FF, 9A, FF, 3A, 0C, 0C, 32, +41, 0C, C9, 2A, 0C, 0C, 22, 15, +0C, C9, CD, 32, 02, CD, C6, 07, +3E, 1F, C3, 5D, 00, 00, 00, 00, +00, 0E, 00, CD, 3E, 00, 77, 81, +4F, 23, 10, F7, CD, 3E, 00, B9, +28, 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51, 06, 41, 27, 05, +42, 3B, 06, 43, EF, 03, 44, D1, +03, 45, D0, 02, 47, A3, 06, 49, +14, 05, 4B, 34, 06, 4C, 7C, 03, +4D, AD, 01, 4E, C0, 07, 4F, 77, +06, 51, 82, 06, 52, 0C, 07, 53, +FF, 02, 54, FC, 01, 57, 00, 04, +58, 7A, 04, 5A, 0A, 05, 3F, 98, +04, 00, B7, 02, CD, 3E, 00, F7, +18, FA, F5, CD, 66, 04, B7, 28, +04, F1, 7D, E1, C9, F1, E1, C9, +CD, AE, 07, C3, 3B, 01, E5, 21, +AA, 04, 18, E6, 21, FE, 04, 22, +4E, 0C, 21, A8, 07, E5, 18, 0A, +2A, 39, 01, 22, 4E, 0C, E5, 2A, +36, 01, 22, 4B, 0C, E1, C9, CD, +69, 00, D8, CD, F6, 04, D0, E6, +7F, E5, F5, 21, 42, 0C, CB, 6E, +CC, CF, 04, F1, CD, AE, 07, FE, +1E, C3, 8D, 04, 00, B7, C8, F5, +EA, F5, 07, EE, 80, CB, 46, 28, +02, EE, 80, CD, 5E, 00, F1, C9; \ No newline at end of file diff --git a/Naschr-1.coe b/Naschr-1.coe new file mode 100755 index 0000000..aa77295 --- /dev/null +++ b/Naschr-1.coe @@ -0,0 +1,258 @@ +memory_initialization_radix = 16; +memory_initialization_vector = +7F, 41, 41, 41, 41, 41, 41, 41, +7F, 00, 00, 00, 00, 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00, 00, 00, 00, 00, 00, 00, +00, 40, 20, 10, 08, 04, 02, 01, +00, 00, 00, 00, 00, 00, 00, 00, +3C, 04, 04, 04, 04, 04, 04, 04, +3C, 00, 00, 00, 00, 00, 00, 00, +00, 08, 1C, 2A, 49, 08, 08, 08, +00, 00, 00, 00, 00, 00, 00, 00, +00, 00, 00, 00, 00, 00, 00, 00, +7F, 00, 00, 00, 00, 00, 00, 00, +18, 18, 08, 04, 00, 00, 00, 00, +00, 00, 00, 00, 00, 00, 00, 00, +00, 00, 00, 3C, 02, 3E, 42, 42, +3D, 00, 00, 00, 00, 00, 00, 00, +40, 40, 40, 5C, 62, 42, 42, 62, +5C, 00, 00, 00, 00, 00, 00, 00, +00, 00, 00, 3C, 42, 40, 40, 42, +3C, 00, 00, 00, 00, 00, 00, 00, +02, 02, 02, 3A, 46, 42, 42, 46, +3A, 00, 00, 00, 00, 00, 00, 00, +00, 00, 00, 3C, 42, 7E, 40, 40, +3C, 00, 00, 00, 00, 00, 00, 00, +0C, 12, 10, 10, 7C, 10, 10, 10, +10, 00, 00, 00, 00, 00, 00, 00, +00, 00, 00, 3A, 46, 42, 42, 46, +3A, 02, 42, 3C, 00, 00, 00, 00, +40, 40, 40, 5C, 62, 42, 42, 42, +42, 00, 00, 00, 00, 00, 00, 00, +00, 08, 00, 18, 08, 08, 08, 08, +1C, 00, 00, 00, 00, 00, 00, 00, +00, 02, 00, 06, 02, 02, 02, 02, +02, 02, 22, 1C, 00, 00, 00, 00, +40, 40, 40, 44, 48, 50, 68, 44, +42, 00, 00, 00, 00, 00, 00, 00, +18, 08, 08, 08, 08, 08, 08, 08, +1C, 00, 00, 00, 00, 00, 00, 00, +00, 00, 00, 76, 49, 49, 49, 49, +49, 00, 00, 00, 00, 00, 00, 00, +00, 00, 00, 5C, 62, 42, 42, 42, +42, 00, 00, 00, 00, 00, 00, 00, +00, 00, 00, 3C, 42, 42, 42, 42, +3C, 00, 00, 00, 00, 00, 00, 00, +00, 00, 00, 5C, 62, 42, 42, 62, +5C, 40, 40, 40, 00, 00, 00, 00, +00, 00, 00, 3A, 46, 42, 42, 46, +3A, 02, 02, 02, 00, 00, 00, 00, +00, 00, 00, 5C, 62, 40, 40, 40, +40, 00, 00, 00, 00, 00, 00, 00, +00, 00, 00, 3C, 42, 30, 0C, 42, +3C, 00, 00, 00, 00, 00, 00, 00, +00, 10, 10, 7C, 10, 10, 10, 12, +0C, 00, 00, 00, 00, 00, 00, 00, +00, 00, 00, 42, 42, 42, 42, 46, +3A, 00, 00, 00, 00, 00, 00, 00, +00, 00, 00, 41, 41, 41, 22, 14, +08, 00, 00, 00, 00, 00, 00, 00, +00, 00, 00, 41, 49, 49, 49, 49, +36, 00, 00, 00, 00, 00, 00, 00, +00, 00, 00, 42, 24, 18, 18, 24, +42, 00, 00, 00, 00, 00, 00, 00, +00, 00, 00, 42, 42, 42, 42, 46, +3A, 02, 42, 3C, 00, 00, 00, 00, +00, 00, 00, 7E, 04, 08, 10, 20, +7E, 00, 00, 00, 00, 00, 00, 00, +0C, 10, 10, 10, 20, 10, 10, 10, +0C, 00, 00, 00, 00, 00, 00, 00, +08, 08, 08, 00, 00, 08, 08, 08, +00, 00, 00, 00, 00, 00, 00, 00, +18, 04, 04, 04, 02, 04, 04, 04, +18, 00, 00, 00, 00, 00, 00, 00, +7F, 00, 00, 00, 00, 00, 00, 00, +00, 00, 00, 00, 00, 00, 00, 00, +24, 49, 12, 24, 49, 12, 24, 49, +12, 00, 00, 00, 00, 00, 00, 00; \ No newline at end of file diff --git a/ROM_form.coe b/ROM_form.coe new file mode 100755 index 0000000..97d039b --- /dev/null +++ b/ROM_form.coe @@ -0,0 +1,29 @@ +component_name={name}; +width_a=18; +depth_a=1024; +configuration_port_a=read_only; +port_a_enable_pin=false; +port_a_handshaking_pins=false; +port_a_register_inputs=false; +port_a_init_pin=false; +port_a_init_value=00000; +port_a_additional_output_pipe_stages = 0; +port_a_register_inputs = false; +port_a_active_clock_edge = Rising_Edge_Triggered; +width_b=18; +depth_b=1024; +configuration_port_b=read_and_write; +write_mode_port_b=read_after_write; +port_b_enable_pin=false; +port_b_handshaking_pins=false; +port_b_register_inputs=false; +port_b_init_pin=false; +port_b_init_value=00000; +port_b_additional_output_pipe_stages = 0; +port_b_register_inputs = false; +port_b_active_clock_edge = Rising_Edge_Triggered; +port_b_write_enable_polarity = Active_High; +memory_initialization_radix=16; +global_init_value=00000; +memory_initialization_vector= + diff --git a/ROM_form.v b/ROM_form.v new file mode 100755 index 0000000..6ce5dfe --- /dev/null +++ b/ROM_form.v @@ -0,0 +1,350 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2004 Xilinx, Inc. +// All Rights Reserved +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: 1.02 +// \ \ Filename: ROM_form.v +// / / Date Last Modified: September 7 2004 +// /___/ /\ Date Created: July 2003 +// \ \ / \ +// \___\/\___\ +// +//Device: Xilinx +//Purpose: +// This is the Verilog template file for the KCPSM3 assembler. +// It is used to configure a Spartan-3, Virtex-II or Virtex-IIPRO block +// RAM to act as a single port program ROM. +// +// This Verilog file is not valid as input directly into a synthesis or +// simulation tool. The assembler will read this template and insert the +// data required to complete the definition of program ROM and write it out +// to a new '.v' file associated with the name of the original '.psm' file +// being assembled. +// +// This template can be modified to define alternative memory definitions +// such as dual port. However, you are responsible for ensuring the template +// is correct as the assembler does not perform any checking of the Verilog. +// +// The assembler identifies all text enclosed by {} characters, and replaces +// these character strings. All templates should include these {} character +// strings for the assembler to work correctly. +// +// This template defines a block RAM configured in 1024 x 18-bit single port +// mode and conneceted to act as a single port ROM. +// +//Reference: +// None +//Revision History: +// Rev 1.00 - jc - Converted to verilog, July 2003. +// Rev 1.01 - sus - Added text to confirm to Xilinx HDL std, August 4 2004. +// Rev 1.02 - njs - Added attributes for Synplicity August 5 2004. +// Rev 1.03 - sus - Added text to conform to Xilinx generated +// HDL spec, September 7 2004 +// +//////////////////////////////////////////////////////////////////////////////// +// Contact: e-mail picoblaze@xilinx.com +////////////////////////////////////////////////////////////////////////////////// +// +// Disclaimer: +// LIMITED WARRANTY AND DISCLAIMER. These designs are +// provided to you "as is". Xilinx and its licensors make and you +// receive no warranties or conditions, express, implied, +// statutory or otherwise, and Xilinx specifically disclaims any +// implied warranties of merchantability, non-infringement, or +// fitness for a particular purpose. Xilinx does not warrant that +// the functions contained in these designs will meet your +// requirements, or that the operation of these designs will be +// uninterrupted or error free, or that defects in the Designs +// will be corrected. Furthermore, Xilinx does not warrant or +// make any representations regarding use or the results of the +// use of the designs in terms of correctness, accuracy, +// reliability, or otherwise. +// +// LIMITATION OF LIABILITY. In no event will Xilinx or its +// licensors be liable for any loss of data, lost profits, cost +// or procurement of substitute goods or services, or for any +// special, incidental, consequential, or indirect damages +// arising from the use or operation of the designs or +// accompanying documentation, however caused and on any theory +// of liability. This limitation will apply even if Xilinx +// has been advised of the possibility of such damage. This +// limitation shall apply not-withstanding the failure of the +// essential purpose of any limited remedies herein. +////////////////////////////////////////////////////////////////////////////////// + +The next line is used to determine where the template actually starts and must exist. +{begin template} +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2004 Xilinx, Inc. +// All Rights Reserved +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: v1.30 +// \ \ Application : KCPSM3 +// / / Filename: {name}.v +// /___/ /\ +// \ \ / \ +// \___\/\___\ +// +//Command: kcpsm3 {name}.psm +//Device: Spartan-3, Spartan-3E, Virtex-II, and Virtex-II Pro FPGAs +//Design Name: {name} +//Generated {timestamp}. +//Purpose: +// {name} verilog program definition. +// +//Reference: +// PicoBlaze 8-bit Embedded Microcontroller User Guide +//////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1ps + +module {name} (address, instruction, clk); + +input [9:0] address; +input clk; + +output [17:0] instruction; + +RAMB16_S18 ram_1024_x_18( + .DI (16'h0000), + .DIP (2'b00), + .EN (1'b1), + .WE (1'b0), + .SSR (1'b0), + .CLK (clk), + .ADDR (address), + .DO (instruction[15:0]), + .DOP (instruction[17:16])) +/*synthesis +init_00 = "{INIT_00}" +init_01 = "{INIT_01}" +init_02 = "{INIT_02}" +init_03 = "{INIT_03}" +init_04 = "{INIT_04}" +init_05 = "{INIT_05}" +init_06 = "{INIT_06}" +init_07 = "{INIT_07}" +init_08 = "{INIT_08}" +init_09 = "{INIT_09}" +init_0A = "{INIT_0A}" +init_0B = "{INIT_0B}" +init_0C = "{INIT_0C}" +init_0D = "{INIT_0D}" +init_0E = "{INIT_0E}" +init_0F = "{INIT_0F}" +init_10 = "{INIT_10}" +init_11 = "{INIT_11}" +init_12 = "{INIT_12}" +init_13 = "{INIT_13}" +init_14 = "{INIT_14}" +init_15 = "{INIT_15}" +init_16 = "{INIT_16}" +init_17 = "{INIT_17}" +init_18 = "{INIT_18}" +init_19 = "{INIT_19}" +init_1A = "{INIT_1A}" +init_1B = "{INIT_1B}" +init_1C = "{INIT_1C}" +init_1D = "{INIT_1D}" +init_1E = "{INIT_1E}" +init_1F = "{INIT_1F}" +init_20 = "{INIT_20}" +init_21 = "{INIT_21}" +init_22 = "{INIT_22}" +init_23 = "{INIT_23}" +init_24 = "{INIT_24}" +init_25 = "{INIT_25}" +init_26 = "{INIT_26}" +init_27 = "{INIT_27}" +init_28 = "{INIT_28}" +init_29 = "{INIT_29}" +init_2A = "{INIT_2A}" +init_2B = "{INIT_2B}" +init_2C = "{INIT_2C}" +init_2D = "{INIT_2D}" +init_2E = "{INIT_2E}" +init_2F = "{INIT_2F}" +init_30 = "{INIT_30}" +init_31 = "{INIT_31}" +init_32 = "{INIT_32}" +init_33 = "{INIT_33}" +init_34 = "{INIT_34}" +init_35 = "{INIT_35}" +init_36 = "{INIT_36}" +init_37 = "{INIT_37}" +init_38 = "{INIT_38}" +init_39 = "{INIT_39}" +init_3A = "{INIT_3A}" +init_3B = "{INIT_3B}" +init_3C = "{INIT_3C}" +init_3D = "{INIT_3D}" +init_3E = "{INIT_3E}" +init_3F = "{INIT_3F}" +initp_00 = "{INITP_00}" +initp_01 = "{INITP_01}" +initp_02 = "{INITP_02}" +initp_03 = "{INITP_03}" +initp_04 = "{INITP_04}" +initp_05 = "{INITP_05}" +initp_06 = "{INITP_06}" +initp_07 = "{INITP_07}" */; + +// synthesis translate_off +// Attributes for Simulation +defparam ram_1024_x_18.INIT_00 = 256'h{INIT_00}; +defparam ram_1024_x_18.INIT_01 = 256'h{INIT_01}; +defparam ram_1024_x_18.INIT_02 = 256'h{INIT_02}; +defparam ram_1024_x_18.INIT_03 = 256'h{INIT_03}; +defparam ram_1024_x_18.INIT_04 = 256'h{INIT_04}; +defparam ram_1024_x_18.INIT_05 = 256'h{INIT_05}; +defparam ram_1024_x_18.INIT_06 = 256'h{INIT_06}; +defparam ram_1024_x_18.INIT_07 = 256'h{INIT_07}; +defparam ram_1024_x_18.INIT_08 = 256'h{INIT_08}; +defparam ram_1024_x_18.INIT_09 = 256'h{INIT_09}; +defparam ram_1024_x_18.INIT_0A = 256'h{INIT_0A}; +defparam ram_1024_x_18.INIT_0B = 256'h{INIT_0B}; +defparam ram_1024_x_18.INIT_0C = 256'h{INIT_0C}; +defparam ram_1024_x_18.INIT_0D = 256'h{INIT_0D}; +defparam ram_1024_x_18.INIT_0E = 256'h{INIT_0E}; +defparam ram_1024_x_18.INIT_0F = 256'h{INIT_0F}; +defparam ram_1024_x_18.INIT_10 = 256'h{INIT_10}; +defparam ram_1024_x_18.INIT_11 = 256'h{INIT_11}; +defparam ram_1024_x_18.INIT_12 = 256'h{INIT_12}; +defparam ram_1024_x_18.INIT_13 = 256'h{INIT_13}; +defparam ram_1024_x_18.INIT_14 = 256'h{INIT_14}; +defparam ram_1024_x_18.INIT_15 = 256'h{INIT_15}; +defparam ram_1024_x_18.INIT_16 = 256'h{INIT_16}; +defparam ram_1024_x_18.INIT_17 = 256'h{INIT_17}; +defparam ram_1024_x_18.INIT_18 = 256'h{INIT_18}; +defparam ram_1024_x_18.INIT_19 = 256'h{INIT_19}; +defparam ram_1024_x_18.INIT_1A = 256'h{INIT_1A}; +defparam ram_1024_x_18.INIT_1B = 256'h{INIT_1B}; +defparam ram_1024_x_18.INIT_1C = 256'h{INIT_1C}; +defparam ram_1024_x_18.INIT_1D = 256'h{INIT_1D}; +defparam ram_1024_x_18.INIT_1E = 256'h{INIT_1E}; +defparam ram_1024_x_18.INIT_1F = 256'h{INIT_1F}; +defparam ram_1024_x_18.INIT_20 = 256'h{INIT_20}; +defparam ram_1024_x_18.INIT_21 = 256'h{INIT_21}; +defparam ram_1024_x_18.INIT_22 = 256'h{INIT_22}; +defparam ram_1024_x_18.INIT_23 = 256'h{INIT_23}; +defparam ram_1024_x_18.INIT_24 = 256'h{INIT_24}; +defparam ram_1024_x_18.INIT_25 = 256'h{INIT_25}; +defparam ram_1024_x_18.INIT_26 = 256'h{INIT_26}; +defparam ram_1024_x_18.INIT_27 = 256'h{INIT_27}; +defparam ram_1024_x_18.INIT_28 = 256'h{INIT_28}; +defparam ram_1024_x_18.INIT_29 = 256'h{INIT_29}; +defparam ram_1024_x_18.INIT_2A = 256'h{INIT_2A}; +defparam ram_1024_x_18.INIT_2B = 256'h{INIT_2B}; +defparam ram_1024_x_18.INIT_2C = 256'h{INIT_2C}; +defparam ram_1024_x_18.INIT_2D = 256'h{INIT_2D}; +defparam ram_1024_x_18.INIT_2E = 256'h{INIT_2E}; +defparam ram_1024_x_18.INIT_2F = 256'h{INIT_2F}; +defparam ram_1024_x_18.INIT_30 = 256'h{INIT_30}; +defparam ram_1024_x_18.INIT_31 = 256'h{INIT_31}; +defparam ram_1024_x_18.INIT_32 = 256'h{INIT_32}; +defparam ram_1024_x_18.INIT_33 = 256'h{INIT_33}; +defparam ram_1024_x_18.INIT_34 = 256'h{INIT_34}; +defparam ram_1024_x_18.INIT_35 = 256'h{INIT_35}; +defparam ram_1024_x_18.INIT_36 = 256'h{INIT_36}; +defparam ram_1024_x_18.INIT_37 = 256'h{INIT_37}; +defparam ram_1024_x_18.INIT_38 = 256'h{INIT_38}; +defparam ram_1024_x_18.INIT_39 = 256'h{INIT_39}; +defparam ram_1024_x_18.INIT_3A = 256'h{INIT_3A}; +defparam ram_1024_x_18.INIT_3B = 256'h{INIT_3B}; +defparam ram_1024_x_18.INIT_3C = 256'h{INIT_3C}; +defparam ram_1024_x_18.INIT_3D = 256'h{INIT_3D}; +defparam ram_1024_x_18.INIT_3E = 256'h{INIT_3E}; +defparam ram_1024_x_18.INIT_3F = 256'h{INIT_3F}; +defparam ram_1024_x_18.INITP_00 = 256'h{INITP_00}; +defparam ram_1024_x_18.INITP_01 = 256'h{INITP_01}; +defparam ram_1024_x_18.INITP_02 = 256'h{INITP_02}; +defparam ram_1024_x_18.INITP_03 = 256'h{INITP_03}; +defparam ram_1024_x_18.INITP_04 = 256'h{INITP_04}; +defparam ram_1024_x_18.INITP_05 = 256'h{INITP_05}; +defparam ram_1024_x_18.INITP_06 = 256'h{INITP_06}; +defparam ram_1024_x_18.INITP_07 = 256'h{INITP_07}; + +// synthesis translate_on +// Attributes for XST (Synplicity attributes are in-line) +// synthesis attribute INIT_00 of ram_1024_x_18 is "{INIT_00}" +// synthesis attribute INIT_01 of ram_1024_x_18 is "{INIT_01}" +// synthesis attribute INIT_02 of ram_1024_x_18 is "{INIT_02}" +// synthesis attribute INIT_03 of ram_1024_x_18 is "{INIT_03}" +// synthesis attribute INIT_04 of ram_1024_x_18 is "{INIT_04}" +// synthesis attribute INIT_05 of ram_1024_x_18 is "{INIT_05}" +// synthesis attribute INIT_06 of ram_1024_x_18 is "{INIT_06}" +// synthesis attribute INIT_07 of ram_1024_x_18 is "{INIT_07}" +// synthesis attribute INIT_08 of ram_1024_x_18 is "{INIT_08}" +// synthesis attribute INIT_09 of ram_1024_x_18 is "{INIT_09}" +// synthesis attribute INIT_0A of ram_1024_x_18 is "{INIT_0A}" +// synthesis attribute INIT_0B of ram_1024_x_18 is "{INIT_0B}" +// synthesis attribute INIT_0C of ram_1024_x_18 is "{INIT_0C}" +// synthesis attribute INIT_0D of ram_1024_x_18 is "{INIT_0D}" +// synthesis attribute INIT_0E of ram_1024_x_18 is "{INIT_0E}" +// synthesis attribute INIT_0F of ram_1024_x_18 is "{INIT_0F}" +// synthesis attribute INIT_10 of ram_1024_x_18 is "{INIT_10}" +// synthesis attribute INIT_11 of ram_1024_x_18 is "{INIT_11}" +// synthesis attribute INIT_12 of ram_1024_x_18 is "{INIT_12}" +// synthesis attribute INIT_13 of ram_1024_x_18 is "{INIT_13}" +// synthesis attribute INIT_14 of ram_1024_x_18 is "{INIT_14}" +// synthesis attribute INIT_15 of ram_1024_x_18 is "{INIT_15}" +// synthesis attribute INIT_16 of ram_1024_x_18 is "{INIT_16}" +// synthesis attribute INIT_17 of ram_1024_x_18 is "{INIT_17}" +// synthesis attribute INIT_18 of ram_1024_x_18 is "{INIT_18}" +// synthesis attribute INIT_19 of ram_1024_x_18 is "{INIT_19}" +// synthesis attribute INIT_1A of ram_1024_x_18 is "{INIT_1A}" +// synthesis attribute INIT_1B of ram_1024_x_18 is "{INIT_1B}" +// synthesis attribute INIT_1C of ram_1024_x_18 is "{INIT_1C}" +// synthesis attribute INIT_1D of ram_1024_x_18 is "{INIT_1D}" +// synthesis attribute INIT_1E of ram_1024_x_18 is "{INIT_1E}" +// synthesis attribute INIT_1F of ram_1024_x_18 is "{INIT_1F}" +// synthesis attribute INIT_20 of ram_1024_x_18 is "{INIT_20}" +// synthesis attribute INIT_21 of ram_1024_x_18 is "{INIT_21}" +// synthesis attribute INIT_22 of ram_1024_x_18 is "{INIT_22}" +// synthesis attribute INIT_23 of ram_1024_x_18 is "{INIT_23}" +// synthesis attribute INIT_24 of ram_1024_x_18 is "{INIT_24}" +// synthesis attribute INIT_25 of ram_1024_x_18 is "{INIT_25}" +// synthesis attribute INIT_26 of ram_1024_x_18 is "{INIT_26}" +// synthesis attribute INIT_27 of ram_1024_x_18 is "{INIT_27}" +// synthesis attribute INIT_28 of ram_1024_x_18 is "{INIT_28}" +// synthesis attribute INIT_29 of ram_1024_x_18 is "{INIT_29}" +// synthesis attribute INIT_2A of ram_1024_x_18 is "{INIT_2A}" +// synthesis attribute INIT_2B of ram_1024_x_18 is "{INIT_2B}" +// synthesis attribute INIT_2C of ram_1024_x_18 is "{INIT_2C}" +// synthesis attribute INIT_2D of ram_1024_x_18 is "{INIT_2D}" +// synthesis attribute INIT_2E of ram_1024_x_18 is "{INIT_2E}" +// synthesis attribute INIT_2F of ram_1024_x_18 is "{INIT_2F}" +// synthesis attribute INIT_30 of ram_1024_x_18 is "{INIT_30}" +// synthesis attribute INIT_31 of ram_1024_x_18 is "{INIT_31}" +// synthesis attribute INIT_32 of ram_1024_x_18 is "{INIT_32}" +// synthesis attribute INIT_33 of ram_1024_x_18 is "{INIT_33}" +// synthesis attribute INIT_34 of ram_1024_x_18 is "{INIT_34}" +// synthesis attribute INIT_35 of ram_1024_x_18 is "{INIT_35}" +// synthesis attribute INIT_36 of ram_1024_x_18 is "{INIT_36}" +// synthesis attribute INIT_37 of ram_1024_x_18 is "{INIT_37}" +// synthesis attribute INIT_38 of ram_1024_x_18 is "{INIT_38}" +// synthesis attribute INIT_39 of ram_1024_x_18 is "{INIT_39}" +// synthesis attribute INIT_3A of ram_1024_x_18 is "{INIT_3A}" +// synthesis attribute INIT_3B of ram_1024_x_18 is "{INIT_3B}" +// synthesis attribute INIT_3C of ram_1024_x_18 is "{INIT_3C}" +// synthesis attribute INIT_3D of ram_1024_x_18 is "{INIT_3D}" +// synthesis attribute INIT_3E of ram_1024_x_18 is "{INIT_3E}" +// synthesis attribute INIT_3F of ram_1024_x_18 is "{INIT_3F}" +// synthesis attribute INITP_00 of ram_1024_x_18 is "{INITP_00}" +// synthesis attribute INITP_01 of ram_1024_x_18 is "{INITP_01}" +// synthesis attribute INITP_02 of ram_1024_x_18 is "{INITP_02}" +// synthesis attribute INITP_03 of ram_1024_x_18 is "{INITP_03}" +// synthesis attribute INITP_04 of ram_1024_x_18 is "{INITP_04}" +// synthesis attribute INITP_05 of ram_1024_x_18 is "{INITP_05}" +// synthesis attribute INITP_06 of ram_1024_x_18 is "{INITP_06}" +// synthesis attribute INITP_07 of ram_1024_x_18 is "{INITP_07}" + +endmodule + +// END OF FILE {name}.v \ No newline at end of file diff --git a/ROM_form.vhd b/ROM_form.vhd new file mode 100755 index 0000000..6b1ce36 --- /dev/null +++ b/ROM_form.vhd @@ -0,0 +1,305 @@ +ROM_form.vhd + +Ken Chapman (Xilinx Ltd) July 2003 + +This is the VHDL template file for the KCPSM3 assembler. +It is used to configure a Spartan-3, Virtex-II or Virtex-IIPRO block RAM to act as +a single port program ROM. + +This VHDL file is not valid as input directly into a synthesis or simulation tool. +The assembler will read this template and insert the data required to complete the +definition of program ROM and write it out to a new '.vhd' file associated with the +name of the original '.psm' file being assembled. + +This template can be modified to define alternative memory definitions such as dual port. +However, you are responsible for ensuring the template is correct as the assembler does +not perform any checking of the VHDL. + +The assembler identifies all text enclosed by {} characters, and replaces these +character strings. All templates should include these {} character strings for +the assembler to work correctly. + +**************************************************************************************** + +This template defines a block RAM configured in 1024 x 18-bit single port mode and +conneceted to act as a single port ROM. + +**************************************************************************************** + +The next line is used to determine where the template actually starts and must exist. +{begin template} +-- +-- Definition of a single port ROM for KCPSM3 program defined by {name}.psm +-- +-- Generated by KCPSM3 Assembler {timestamp}. +-- +-- Standard IEEE libraries +-- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +-- +-- The Unisim Library is used to define Xilinx primitives. It is also used during +-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd +-- +library unisim; +use unisim.vcomponents.all; +-- +-- +entity {name} is + Port ( address : in std_logic_vector(9 downto 0); + instruction : out std_logic_vector(17 downto 0); + clk : in std_logic); + end {name}; +-- +architecture low_level_definition of {name} is +-- +-- Attributes to define ROM contents during implementation synthesis. +-- The information is repeated in the generic map for functional simulation +-- +attribute INIT_00 : string; +attribute INIT_01 : string; +attribute INIT_02 : string; +attribute INIT_03 : string; +attribute INIT_04 : string; +attribute INIT_05 : string; +attribute INIT_06 : string; +attribute INIT_07 : string; +attribute INIT_08 : string; +attribute INIT_09 : string; +attribute INIT_0A : string; +attribute INIT_0B : string; +attribute INIT_0C : string; +attribute INIT_0D : string; +attribute INIT_0E : string; +attribute INIT_0F : string; +attribute INIT_10 : string; +attribute INIT_11 : string; +attribute INIT_12 : string; +attribute INIT_13 : string; +attribute INIT_14 : string; +attribute INIT_15 : string; +attribute INIT_16 : string; +attribute INIT_17 : string; +attribute INIT_18 : string; +attribute INIT_19 : string; +attribute INIT_1A : string; +attribute INIT_1B : string; +attribute INIT_1C : string; +attribute INIT_1D : string; +attribute INIT_1E : string; +attribute INIT_1F : string; +attribute INIT_20 : string; +attribute INIT_21 : string; +attribute INIT_22 : string; +attribute INIT_23 : string; +attribute INIT_24 : string; +attribute INIT_25 : string; +attribute INIT_26 : string; +attribute INIT_27 : string; +attribute INIT_28 : string; +attribute INIT_29 : string; +attribute INIT_2A : string; +attribute INIT_2B : string; +attribute INIT_2C : string; +attribute INIT_2D : string; +attribute INIT_2E : string; +attribute INIT_2F : string; +attribute INIT_30 : string; +attribute INIT_31 : string; +attribute INIT_32 : string; +attribute INIT_33 : string; +attribute INIT_34 : string; +attribute INIT_35 : string; +attribute INIT_36 : string; +attribute INIT_37 : string; +attribute INIT_38 : string; +attribute INIT_39 : string; +attribute INIT_3A : string; +attribute INIT_3B : string; +attribute INIT_3C : string; +attribute INIT_3D : string; +attribute INIT_3E : string; +attribute INIT_3F : string; +attribute INITP_00 : string; +attribute INITP_01 : string; +attribute INITP_02 : string; +attribute INITP_03 : string; +attribute INITP_04 : string; +attribute INITP_05 : string; +attribute INITP_06 : string; +attribute INITP_07 : string; +-- +-- Attributes to define ROM contents during implementation synthesis. +-- +attribute INIT_00 of ram_1024_x_18 : label is "{INIT_00}"; +attribute INIT_01 of ram_1024_x_18 : label is "{INIT_01}"; +attribute INIT_02 of ram_1024_x_18 : label is "{INIT_02}"; +attribute INIT_03 of ram_1024_x_18 : label is "{INIT_03}"; +attribute INIT_04 of ram_1024_x_18 : label is "{INIT_04}"; +attribute INIT_05 of ram_1024_x_18 : label is "{INIT_05}"; +attribute INIT_06 of ram_1024_x_18 : label is "{INIT_06}"; +attribute INIT_07 of ram_1024_x_18 : label is "{INIT_07}"; +attribute INIT_08 of ram_1024_x_18 : label is "{INIT_08}"; +attribute INIT_09 of ram_1024_x_18 : label is "{INIT_09}"; +attribute INIT_0A of ram_1024_x_18 : label is "{INIT_0A}"; +attribute INIT_0B of ram_1024_x_18 : label is "{INIT_0B}"; +attribute INIT_0C of ram_1024_x_18 : label is "{INIT_0C}"; +attribute INIT_0D of ram_1024_x_18 : label is "{INIT_0D}"; +attribute INIT_0E of ram_1024_x_18 : label is "{INIT_0E}"; +attribute INIT_0F of ram_1024_x_18 : label is "{INIT_0F}"; +attribute INIT_10 of ram_1024_x_18 : label is "{INIT_10}"; +attribute INIT_11 of ram_1024_x_18 : label is "{INIT_11}"; +attribute INIT_12 of ram_1024_x_18 : label is "{INIT_12}"; +attribute INIT_13 of ram_1024_x_18 : label is "{INIT_13}"; +attribute INIT_14 of ram_1024_x_18 : label is "{INIT_14}"; +attribute INIT_15 of ram_1024_x_18 : label is "{INIT_15}"; +attribute INIT_16 of ram_1024_x_18 : label is "{INIT_16}"; +attribute INIT_17 of ram_1024_x_18 : label is "{INIT_17}"; +attribute INIT_18 of ram_1024_x_18 : label is "{INIT_18}"; +attribute INIT_19 of ram_1024_x_18 : label is "{INIT_19}"; +attribute INIT_1A of ram_1024_x_18 : label is "{INIT_1A}"; +attribute INIT_1B of ram_1024_x_18 : label is "{INIT_1B}"; +attribute INIT_1C of ram_1024_x_18 : label is "{INIT_1C}"; +attribute INIT_1D of ram_1024_x_18 : label is "{INIT_1D}"; +attribute INIT_1E of ram_1024_x_18 : label is "{INIT_1E}"; +attribute INIT_1F of ram_1024_x_18 : label is "{INIT_1F}"; +attribute INIT_20 of ram_1024_x_18 : label is "{INIT_20}"; +attribute INIT_21 of ram_1024_x_18 : label is "{INIT_21}"; +attribute INIT_22 of ram_1024_x_18 : label is "{INIT_22}"; +attribute INIT_23 of ram_1024_x_18 : label is "{INIT_23}"; +attribute INIT_24 of ram_1024_x_18 : label is "{INIT_24}"; +attribute INIT_25 of ram_1024_x_18 : label is "{INIT_25}"; +attribute INIT_26 of ram_1024_x_18 : label is "{INIT_26}"; +attribute INIT_27 of ram_1024_x_18 : label is "{INIT_27}"; +attribute INIT_28 of ram_1024_x_18 : label is "{INIT_28}"; +attribute INIT_29 of ram_1024_x_18 : label is "{INIT_29}"; +attribute INIT_2A of ram_1024_x_18 : label is "{INIT_2A}"; +attribute INIT_2B of ram_1024_x_18 : label is "{INIT_2B}"; +attribute INIT_2C of ram_1024_x_18 : label is "{INIT_2C}"; +attribute INIT_2D of ram_1024_x_18 : label is "{INIT_2D}"; +attribute INIT_2E of ram_1024_x_18 : label is "{INIT_2E}"; +attribute INIT_2F of ram_1024_x_18 : label is "{INIT_2F}"; +attribute INIT_30 of ram_1024_x_18 : label is "{INIT_30}"; +attribute INIT_31 of ram_1024_x_18 : label is "{INIT_31}"; +attribute INIT_32 of ram_1024_x_18 : label is "{INIT_32}"; +attribute INIT_33 of ram_1024_x_18 : label is "{INIT_33}"; +attribute INIT_34 of ram_1024_x_18 : label is "{INIT_34}"; +attribute INIT_35 of ram_1024_x_18 : label is "{INIT_35}"; +attribute INIT_36 of ram_1024_x_18 : label is "{INIT_36}"; +attribute INIT_37 of ram_1024_x_18 : label is "{INIT_37}"; +attribute INIT_38 of ram_1024_x_18 : label is "{INIT_38}"; +attribute INIT_39 of ram_1024_x_18 : label is "{INIT_39}"; +attribute INIT_3A of ram_1024_x_18 : label is "{INIT_3A}"; +attribute INIT_3B of ram_1024_x_18 : label is "{INIT_3B}"; +attribute INIT_3C of ram_1024_x_18 : label is "{INIT_3C}"; +attribute INIT_3D of ram_1024_x_18 : label is "{INIT_3D}"; +attribute INIT_3E of ram_1024_x_18 : label is "{INIT_3E}"; +attribute INIT_3F of ram_1024_x_18 : label is "{INIT_3F}"; +attribute INITP_00 of ram_1024_x_18 : label is "{INITP_00}"; +attribute INITP_01 of ram_1024_x_18 : label is "{INITP_01}"; +attribute INITP_02 of ram_1024_x_18 : label is "{INITP_02}"; +attribute INITP_03 of ram_1024_x_18 : label is "{INITP_03}"; +attribute INITP_04 of ram_1024_x_18 : label is "{INITP_04}"; +attribute INITP_05 of ram_1024_x_18 : label is "{INITP_05}"; +attribute INITP_06 of ram_1024_x_18 : label is "{INITP_06}"; +attribute INITP_07 of ram_1024_x_18 : label is "{INITP_07}"; +-- +begin +-- + --Instantiate the Xilinx primitive for a block RAM + ram_1024_x_18: RAMB16_S18 + --synthesis translate_off + --INIT values repeated to define contents for functional simulation + generic map ( INIT_00 => X"{INIT_00}", + INIT_01 => X"{INIT_01}", + INIT_02 => X"{INIT_02}", + INIT_03 => X"{INIT_03}", + INIT_04 => X"{INIT_04}", + INIT_05 => X"{INIT_05}", + INIT_06 => X"{INIT_06}", + INIT_07 => X"{INIT_07}", + INIT_08 => X"{INIT_08}", + INIT_09 => X"{INIT_09}", + INIT_0A => X"{INIT_0A}", + INIT_0B => X"{INIT_0B}", + INIT_0C => X"{INIT_0C}", + INIT_0D => X"{INIT_0D}", + INIT_0E => X"{INIT_0E}", + INIT_0F => X"{INIT_0F}", + INIT_10 => X"{INIT_10}", + INIT_11 => X"{INIT_11}", + INIT_12 => X"{INIT_12}", + INIT_13 => X"{INIT_13}", + INIT_14 => X"{INIT_14}", + INIT_15 => X"{INIT_15}", + INIT_16 => X"{INIT_16}", + INIT_17 => X"{INIT_17}", + INIT_18 => X"{INIT_18}", + INIT_19 => X"{INIT_19}", + INIT_1A => X"{INIT_1A}", + INIT_1B => X"{INIT_1B}", + INIT_1C => X"{INIT_1C}", + INIT_1D => X"{INIT_1D}", + INIT_1E => X"{INIT_1E}", + INIT_1F => X"{INIT_1F}", + INIT_20 => X"{INIT_20}", + INIT_21 => X"{INIT_21}", + INIT_22 => X"{INIT_22}", + INIT_23 => X"{INIT_23}", + INIT_24 => X"{INIT_24}", + INIT_25 => X"{INIT_25}", + INIT_26 => X"{INIT_26}", + INIT_27 => X"{INIT_27}", + INIT_28 => X"{INIT_28}", + INIT_29 => X"{INIT_29}", + INIT_2A => X"{INIT_2A}", + INIT_2B => X"{INIT_2B}", + INIT_2C => X"{INIT_2C}", + INIT_2D => X"{INIT_2D}", + INIT_2E => X"{INIT_2E}", + INIT_2F => X"{INIT_2F}", + INIT_30 => X"{INIT_30}", + INIT_31 => X"{INIT_31}", + INIT_32 => X"{INIT_32}", + INIT_33 => X"{INIT_33}", + INIT_34 => X"{INIT_34}", + INIT_35 => X"{INIT_35}", + INIT_36 => X"{INIT_36}", + INIT_37 => X"{INIT_37}", + INIT_38 => X"{INIT_38}", + INIT_39 => X"{INIT_39}", + INIT_3A => X"{INIT_3A}", + INIT_3B => X"{INIT_3B}", + INIT_3C => X"{INIT_3C}", + INIT_3D => X"{INIT_3D}", + INIT_3E => X"{INIT_3E}", + INIT_3F => X"{INIT_3F}", + INITP_00 => X"{INITP_00}", + INITP_01 => X"{INITP_01}", + INITP_02 => X"{INITP_02}", + INITP_03 => X"{INITP_03}", + INITP_04 => X"{INITP_04}", + INITP_05 => X"{INITP_05}", + INITP_06 => X"{INITP_06}", + INITP_07 => X"{INITP_07}") + --synthesis translate_on + port map( DI => "0000000000000000", + DIP => "00", + EN => '1', + WE => '0', + SSR => '0', + CLK => clk, + ADDR => address, + DO => instruction(15 downto 0), + DOP => instruction(17 downto 16)); +-- +end low_level_definition; +-- +------------------------------------------------------------------------------------ +-- +-- END OF FILE {name}.vhd +-- +------------------------------------------------------------------------------------ + diff --git a/T80.vhd b/T80.vhd new file mode 100755 index 0000000..398fa0d --- /dev/null +++ b/T80.vhd @@ -0,0 +1,1073 @@ +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 and Auto_Wait_t1 = '0' then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusB <= "--------"; + end case; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if T_Res = '1' then + Auto_Wait_t1 <= '0'; + else + Auto_Wait_t1 <= Auto_Wait or IORQ_i; + end if; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if (Auto_Wait = '1' and Auto_Wait_t2 = '0') nor + (IOWait = 1 and IORQ_i = '1' and Auto_Wait_t1 = '0') then + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/T80_ALU.vhd b/T80_ALU.vhd new file mode 100755 index 0000000..86fddce --- /dev/null +++ b/T80_ALU.vhd @@ -0,0 +1,351 @@ +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + OverFlow_v <= Carry_v xor Carry7_v; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; + +end; diff --git a/T80_MCode.vhd b/T80_MCode.vhd new file mode 100755 index 0000000..4cc30f3 --- /dev/null +++ b/T80_MCode.vhd @@ -0,0 +1,1934 @@ +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; +-- constant aNone : std_logic_vector(2 downto 0) := "000"; +-- constant aXY : std_logic_vector(2 downto 0) := "001"; +-- constant aIOA : std_logic_vector(2 downto 0) := "010"; +-- constant aSP : std_logic_vector(2 downto 0) := "011"; +-- constant aBC : std_logic_vector(2 downto 0) := "100"; +-- constant aDE : std_logic_vector(2 downto 0) := "101"; +-- constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0010"; + else + IncDec_16 <= "1010"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0010"; + else + IncDec_16 <= "1010"; + end if; + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/T80_Pack.vhd b/T80_Pack.vhd new file mode 100755 index 0000000..ac7d34d --- /dev/null +++ b/T80_Pack.vhd @@ -0,0 +1,208 @@ +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/T80_Reg.vhd b/T80_Reg.vhd new file mode 100755 index 0000000..828485f --- /dev/null +++ b/T80_Reg.vhd @@ -0,0 +1,105 @@ +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/T80_RegX.vhd b/T80_RegX.vhd new file mode 100755 index 0000000..4d89bae --- /dev/null +++ b/T80_RegX.vhd @@ -0,0 +1,170 @@ +-- +-- T80 Registers for Xilinx Select RAM +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Removed UNISIM library and added componet declaration +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +library UNISIM; +use UNISIM.VComponents.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + +-- component RAM16X1D +-- port( +-- DPO : out std_ulogic; +-- SPO : out std_ulogic; +-- A0 : in std_ulogic; +-- A1 : in std_ulogic; +-- A2 : in std_ulogic; +-- A3 : in std_ulogic; +-- D : in std_ulogic; +-- DPRA0 : in std_ulogic; +-- DPRA1 : in std_ulogic; +-- DPRA2 : in std_ulogic; +-- DPRA3 : in std_ulogic; +-- WCLK : in std_ulogic; +-- WE : in std_ulogic); +-- end component; + + signal ENH : std_logic; + signal ENL : std_logic; + +begin + + ENH <= CEN and WEH; + ENL <= CEN and WEL; + + bG1: for I in 0 to 7 generate + begin + Reg1H : RAM16X1D + port map( + DPO => DOBH(i), + SPO => DOAH(i), + A0 => AddrA(0), + A1 => AddrA(1), + A2 => AddrA(2), + A3 => '0', + D => DIH(i), + DPRA0 => AddrB(0), + DPRA1 => AddrB(1), + DPRA2 => AddrB(2), + DPRA3 => '0', + WCLK => Clk, + WE => ENH); + Reg1L : RAM16X1D + port map( + DPO => DOBL(i), + SPO => DOAL(i), + A0 => AddrA(0), + A1 => AddrA(1), + A2 => AddrA(2), + A3 => '0', + D => DIL(i), + DPRA0 => AddrB(0), + DPRA1 => AddrB(1), + DPRA2 => AddrB(2), + DPRA3 => '0', + WCLK => Clk, + WE => ENL); + Reg2H : RAM16X1D + port map( + DPO => DOCH(i), + SPO => open, + A0 => AddrA(0), + A1 => AddrA(1), + A2 => AddrA(2), + A3 => '0', + D => DIH(i), + DPRA0 => AddrC(0), + DPRA1 => AddrC(1), + DPRA2 => AddrC(2), + DPRA3 => '0', + WCLK => Clk, + WE => ENH); + Reg2L : RAM16X1D + port map( + DPO => DOCL(i), + SPO => open, + A0 => AddrA(0), + A1 => AddrA(1), + A2 => AddrA(2), + A3 => '0', + D => DIL(i), + DPRA0 => AddrC(0), + DPRA1 => AddrC(1), + DPRA2 => AddrC(2), + DPRA3 => '0', + WCLK => Clk, + WE => ENL); + end generate; + +end; diff --git a/T80a.vhd b/T80a.vhd new file mode 100755 index 0000000..dc1e899 --- /dev/null +++ b/T80a.vhd @@ -0,0 +1,255 @@ +-- +-- Z80 compatible microprocessor core, asynchronous top level +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed interrupt cycle +-- +-- 0235 : Updated for T80 interface change +-- +-- 0238 : Updated for T80 interface change +-- +-- 0240 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80a is + generic( + Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DIN : in std_logic_vector(7 downto 0); + DOUT : out std_logic_vector(7 downto 0) + ); +end T80a; + +architecture rtl of T80a is + + signal CEN : std_logic; + signal Reset_s : std_logic; + signal IntCycle_n : std_logic; + signal IORQ : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal MREQ : std_logic; + signal MReq_Inhibit : std_logic; + signal Req_Inhibit : std_logic; + signal RD : std_logic; + signal MREQ_n_i : std_logic; + signal IORQ_n_i : std_logic; + signal RD_n_i : std_logic; + signal WR_n_i : std_logic; + signal RFSH_n_i : std_logic; + signal BUSAK_n_i : std_logic; + signal A_i : std_logic_vector(15 downto 0); + signal DO : std_logic_vector(7 downto 0); + signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser + signal Wait_s : std_logic; + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + +begin + + CEN <= '1'; + + BUSAK_n <= BUSAK_n_i; + MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit); + RD_n_i <= not RD or Req_Inhibit; + + MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z'; + IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z'; + RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z'; + WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z'; + RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z'; + A <= A_i when BUSAK_n_i = '1' else (others => 'Z'); +-- D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z'); + DOUT <= DO; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + Reset_s <= '0'; + elsif CLK_n'event and CLK_n = '1' then + Reset_s <= '1'; + end if; + end process; + + u0 : T80 + generic map( + Mode => Mode, + IOWait => 1) + port map( + CEN => CEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n_i, + HALT_n => HALT_n, + WAIT_n => Wait_s, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => Reset_s, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n_i, + CLK_n => CLK_n, + A => A_i, + DInst => DIN, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (CLK_n) + begin + if CLK_n'event and CLK_n = '0' then + Wait_s <= WAIT_n; + if TState = "011" and BUSAK_n_i = '1' then + DI_Reg <= DIN; + end if; + end if; + end process; + + process (Reset_s,CLK_n) + begin + if Reset_s = '0' then + WR_n_i <= '1'; + elsif CLK_n'event and CLK_n = '1' then + WR_n_i <= '1'; + if TState = "001" then -- To short for IO writes !!!!!!!!!!!!!!!!!!! + WR_n_i <= not Write; + end if; + end if; + end process; + + process (Reset_s,CLK_n) + begin + if Reset_s = '0' then + Req_Inhibit <= '0'; + elsif CLK_n'event and CLK_n = '1' then + if MCycle = "001" and TState = "010" then + Req_Inhibit <= '1'; + else + Req_Inhibit <= '0'; + end if; + end if; + end process; + + process (Reset_s,CLK_n) + begin + if Reset_s = '0' then + MReq_Inhibit <= '0'; + elsif CLK_n'event and CLK_n = '0' then + if MCycle = "001" and TState = "010" then + MReq_Inhibit <= '1'; + else + MReq_Inhibit <= '0'; + end if; + end if; + end process; + + process(Reset_s,CLK_n) + begin + if Reset_s = '0' then + RD <= '0'; + IORQ_n_i <= '1'; + MREQ <= '0'; + elsif CLK_n'event and CLK_n = '0' then + + if MCycle = "001" then + if TState = "001" then + RD <= IntCycle_n; + MREQ <= IntCycle_n; + IORQ_n_i <= IntCycle_n; + end if; + if TState = "011" then + RD <= '0'; + IORQ_n_i <= '1'; + MREQ <= '1'; + end if; + if TState = "100" then + MREQ <= '0'; + end if; + else + if TState = "001" and NoRead = '0' then + RD <= not Write; + IORQ_n_i <= not IORQ; + MREQ <= not IORQ; + end if; + if TState = "011" then + RD <= '0'; + IORQ_n_i <= '1'; + MREQ <= '0'; + end if; + end if; + end if; + end process; + +end; diff --git a/T80s.vhd b/T80s.vhd new file mode 100755 index 0000000..5b61211 --- /dev/null +++ b/T80s.vhd @@ -0,0 +1,190 @@ +-- +-- Z80 compatible microprocessor core, synchronous top level +-- Different timing than the original z80 +-- Inputs needs to be synchronous and outputs may glitch +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed read with wait +-- +-- 0211 : Fixed interrupt cycle +-- +-- 0235 : Updated for T80 interface change +-- +-- 0236 : Added T2Write generic +-- +-- 0237 : Fixed T2Write with wait state +-- +-- 0238 : Updated for T80 interface change +-- +-- 0240 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80s is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + T2Write : integer := 0; -- 0 => WR_n active in T3, /=0 => WR_n active in T2 + IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T80s; + +architecture rtl of T80s is + + signal CEN : std_logic; + signal IntCycle_n : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal IORQ : std_logic; + signal DI_Reg : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + +begin + + CEN <= '1'; + + u0 : T80 + generic map( + Mode => Mode, + IOWait => IOWait) + port map( + CEN => CEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + WAIT_n => Wait_n, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => RESET_n, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n, + CLK_n => CLK_n, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK_n'event and CLK_n = '1' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and Wait_n = '0') then + RD_n <= not IntCycle_n; + MREQ_n <= not IntCycle_n; + IORQ_n <= IntCycle_n; + end if; + if TState = "011" then + MREQ_n <= '0'; + end if; + else + if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then + RD_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + if T2Write = 0 then + if TState = "010" and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + else + if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + end if; + end if; + if TState = "010" and Wait_n = '1' then + DI_Reg <= DI; + end if; + end if; + end process; + +end; diff --git a/T80se.vhd b/T80se.vhd new file mode 100755 index 0000000..ac8886a --- /dev/null +++ b/T80se.vhd @@ -0,0 +1,184 @@ +-- +-- Z80 compatible microprocessor core, synchronous top level with clock enable +-- Different timing than the original z80 +-- Inputs needs to be synchronous and outputs may glitch +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0235 : First release +-- +-- 0236 : Added T2Write generic +-- +-- 0237 : Fixed T2Write with wait state +-- +-- 0238 : Updated for T80 interface change +-- +-- 0240 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80se is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + T2Write : integer := 0; -- 0 => WR_n active in T3, /=0 => WR_n active in T2 + IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CLKEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T80se; + +architecture rtl of T80se is + + signal IntCycle_n : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal IORQ : std_logic; + signal DI_Reg : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + +begin + + u0 : T80 + generic map( + Mode => Mode, + IOWait => IOWait) + port map( + CEN => CLKEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + WAIT_n => Wait_n, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => RESET_n, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n, + CLK_n => CLK_n, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK_n'event and CLK_n = '1' then + if CLKEN = '1' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and Wait_n = '0') then + RD_n <= not IntCycle_n; + MREQ_n <= not IntCycle_n; + IORQ_n <= IntCycle_n; + end if; + if TState = "011" then + MREQ_n <= '0'; + end if; + else + if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then + RD_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + if T2Write = 0 then + if TState = "010" and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + else + if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + end if; + end if; + if TState = "010" and Wait_n = '1' then + DI_Reg <= DI; + end if; + end if; + end if; + end process; + +end; diff --git a/coregen/basic_rom.mif b/coregen/basic_rom.mif new file mode 100755 index 0000000..c643a59 --- /dev/null +++ b/coregen/basic_rom.mif @@ -0,0 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0, + c_has_regcea => 0, + c_mem_type => 3, + c_prim_type => 1, + c_sinita_val => "0", + c_read_width_b => 8, + c_family => "spartan3", + c_read_width_a => 8, + c_disable_warn_bhv_coll => 0, + c_write_mode_b => "WRITE_FIRST", + c_init_file_name => "basic_rom.mif", + c_write_mode_a => "WRITE_FIRST", + c_mux_pipeline_stages => 0, + c_has_mem_output_regs_b => 0, + c_load_init_file => 1, + c_xdevicefamily => "spartan3a", + c_has_mem_output_regs_a => 0, + c_write_depth_b => 8192, + c_write_depth_a => 8192, + c_has_ssrb => 0, + c_has_mux_output_regs_b => 0, + c_has_ssra => 0, + c_has_mux_output_regs_a => 0, + c_addra_width => 13, + c_addrb_width => 13, + c_default_data => "0", + c_use_ecc => 0, + c_algorithm => 1, + c_disable_warn_bhv_range => 0, + c_write_width_b => 8, + c_write_width_a => 8, + c_read_depth_b => 8192, + c_read_depth_a => 8192, + c_byte_size => 9, + c_sim_collision_check => "ALL", + c_use_ramb16bwer_rst_bhv => 0, + c_common_clk => 0, + c_wea_width => 1, + c_has_enb => 0, + c_web_width => 1, + c_has_ena => 1, + c_sinitb_val => "0", + c_use_byte_web => 0, + c_use_byte_wea => 0, + c_use_default_data => 0); +-- synthesis translate_on +BEGIN +-- synthesis translate_off +U0 : wrapped_basic_rom + port map ( + clka => clka, + addra => addra, + ena => ena, + douta => douta); +-- synthesis translate_on + +END basic_rom_a; + diff --git a/coregen/basic_rom.vho b/coregen/basic_rom.vho new file mode 100755 index 0000000..0d0b067 --- /dev/null +++ b/coregen/basic_rom.vho @@ -0,0 +1,58 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2007 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- The following code must appear in the VHDL architecture header: + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +component basic_rom + port ( + clka: IN std_logic; + addra: IN std_logic_VECTOR(12 downto 0); + ena: IN std_logic; + douta: OUT std_logic_VECTOR(7 downto 0)); +end component; + +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : basic_rom + port map ( + clka => clka, + addra => addra, + ena => ena, + douta => douta); +-- INST_TAG_END ------ End INSTANTIATION Template ------------ + +-- You must compile the wrapper file basic_rom.vhd when simulating +-- the core, basic_rom. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + diff --git a/coregen/basic_rom.xco b/coregen/basic_rom.xco new file mode 100755 index 0000000..12f9c62 --- /dev/null +++ b/coregen/basic_rom.xco @@ -0,0 +1,78 @@ +############################################################## +# +# Xilinx Core Generator version J.40 +# Date: Fri Jan 09 14:26:54 2009 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = False +SET asysymbol = False +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = False +SET designentry = VHDL +SET device = xc3s700an +SET devicefamily = spartan3a +SET flowvendor = Other +SET formalverification = False +SET foundationsym = False +SET implementationfiletype = Ngc +SET package = fgg484 +SET removerpms = False +SET simulationfiles = Behavioral +SET speedgrade = -4 +SET verilogsim = False +SET vhdlsim = True +# END Project Options +# BEGIN Select +SELECT Block_Memory_Generator family Xilinx,_Inc. 2.6 +# END Select +# BEGIN Parameters +CSET algorithm=Minimum_Area +CSET assume_synchronous_clk=false +CSET byte_size=9 +CSET coe_file=C:/vhdl/Basic.coe +CSET collision_warnings=ALL +CSET component_name=basic_rom +CSET disable_collision_warnings=false +CSET disable_out_of_range_warnings=false +CSET ecc=false +CSET enable_a=Use_ENA_Pin +CSET enable_b=Always_Enabled +CSET fill_remaining_memory_locations=false +CSET load_init_file=true +CSET memory_type=Single_Port_ROM +CSET operating_mode_a=WRITE_FIRST +CSET operating_mode_b=WRITE_FIRST +CSET output_reset_value_a=0 +CSET output_reset_value_b=0 +CSET pipeline_stages=0 +CSET primitive=8kx2 +CSET read_width_a=8 +CSET read_width_b=8 +CSET register_porta_output_of_memory_core=false +CSET register_porta_output_of_memory_primitives=false +CSET register_portb_output_of_memory_core=false +CSET register_portb_output_of_memory_primitives=false +CSET remaining_memory_locations=0 +CSET single_bit_ecc=false +CSET use_byte_write_enable=false +CSET use_ramb16bwer_reset_behavior=false +CSET use_regcea_pin=false +CSET use_regceb_pin=false +CSET use_ssra_pin=false +CSET use_ssrb_pin=false +CSET write_depth_a=8192 +CSET write_width_a=8 +CSET write_width_b=8 +# END Parameters +GENERATE +# CRC: 1cd67ff3 + diff --git a/coregen/basic_rom_blk_mem_gen_v2_6_xst_1_vhdl.prj b/coregen/basic_rom_blk_mem_gen_v2_6_xst_1_vhdl.prj new file mode 100755 index 0000000..39c4ab3 --- /dev/null +++ b/coregen/basic_rom_blk_mem_gen_v2_6_xst_1_vhdl.prj @@ -0,0 +1,24 @@ +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_xst_comp.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_defaults.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_pkg.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_getinit_pkg.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_min_area_pkg.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_bindec.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_mux.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3adsp.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3adsp_init.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3a.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3a_init.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v5.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v5_init.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v4.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v4_init.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v2.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v2_init.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_width.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_generic_cstr.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_input_block.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_output_block.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_top.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_xst.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\basic_rom_blk_mem_gen_v2_6_xst_1.vhd" diff --git a/coregen/basic_rom_flist.txt b/coregen/basic_rom_flist.txt new file mode 100755 index 0000000..2f70b7a --- /dev/null +++ b/coregen/basic_rom_flist.txt @@ -0,0 +1,9 @@ +# Output products list for +basic_rom.mif +basic_rom.ngc +basic_rom.vhd +basic_rom.vho +basic_rom.xco +basic_rom_blk_mem_gen_v2_6_xst_1_vhdl.prj +basic_rom_flist.txt +basic_rom_xmdf.tcl diff --git a/coregen/basic_rom_readme.txt b/coregen/basic_rom_readme.txt new file mode 100755 index 0000000..2e8eb07 --- /dev/null +++ b/coregen/basic_rom_readme.txt @@ -0,0 +1,45 @@ +The following files were generated for 'basic_rom' in directory +C:\vhdl\nascom2_t80\coregen\: + +basic_rom.mif: + Memory Initialization File which is automatically generated by the + CORE Generator System for some modules when a simulation flow is + specified. A MIF data file is used to support HDL functional + simulation of modules which use arrays of values. + +basic_rom.ngc: + Binary Xilinx implementation netlist file containing the information + required to implement the module in a Xilinx (R) FPGA. + +basic_rom.vhd: + VHDL wrapper file provided to support functional simulation. This + file contains simulation model customization data that is passed to + a parameterized simulation model for the core. + +basic_rom.vho: + VHO template file containing code that can be used as a model for + instantiating a CORE Generator module in a VHDL design. + +basic_rom.xco: + CORE Generator input file containing the parameters used to + regenerate a core. + +basic_rom_blk_mem_gen_v2_6_xst_1_vhdl.prj: + Please see the core data sheet. + +basic_rom_flist.txt: + Text file listing all of the output files produced when a customized + core was generated in the CORE Generator. + +basic_rom_readme.txt: + Text file indicating the files generated and how they are used. + +basic_rom_xmdf.tcl: + ISE Project Navigator interface file. ISE uses this file to determine + how the files output by CORE Generator for the core can be integrated + into your ISE project. + + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/coregen/basic_rom_xmdf.tcl b/coregen/basic_rom_xmdf.tcl new file mode 100755 index 0000000..d25f082 --- /dev/null +++ b/coregen/basic_rom_xmdf.tcl @@ -0,0 +1,72 @@ +# The package naming convention is _xmdf +package provide basic_rom_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::basic_rom_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::basic_rom_xmdf::xmdfInit { instance } { +# Variable containg name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name basic_rom +} +# ::basic_rom_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::basic_rom_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be magically +# available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path basic_rom.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path basic_rom.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path basic_rom.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path basic_rom.vho +utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path basic_rom.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path basic_rom_blk_mem_gen_v2_6_xst_1_vhdl.prj +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path basic_rom_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module basic_rom +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/coregen/blk_mem_gen_ds512.pdf b/coregen/blk_mem_gen_ds512.pdf new file mode 100755 index 0000000..ebe8c3d Binary files /dev/null and b/coregen/blk_mem_gen_ds512.pdf differ diff --git a/coregen/blk_mem_gen_v2_6.mif b/coregen/blk_mem_gen_v2_6.mif new file mode 100755 index 0000000..b51fac1 --- /dev/null +++ b/coregen/blk_mem_gen_v2_6.mif @@ -0,0 +1,2048 @@ +01111111 +01000001 +01000001 +01000001 +01000001 +01000001 +01000001 +01000001 +01111111 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 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\ No newline at end of file diff --git a/coregen/blk_mem_gen_v2_6.vhd b/coregen/blk_mem_gen_v2_6.vhd new file mode 100755 index 0000000..635d718 --- /dev/null +++ b/coregen/blk_mem_gen_v2_6.vhd @@ -0,0 +1,118 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2007 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file blk_mem_gen_v2_6.vhd when simulating +-- the core, blk_mem_gen_v2_6. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +Library XilinxCoreLib; +-- synthesis translate_on +ENTITY blk_mem_gen_v2_6 IS + port ( + clka: IN std_logic; + addra: IN std_logic_VECTOR(10 downto 0); + douta: OUT std_logic_VECTOR(7 downto 0)); +END blk_mem_gen_v2_6; + +ARCHITECTURE blk_mem_gen_v2_6_a OF blk_mem_gen_v2_6 IS +-- synthesis translate_off +component wrapped_blk_mem_gen_v2_6 + port ( + clka: IN std_logic; + addra: IN std_logic_VECTOR(10 downto 0); + douta: OUT std_logic_VECTOR(7 downto 0)); +end component; + +-- Configuration specification + for all : wrapped_blk_mem_gen_v2_6 use entity XilinxCoreLib.blk_mem_gen_v2_6(behavioral) + generic map( + c_has_regceb => 0, + c_has_regcea => 0, + c_mem_type => 3, + c_prim_type => 1, + c_sinita_val => "0", + c_read_width_b => 8, + c_family => "spartan3", + c_read_width_a => 8, + c_disable_warn_bhv_coll => 0, + c_write_mode_b => "WRITE_FIRST", + c_init_file_name => "blk_mem_gen_v2_6.mif", + c_write_mode_a => "WRITE_FIRST", + c_mux_pipeline_stages => 0, + c_has_mem_output_regs_b => 0, + c_load_init_file => 1, + c_xdevicefamily => "spartan3a", + c_has_mem_output_regs_a => 0, + c_write_depth_b => 2048, + c_write_depth_a => 2048, + c_has_ssrb => 0, + c_has_mux_output_regs_b => 0, + c_has_ssra => 0, + c_has_mux_output_regs_a => 0, + c_addra_width => 11, + c_addrb_width => 11, + c_default_data => "0", + c_use_ecc => 0, + c_algorithm => 1, + c_disable_warn_bhv_range => 0, + c_write_width_b => 8, + c_write_width_a => 8, + c_read_depth_b => 2048, + c_read_depth_a => 2048, + c_byte_size => 9, + c_sim_collision_check => "ALL", + c_use_ramb16bwer_rst_bhv => 0, + c_common_clk => 0, + c_wea_width => 1, + c_has_enb => 0, + c_web_width => 1, + c_has_ena => 0, + c_sinitb_val => "0", + c_use_byte_web => 0, + c_use_byte_wea => 0, + c_use_default_data => 0); +-- synthesis translate_on +BEGIN +-- synthesis translate_off +U0 : wrapped_blk_mem_gen_v2_6 + port map ( + clka => clka, + addra => addra, + douta => douta); +-- synthesis translate_on + +END blk_mem_gen_v2_6_a; + diff --git a/coregen/blk_mem_gen_v2_6.vho b/coregen/blk_mem_gen_v2_6.vho new file mode 100755 index 0000000..89f84c0 --- /dev/null +++ b/coregen/blk_mem_gen_v2_6.vho @@ -0,0 +1,56 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2007 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- The following code must appear in the VHDL architecture header: + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +component blk_mem_gen_v2_6 + port ( + clka: IN std_logic; + addra: IN std_logic_VECTOR(10 downto 0); + douta: OUT std_logic_VECTOR(7 downto 0)); +end component; + +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : blk_mem_gen_v2_6 + port map ( + clka => clka, + addra => addra, + douta => douta); +-- INST_TAG_END ------ End INSTANTIATION Template ------------ + +-- You must compile the wrapper file blk_mem_gen_v2_6.vhd when simulating +-- the core, blk_mem_gen_v2_6. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + diff --git a/coregen/blk_mem_gen_v2_6.xco b/coregen/blk_mem_gen_v2_6.xco new file mode 100755 index 0000000..37241eb --- /dev/null +++ b/coregen/blk_mem_gen_v2_6.xco @@ -0,0 +1,78 @@ +############################################################## +# +# Xilinx Core Generator version J.40 +# Date: Sat Jan 03 11:55:39 2009 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = False +SET asysymbol = False +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = False +SET designentry = VHDL +SET device = xc3s700an +SET devicefamily = spartan3a +SET flowvendor = Other +SET formalverification = False +SET foundationsym = False +SET implementationfiletype = Ngc +SET package = fgg484 +SET removerpms = False +SET simulationfiles = Behavioral +SET speedgrade = -4 +SET verilogsim = False +SET vhdlsim = True +# END Project Options +# BEGIN Select +SELECT Block_Memory_Generator family Xilinx,_Inc. 2.6 +# END Select +# BEGIN Parameters +CSET algorithm=Minimum_Area +CSET assume_synchronous_clk=false +CSET byte_size=9 +CSET coe_file=C:/vhdl/nascom2_t80/Naschr-1.coe +CSET collision_warnings=ALL +CSET component_name=blk_mem_gen_v2_6 +CSET disable_collision_warnings=false +CSET disable_out_of_range_warnings=false +CSET ecc=false +CSET enable_a=Always_Enabled +CSET enable_b=Always_Enabled +CSET fill_remaining_memory_locations=false +CSET load_init_file=true +CSET memory_type=Single_Port_ROM +CSET operating_mode_a=WRITE_FIRST +CSET operating_mode_b=WRITE_FIRST +CSET output_reset_value_a=0 +CSET output_reset_value_b=0 +CSET pipeline_stages=0 +CSET primitive=8kx2 +CSET read_width_a=8 +CSET read_width_b=8 +CSET register_porta_output_of_memory_core=false +CSET register_porta_output_of_memory_primitives=false +CSET register_portb_output_of_memory_core=false +CSET register_portb_output_of_memory_primitives=false +CSET remaining_memory_locations=0 +CSET single_bit_ecc=false +CSET use_byte_write_enable=false +CSET use_ramb16bwer_reset_behavior=false +CSET use_regcea_pin=false +CSET use_regceb_pin=false +CSET use_ssra_pin=false +CSET use_ssrb_pin=false +CSET write_depth_a=2048 +CSET write_width_a=8 +CSET write_width_b=8 +# END Parameters +GENERATE +# CRC: 686b742a + diff --git a/coregen/blk_mem_gen_v2_6_blk_mem_gen_v2_6_xst_1_vhdl.prj b/coregen/blk_mem_gen_v2_6_blk_mem_gen_v2_6_xst_1_vhdl.prj new file mode 100755 index 0000000..b43c7f4 --- /dev/null +++ b/coregen/blk_mem_gen_v2_6_blk_mem_gen_v2_6_xst_1_vhdl.prj @@ -0,0 +1,24 @@ +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_xst_comp.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_defaults.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_pkg.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_getinit_pkg.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_min_area_pkg.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_bindec.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_mux.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3adsp.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3adsp_init.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3a.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3a_init.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v5.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v5_init.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v4.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v4_init.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v2.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v2_init.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_width.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_generic_cstr.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_input_block.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_output_block.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_top.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_xst.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6_blk_mem_gen_v2_6_xst_1.vhd" diff --git a/coregen/blk_mem_gen_v2_6_flist.txt b/coregen/blk_mem_gen_v2_6_flist.txt new file mode 100755 index 0000000..c827e10 --- /dev/null +++ b/coregen/blk_mem_gen_v2_6_flist.txt @@ -0,0 +1,9 @@ +# Output products list for +blk_mem_gen_v2_6.mif +blk_mem_gen_v2_6.ngc +blk_mem_gen_v2_6.vhd +blk_mem_gen_v2_6.vho +blk_mem_gen_v2_6.xco +blk_mem_gen_v2_6_blk_mem_gen_v2_6_xst_1_vhdl.prj +blk_mem_gen_v2_6_flist.txt +blk_mem_gen_v2_6_xmdf.tcl diff --git a/coregen/blk_mem_gen_v2_6_readme.txt b/coregen/blk_mem_gen_v2_6_readme.txt new file mode 100755 index 0000000..7f4c4ff --- /dev/null +++ b/coregen/blk_mem_gen_v2_6_readme.txt @@ -0,0 +1,45 @@ +The following files were generated for 'blk_mem_gen_v2_6' in directory +C:\vhdl\nascom2_t80\coregen\: + +blk_mem_gen_v2_6.mif: + Memory Initialization File which is automatically generated by the + CORE Generator System for some modules when a simulation flow is + specified. A MIF data file is used to support HDL functional + simulation of modules which use arrays of values. + +blk_mem_gen_v2_6.ngc: + Binary Xilinx implementation netlist file containing the information + required to implement the module in a Xilinx (R) FPGA. + +blk_mem_gen_v2_6.vhd: + VHDL wrapper file provided to support functional simulation. This + file contains simulation model customization data that is passed to + a parameterized simulation model for the core. + +blk_mem_gen_v2_6.vho: + VHO template file containing code that can be used as a model for + instantiating a CORE Generator module in a VHDL design. + +blk_mem_gen_v2_6.xco: + CORE Generator input file containing the parameters used to + regenerate a core. + +blk_mem_gen_v2_6_blk_mem_gen_v2_6_xst_1_vhdl.prj: + Please see the core data sheet. + +blk_mem_gen_v2_6_flist.txt: + Text file listing all of the output files produced when a customized + core was generated in the CORE Generator. + +blk_mem_gen_v2_6_readme.txt: + Text file indicating the files generated and how they are used. + +blk_mem_gen_v2_6_xmdf.tcl: + ISE Project Navigator interface file. ISE uses this file to determine + how the files output by CORE Generator for the core can be integrated + into your ISE project. + + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/coregen/blk_mem_gen_v2_6_xmdf.tcl b/coregen/blk_mem_gen_v2_6_xmdf.tcl new file mode 100755 index 0000000..270bde4 --- /dev/null +++ b/coregen/blk_mem_gen_v2_6_xmdf.tcl @@ -0,0 +1,72 @@ +# The package naming convention is _xmdf +package provide blk_mem_gen_v2_6_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::blk_mem_gen_v2_6_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::blk_mem_gen_v2_6_xmdf::xmdfInit { instance } { +# Variable containg name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name blk_mem_gen_v2_6 +} +# ::blk_mem_gen_v2_6_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::blk_mem_gen_v2_6_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be magically +# available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v2_6.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v2_6.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v2_6.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v2_6.vho +utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v2_6.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v2_6_blk_mem_gen_v2_6_xst_1_vhdl.prj +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v2_6_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module blk_mem_gen_v2_6 +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/coregen/charrom.mif b/coregen/charrom.mif new file mode 100755 index 0000000..b51fac1 --- /dev/null +++ b/coregen/charrom.mif @@ -0,0 +1,2048 @@ +01111111 +01000001 +01000001 +01000001 +01000001 +01000001 +01000001 +01000001 +01111111 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +01111111 +01000000 +01000000 +01000000 +01000000 +01000000 +01000000 +01000000 +01000000 +00000000 +00000000 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\ No newline at end of file diff --git a/coregen/charrom.vhd b/coregen/charrom.vhd new file mode 100755 index 0000000..f0b7a08 --- /dev/null +++ b/coregen/charrom.vhd @@ -0,0 +1,118 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2007 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file charrom.vhd when simulating +-- the core, charrom. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +Library XilinxCoreLib; +-- synthesis translate_on +ENTITY charrom IS + port ( + clka: IN std_logic; + addra: IN std_logic_VECTOR(10 downto 0); + douta: OUT std_logic_VECTOR(7 downto 0)); +END charrom; + +ARCHITECTURE charrom_a OF charrom IS +-- synthesis translate_off +component wrapped_charrom + port ( + clka: IN std_logic; + addra: IN std_logic_VECTOR(10 downto 0); + douta: OUT std_logic_VECTOR(7 downto 0)); +end component; + +-- Configuration specification + for all : wrapped_charrom use entity XilinxCoreLib.blk_mem_gen_v2_6(behavioral) + generic map( + c_has_regceb => 0, + c_has_regcea => 0, + c_mem_type => 3, + c_prim_type => 1, + c_sinita_val => "0", + c_read_width_b => 8, + c_family => "spartan3", + c_read_width_a => 8, + c_disable_warn_bhv_coll => 0, + c_write_mode_b => "WRITE_FIRST", + c_init_file_name => "charrom.mif", + c_write_mode_a => "WRITE_FIRST", + c_mux_pipeline_stages => 0, + c_has_mem_output_regs_b => 0, + c_load_init_file => 1, + c_xdevicefamily => "spartan3a", + c_has_mem_output_regs_a => 0, + c_write_depth_b => 2048, + c_write_depth_a => 2048, + c_has_ssrb => 0, + c_has_mux_output_regs_b => 0, + c_has_ssra => 0, + c_has_mux_output_regs_a => 0, + c_addra_width => 11, + c_addrb_width => 11, + c_default_data => "0", + c_use_ecc => 0, + c_algorithm => 1, + c_disable_warn_bhv_range => 0, + c_write_width_b => 8, + c_write_width_a => 8, + c_read_depth_b => 2048, + c_read_depth_a => 2048, + c_byte_size => 9, + c_sim_collision_check => "ALL", + c_use_ramb16bwer_rst_bhv => 0, + c_common_clk => 0, + c_wea_width => 1, + c_has_enb => 0, + c_web_width => 1, + c_has_ena => 0, + c_sinitb_val => "0", + c_use_byte_web => 0, + c_use_byte_wea => 0, + c_use_default_data => 0); +-- synthesis translate_on +BEGIN +-- synthesis translate_off +U0 : wrapped_charrom + port map ( + clka => clka, + addra => addra, + douta => douta); +-- synthesis translate_on + +END charrom_a; + diff --git a/coregen/charrom.vho b/coregen/charrom.vho new file mode 100755 index 0000000..b586581 --- /dev/null +++ b/coregen/charrom.vho @@ -0,0 +1,56 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2007 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- The following code must appear in the VHDL architecture header: + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +component charrom + port ( + clka: IN std_logic; + addra: IN std_logic_VECTOR(10 downto 0); + douta: OUT std_logic_VECTOR(7 downto 0)); +end component; + +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : charrom + port map ( + clka => clka, + addra => addra, + douta => douta); +-- INST_TAG_END ------ End INSTANTIATION Template ------------ + +-- You must compile the wrapper file charrom.vhd when simulating +-- the core, charrom. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + diff --git a/coregen/charrom.xco b/coregen/charrom.xco new file mode 100755 index 0000000..f6247f2 --- /dev/null +++ b/coregen/charrom.xco @@ -0,0 +1,78 @@ +############################################################## +# +# Xilinx Core Generator version J.40 +# Date: Sat Jan 03 11:56:55 2009 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = False +SET asysymbol = False +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = False +SET designentry = VHDL +SET device = xc3s700an +SET devicefamily = spartan3a +SET flowvendor = Other +SET formalverification = False +SET foundationsym = False +SET implementationfiletype = Ngc +SET package = fgg484 +SET removerpms = False +SET simulationfiles = Behavioral +SET speedgrade = -4 +SET verilogsim = False +SET vhdlsim = True +# END Project Options +# BEGIN Select +SELECT Block_Memory_Generator family Xilinx,_Inc. 2.6 +# END Select +# BEGIN Parameters +CSET algorithm=Minimum_Area +CSET assume_synchronous_clk=false +CSET byte_size=9 +CSET coe_file=C:/vhdl/nascom2_t80/Naschr-1.coe +CSET collision_warnings=ALL +CSET component_name=charrom +CSET disable_collision_warnings=false +CSET disable_out_of_range_warnings=false +CSET ecc=false +CSET enable_a=Always_Enabled +CSET enable_b=Always_Enabled +CSET fill_remaining_memory_locations=false +CSET load_init_file=true +CSET memory_type=Single_Port_ROM +CSET operating_mode_a=WRITE_FIRST +CSET operating_mode_b=WRITE_FIRST +CSET output_reset_value_a=0 +CSET output_reset_value_b=0 +CSET pipeline_stages=0 +CSET primitive=8kx2 +CSET read_width_a=8 +CSET read_width_b=8 +CSET register_porta_output_of_memory_core=false +CSET register_porta_output_of_memory_primitives=false +CSET register_portb_output_of_memory_core=false +CSET register_portb_output_of_memory_primitives=false +CSET remaining_memory_locations=0 +CSET single_bit_ecc=false +CSET use_byte_write_enable=false +CSET use_ramb16bwer_reset_behavior=false +CSET use_regcea_pin=false +CSET use_regceb_pin=false +CSET use_ssra_pin=false +CSET use_ssrb_pin=false +CSET write_depth_a=2048 +CSET write_width_a=8 +CSET write_width_b=8 +# END Parameters +GENERATE +# CRC: 55453eb + diff --git a/coregen/charrom_blk_mem_gen_v2_6_xst_1_vhdl.prj b/coregen/charrom_blk_mem_gen_v2_6_xst_1_vhdl.prj new file mode 100755 index 0000000..c2f3e95 --- /dev/null +++ b/coregen/charrom_blk_mem_gen_v2_6_xst_1_vhdl.prj @@ -0,0 +1,24 @@ +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_xst_comp.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_defaults.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_pkg.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_getinit_pkg.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_min_area_pkg.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_bindec.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_mux.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3adsp.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3adsp_init.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3a.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3a_init.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v5.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v5_init.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v4.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v4_init.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v2.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v2_init.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_width.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_generic_cstr.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_input_block.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_output_block.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_top.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_xst.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\charrom_blk_mem_gen_v2_6_xst_1.vhd" diff --git a/coregen/charrom_flist.txt b/coregen/charrom_flist.txt new file mode 100755 index 0000000..1362f05 --- /dev/null +++ b/coregen/charrom_flist.txt @@ -0,0 +1,10 @@ +# Output products list for +blk_mem_gen_v2_6.mif +charrom.mif +charrom.ngc +charrom.vhd +charrom.vho +charrom.xco +charrom_blk_mem_gen_v2_6_xst_1_vhdl.prj +charrom_flist.txt +charrom_xmdf.tcl diff --git a/coregen/charrom_readme.txt b/coregen/charrom_readme.txt new file mode 100755 index 0000000..aad6288 --- /dev/null +++ b/coregen/charrom_readme.txt @@ -0,0 +1,51 @@ +The following files were generated for 'charrom' in directory +C:\vhdl\nascom2_t80\coregen\: + +blk_mem_gen_v2_6.mif: + Memory Initialization File which is automatically generated by the + CORE Generator System for some modules when a simulation flow is + specified. A MIF data file is used to support HDL functional + simulation of modules which use arrays of values. + +charrom.mif: + Memory Initialization File which is automatically generated by the + CORE Generator System for some modules when a simulation flow is + specified. A MIF data file is used to support HDL functional + simulation of modules which use arrays of values. + +charrom.ngc: + Binary Xilinx implementation netlist file containing the information + required to implement the module in a Xilinx (R) FPGA. + +charrom.vhd: + VHDL wrapper file provided to support functional simulation. This + file contains simulation model customization data that is passed to + a parameterized simulation model for the core. + +charrom.vho: + VHO template file containing code that can be used as a model for + instantiating a CORE Generator module in a VHDL design. + +charrom.xco: + CORE Generator input file containing the parameters used to + regenerate a core. + +charrom_blk_mem_gen_v2_6_xst_1_vhdl.prj: + Please see the core data sheet. + +charrom_flist.txt: + Text file listing all of the output files produced when a customized + core was generated in the CORE Generator. + +charrom_readme.txt: + Text file indicating the files generated and how they are used. + +charrom_xmdf.tcl: + ISE Project Navigator interface file. ISE uses this file to determine + how the files output by CORE Generator for the core can be integrated + into your ISE project. + + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/coregen/charrom_xmdf.tcl b/coregen/charrom_xmdf.tcl new file mode 100755 index 0000000..da71fe2 --- /dev/null +++ b/coregen/charrom_xmdf.tcl @@ -0,0 +1,76 @@ +# The package naming convention is _xmdf +package provide charrom_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::charrom_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::charrom_xmdf::xmdfInit { instance } { +# Variable containg name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name charrom +} +# ::charrom_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::charrom_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be magically +# available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v2_6.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path charrom.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path charrom.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path charrom.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path charrom.vho +utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path charrom.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path charrom_blk_mem_gen_v2_6_xst_1_vhdl.prj +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path charrom_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module charrom +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/coregen/coregen.cgp b/coregen/coregen.cgp new file mode 100755 index 0000000..8276be1 --- /dev/null +++ b/coregen/coregen.cgp @@ -0,0 +1,20 @@ +# Date: Wed Dec 31 13:09:41 2008 +SET addpads = False +SET asysymbol = False +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = False +SET designentry = VHDL +SET device = xc3s700an +SET devicefamily = spartan3a +SET flowvendor = Other +SET formalverification = False +SET foundationsym = False +SET implementationfiletype = Ngc +SET package = fgg484 +SET removerpms = False +SET simulationfiles = Behavioral +SET speedgrade = -4 +SET verilogsim = False +SET vhdlsim = True +SET workingdirectory = c:\vhdl\nascom2\coregen\tmp + diff --git a/coregen/dcm_in50.vhd b/coregen/dcm_in50.vhd new file mode 100755 index 0000000..4f5f068 --- /dev/null +++ b/coregen/dcm_in50.vhd @@ -0,0 +1,98 @@ +-------------------------------------------------------------------------------- +-- Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. +-------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 9.2.04i +-- \ \ Application : xaw2vhdl +-- / / Filename : dcm_in50.vhd +-- /___/ /\ Timestamp : 01/03/2009 16:40:00 +-- \ \ / \ +-- \___\/\___\ +-- +--Command: xaw2vhdl-st C:\vhdl\nascom2_t80\coregen\\dcm_in50.xaw C:\vhdl\nascom2_t80\coregen\\dcm_in50 +--Design Name: dcm_in50 +--Device: xc3s700an-4fgg484 +-- +-- Module dcm_in50 +-- Generated by Xilinx Architecture Wizard +-- Written for synthesis tool: XST +-- Period Jitter (unit interval) for block DCM_SP_INST = 0.05 UI +-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 2.88 ns + +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; +library UNISIM; +use UNISIM.Vcomponents.ALL; + +entity dcm_in50 is + port ( CLKIN_IN : in std_logic; + RST_IN : in std_logic; + CLKFX_OUT : out std_logic; + CLKIN_IBUFG_OUT : out std_logic; + CLK0_OUT : out std_logic; + LOCKED_OUT : out std_logic); +end dcm_in50; + +architecture BEHAVIORAL of dcm_in50 is + signal CLKFB_IN : std_logic; + signal CLKFX_BUF : std_logic; + signal CLKIN_IBUFG : std_logic; + signal CLK0_BUF : std_logic; + signal GND_BIT : std_logic; +begin + GND_BIT <= '0'; + CLKIN_IBUFG_OUT <= CLKIN_IBUFG; + CLK0_OUT <= CLKFB_IN; + CLKFX_BUFG_INST : BUFG + port map (I=>CLKFX_BUF, + O=>CLKFX_OUT); + + CLKIN_IBUFG_INST : IBUFG + port map (I=>CLKIN_IN, + O=>CLKIN_IBUFG); + + CLK0_BUFG_INST : BUFG + port map (I=>CLK0_BUF, + O=>CLKFB_IN); + + DCM_SP_INST : DCM_SP + generic map( CLK_FEEDBACK => "1X", + CLKDV_DIVIDE => 2.0, + CLKFX_DIVIDE => 25, + CLKFX_MULTIPLY => 16, + CLKIN_DIVIDE_BY_2 => TRUE, + CLKIN_PERIOD => 40.000, + CLKOUT_PHASE_SHIFT => "NONE", + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", + DFS_FREQUENCY_MODE => "LOW", + DLL_FREQUENCY_MODE => "LOW", + DUTY_CYCLE_CORRECTION => TRUE, + FACTORY_JF => x"C080", + PHASE_SHIFT => 0, + STARTUP_WAIT => TRUE) + port map (CLKFB=>CLKFB_IN, + CLKIN=>CLKIN_IBUFG, + DSSEN=>GND_BIT, + PSCLK=>GND_BIT, + PSEN=>GND_BIT, + PSINCDEC=>GND_BIT, + RST=>RST_IN, + CLKDV=>open, + CLKFX=>CLKFX_BUF, + CLKFX180=>open, + CLK0=>CLK0_BUF, + CLK2X=>open, + CLK2X180=>open, + CLK90=>open, + CLK180=>open, + CLK270=>open, + LOCKED=>LOCKED_OUT, + PSDONE=>open, + STATUS=>open); + +end BEHAVIORAL; + + diff --git a/coregen/dcm_in50.xaw b/coregen/dcm_in50.xaw new file mode 100755 index 0000000..95ea88f --- /dev/null +++ b/coregen/dcm_in50.xaw @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.4e 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b/coregen/distram16x8.vhd @@ -0,0 +1,115 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2007 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file distram16x8.vhd when simulating +-- the core, distram16x8. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +Library XilinxCoreLib; +-- synthesis translate_on +ENTITY distram16x8 IS + port ( + a: IN std_logic_VECTOR(3 downto 0); + d: IN std_logic_VECTOR(7 downto 0); + dpra: IN std_logic_VECTOR(3 downto 0); + clk: IN std_logic; + we: IN std_logic; + spo: OUT std_logic_VECTOR(7 downto 0); + dpo: OUT std_logic_VECTOR(7 downto 0)); +END distram16x8; + +ARCHITECTURE distram16x8_a OF distram16x8 IS +-- synthesis translate_off +component wrapped_distram16x8 + port ( + a: IN std_logic_VECTOR(3 downto 0); + d: IN std_logic_VECTOR(7 downto 0); + dpra: IN std_logic_VECTOR(3 downto 0); + clk: IN std_logic; + we: IN std_logic; + spo: OUT std_logic_VECTOR(7 downto 0); + dpo: OUT std_logic_VECTOR(7 downto 0)); +end component; + +-- Configuration specification + for all : wrapped_distram16x8 use entity XilinxCoreLib.dist_mem_gen_v3_3(behavioral) + generic map( + c_has_clk => 1, + c_has_qdpo_clk => 0, + c_has_qdpo_ce => 0, + c_has_d => 1, + c_has_spo => 1, + c_read_mif => 0, + c_has_qspo => 0, + c_width => 8, + c_reg_a_d_inputs => 0, + c_has_we => 1, + c_pipeline_stages => 0, + c_has_qdpo_rst => 0, + c_reg_dpra_input => 0, + c_qualify_we => 0, + c_sync_enable => 1, + c_depth => 16, + c_has_qspo_srst => 0, + c_has_qdpo_srst => 0, + c_has_dpra => 1, + c_qce_joined => 0, + c_mem_type => 2, + c_has_i_ce => 0, + c_has_dpo => 1, + c_mem_init_file => "no_coe_file_loaded", + c_default_data => "0", + c_has_spra => 0, + c_has_qspo_ce => 0, + c_addr_width => 4, + c_has_qdpo => 0, + c_has_qspo_rst => 0); +-- synthesis translate_on +BEGIN +-- synthesis translate_off +U0 : wrapped_distram16x8 + port map ( + a => a, + d => d, + dpra => dpra, + clk => clk, + we => we, + spo => spo, + dpo => dpo); +-- synthesis translate_on + +END distram16x8_a; + diff --git a/coregen/distram16x8.vho b/coregen/distram16x8.vho new file mode 100755 index 0000000..4158df6 --- /dev/null +++ b/coregen/distram16x8.vho @@ -0,0 +1,64 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2007 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- The following code must appear in the VHDL architecture header: + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +component distram16x8 + port ( + a: IN std_logic_VECTOR(3 downto 0); + d: IN std_logic_VECTOR(7 downto 0); + dpra: IN std_logic_VECTOR(3 downto 0); + clk: IN std_logic; + we: IN std_logic; + spo: OUT std_logic_VECTOR(7 downto 0); + dpo: OUT std_logic_VECTOR(7 downto 0)); +end component; + +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : distram16x8 + port map ( + a => a, + d => d, + dpra => dpra, + clk => clk, + we => we, + spo => spo, + dpo => dpo); +-- INST_TAG_END ------ End INSTANTIATION Template ------------ + +-- You must compile the wrapper file distram16x8.vhd when simulating +-- the core, distram16x8. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + diff --git a/coregen/distram16x8.xco b/coregen/distram16x8.xco new file mode 100755 index 0000000..418b005 --- /dev/null +++ b/coregen/distram16x8.xco @@ -0,0 +1,63 @@ +############################################################## +# +# Xilinx Core Generator version J.40 +# Date: Wed Dec 31 13:10:21 2008 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = False +SET asysymbol = False +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = False +SET designentry = VHDL +SET device = xc3s700an +SET devicefamily = spartan3a +SET flowvendor = Other +SET formalverification = False +SET foundationsym = False +SET implementationfiletype = Ngc +SET package = fgg484 +SET removerpms = False +SET simulationfiles = Behavioral +SET speedgrade = -4 +SET verilogsim = False +SET vhdlsim = True +# END Project Options +# BEGIN Select +SELECT Distributed_Memory_Generator family Xilinx,_Inc. 3.3 +# END Select +# BEGIN Parameters +CSET ce_overrides=ce_overrides_sync_controls +CSET coefficient_file=no_coe_file_loaded +CSET common_output_ce=false +CSET common_output_clk=false +CSET component_name=distram16x8 +CSET data_width=8 +CSET default_data=0 +CSET default_data_radix=16 +CSET depth=16 +CSET dual_port_address=non_registered +CSET dual_port_output_clock_enable=false +CSET input_clock_enable=false +CSET input_options=non_registered +CSET memory_type=dual_port_ram +CSET output_options=non_registered +CSET pipeline_stages=0 +CSET qualify_we_with_i_ce=false +CSET reset_qdpo=false +CSET reset_qspo=false +CSET single_port_output_clock_enable=false +CSET sync_reset_qdpo=false +CSET sync_reset_qspo=false +# END Parameters +GENERATE +# CRC: 79e446fd + diff --git a/coregen/distram16x8_flist.txt b/coregen/distram16x8_flist.txt new file mode 100755 index 0000000..3e334c6 --- /dev/null +++ b/coregen/distram16x8_flist.txt @@ -0,0 +1,7 @@ +# Output products list for +distram16x8.ngc +distram16x8.vhd +distram16x8.vho +distram16x8.xco +distram16x8_flist.txt +distram16x8_xmdf.tcl diff --git a/coregen/distram16x8_readme.txt b/coregen/distram16x8_readme.txt new file mode 100755 index 0000000..d74af67 --- /dev/null +++ b/coregen/distram16x8_readme.txt @@ -0,0 +1,36 @@ +The following files were generated for 'distram16x8' in directory +c:\vhdl\nascom2\coregen\: + +distram16x8.ngc: + Binary Xilinx implementation netlist file containing the information + required to implement the module in a Xilinx (R) FPGA. + +distram16x8.vhd: + VHDL wrapper file provided to support functional simulation. This + file contains simulation model customization data that is passed to + a parameterized simulation model for the core. + +distram16x8.vho: + VHO template file containing code that can be used as a model for + instantiating a CORE Generator module in a VHDL design. + +distram16x8.xco: + CORE Generator input file containing the parameters used to + regenerate a core. + +distram16x8_flist.txt: + Text file listing all of the output files produced when a customized + core was generated in the CORE Generator. + +distram16x8_readme.txt: + Text file indicating the files generated and how they are used. + +distram16x8_xmdf.tcl: + ISE Project Navigator interface file. ISE uses this file to determine + how the files output by CORE Generator for the core can be integrated + into your ISE project. + + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/coregen/distram16x8_xmdf.tcl b/coregen/distram16x8_xmdf.tcl new file mode 100755 index 0000000..86a52bc --- /dev/null +++ b/coregen/distram16x8_xmdf.tcl @@ -0,0 +1,64 @@ +# The package naming convention is _xmdf +package provide distram16x8_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::distram16x8_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::distram16x8_xmdf::xmdfInit { instance } { +# Variable containg name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name distram16x8 +} +# ::distram16x8_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::distram16x8_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be magically +# available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path distram16x8.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path distram16x8.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path distram16x8.vho +utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path distram16x8.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path distram16x8_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module distram16x8 +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/coregen/monitorrom.asy b/coregen/monitorrom.asy new file mode 100755 index 0000000..bdc17b3 --- /dev/null +++ b/coregen/monitorrom.asy @@ -0,0 +1,17 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 monitorrom +RECTANGLE Normal 32 32 544 576 +LINE Wide 0 80 32 80 +PIN 0 80 LEFT 36 +PINATTR PinName addra[10:0] +PINATTR Polarity IN +LINE Normal 0 272 32 272 +PIN 0 272 LEFT 36 +PINATTR PinName clka +PINATTR Polarity IN +LINE Wide 576 80 544 80 +PIN 576 80 RIGHT 36 +PINATTR PinName douta[7:0] +PINATTR Polarity OUT + diff --git a/coregen/monitorrom.mif b/coregen/monitorrom.mif new file mode 100755 index 0000000..92e4f0b --- /dev/null +++ b/coregen/monitorrom.mif @@ -0,0 +1,2048 @@ +00110001 +00000000 +00010000 +11010111 +00001000 +11000011 +10110010 +00000011 +11011111 +01100010 +11011000 +00011000 +11111011 +11000011 +10011010 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\ No newline at end of file diff --git a/coregen/monitorrom.sym b/coregen/monitorrom.sym new file mode 100755 index 0000000..552fd0f --- /dev/null +++ b/coregen/monitorrom.sym @@ -0,0 +1,27 @@ +VERSION 5 +BEGIN SYMBOL monitorrom +SYMBOLTYPE BLOCK +TIMESTAMP 2008 12 31 13 31 1 +SYMPIN 0 80 Input addra[10:0] +SYMPIN 0 272 Input clka +SYMPIN 576 80 Output douta[7:0] +BEGIN DISPLAY 32 32 TEXT monitorrom + FONT 40 "Arial" +END DISPLAY +RECTANGLE N 32 32 544 576 +BEGIN LINE W 0 80 32 80 +END LINE +BEGIN DISPLAY 36 80 PIN addra[10:0] ATTR PinName + FONT 24 "Arial" +END DISPLAY +LINE N 0 272 32 272 +BEGIN DISPLAY 36 272 PIN clka ATTR PinName + FONT 24 "Arial" +END DISPLAY +BEGIN LINE W 576 80 544 80 +END LINE +BEGIN DISPLAY 540 80 PIN douta[7:0] ATTR PinName + ALIGNMENT RIGHT + FONT 24 "Arial" +END DISPLAY +END SYMBOL diff --git a/coregen/monitorrom.v b/coregen/monitorrom.v new file mode 100755 index 0000000..39e0d16 --- /dev/null +++ b/coregen/monitorrom.v @@ -0,0 +1,126 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2007 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +// You must compile the wrapper file monitorrom.v when simulating +// the core, monitorrom. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +`timescale 1ns/1ps + +module monitorrom( + clka, + addra, + douta); + + +input clka; +input [10 : 0] addra; +output [7 : 0] douta; + +// synthesis translate_off + + BLK_MEM_GEN_V2_6 #( + .C_ADDRA_WIDTH(11), + .C_ADDRB_WIDTH(11), + .C_ALGORITHM(1), + .C_BYTE_SIZE(9), + .C_COMMON_CLK(0), + .C_DEFAULT_DATA("0"), + .C_DISABLE_WARN_BHV_COLL(0), + .C_DISABLE_WARN_BHV_RANGE(0), + .C_FAMILY("spartan3"), + .C_HAS_ENA(0), + .C_HAS_ENB(0), + .C_HAS_MEM_OUTPUT_REGS_A(0), + .C_HAS_MEM_OUTPUT_REGS_B(0), + .C_HAS_MUX_OUTPUT_REGS_A(0), + .C_HAS_MUX_OUTPUT_REGS_B(0), + .C_HAS_REGCEA(0), + .C_HAS_REGCEB(0), + .C_HAS_SSRA(0), + .C_HAS_SSRB(0), + .C_INIT_FILE_NAME("monitorrom.mif"), + .C_LOAD_INIT_FILE(1), + .C_MEM_TYPE(3), + .C_MUX_PIPELINE_STAGES(0), + .C_PRIM_TYPE(1), + .C_READ_DEPTH_A(2048), + .C_READ_DEPTH_B(2048), + .C_READ_WIDTH_A(8), + .C_READ_WIDTH_B(8), + .C_SIM_COLLISION_CHECK("ALL"), + .C_SINITA_VAL("0"), + .C_SINITB_VAL("0"), + .C_USE_BYTE_WEA(0), + .C_USE_BYTE_WEB(0), + .C_USE_DEFAULT_DATA(1), + .C_USE_ECC(0), + .C_USE_RAMB16BWER_RST_BHV(0), + .C_WEA_WIDTH(1), + .C_WEB_WIDTH(1), + .C_WRITE_DEPTH_A(2048), + .C_WRITE_DEPTH_B(2048), + .C_WRITE_MODE_A("WRITE_FIRST"), + .C_WRITE_MODE_B("WRITE_FIRST"), + .C_WRITE_WIDTH_A(8), + .C_WRITE_WIDTH_B(8), + .C_XDEVICEFAMILY("spartan3a")) + inst ( + .CLKA(clka), + .ADDRA(addra), + .DOUTA(douta), + .DINA(), + .ENA(), + .REGCEA(), + .WEA(), + .SSRA(), + .CLKB(), + .DINB(), + .ADDRB(), + .ENB(), + .REGCEB(), + .WEB(), + .SSRB(), + .DOUTB(), + .DBITERR(), + .SBITERR()); + + +// synthesis translate_on + +// XST black box declaration +// box_type "black_box" +// synthesis attribute box_type of monitorrom is "black_box" + +endmodule + diff --git a/coregen/monitorrom.veo b/coregen/monitorrom.veo new file mode 100755 index 0000000..933febe --- /dev/null +++ b/coregen/monitorrom.veo @@ -0,0 +1,45 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2007 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +monitorrom YourInstanceName ( + .clka(clka), + .addra(addra), // Bus [10 : 0] + .douta(douta)); // Bus [7 : 0] + +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file monitorrom.v when simulating +// the core, monitorrom. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + diff --git a/coregen/monitorrom.vhd b/coregen/monitorrom.vhd new file mode 100755 index 0000000..a54319d --- /dev/null +++ b/coregen/monitorrom.vhd @@ -0,0 +1,121 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2007 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file monitorrom.vhd when simulating +-- the core, monitorrom. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +Library XilinxCoreLib; +-- synthesis translate_on +ENTITY monitorrom IS + port ( + clka: IN std_logic; + addra: IN std_logic_VECTOR(10 downto 0); + ena: IN std_logic; + douta: OUT std_logic_VECTOR(7 downto 0)); +END monitorrom; + +ARCHITECTURE monitorrom_a OF monitorrom IS +-- synthesis translate_off +component wrapped_monitorrom + port ( + clka: IN std_logic; + addra: IN std_logic_VECTOR(10 downto 0); + ena: IN std_logic; + douta: OUT std_logic_VECTOR(7 downto 0)); +end component; + +-- Configuration specification + for all : wrapped_monitorrom use entity XilinxCoreLib.blk_mem_gen_v2_6(behavioral) + generic map( + c_has_regceb => 0, + c_has_regcea => 0, + c_mem_type => 3, + c_prim_type => 1, + c_sinita_val => "0", + c_read_width_b => 8, + c_family => "spartan3", + c_read_width_a => 8, + c_disable_warn_bhv_coll => 0, + c_write_mode_b => "WRITE_FIRST", + c_init_file_name => "monitorrom.mif", + c_write_mode_a => "WRITE_FIRST", + c_mux_pipeline_stages => 0, + c_has_mem_output_regs_b => 0, + c_load_init_file => 1, + c_xdevicefamily => "spartan3a", + c_has_mem_output_regs_a => 0, + c_write_depth_b => 2048, + c_write_depth_a => 2048, + c_has_ssrb => 0, + c_has_mux_output_regs_b => 0, + c_has_ssra => 0, + c_has_mux_output_regs_a => 0, + c_addra_width => 11, + c_addrb_width => 11, + c_default_data => "0", + c_use_ecc => 0, + c_algorithm => 1, + c_disable_warn_bhv_range => 0, + c_write_width_b => 8, + c_write_width_a => 8, + c_read_depth_b => 2048, + c_read_depth_a => 2048, + c_byte_size => 9, + c_sim_collision_check => "ALL", + c_use_ramb16bwer_rst_bhv => 0, + c_common_clk => 0, + c_wea_width => 1, + c_has_enb => 0, + c_web_width => 1, + c_has_ena => 1, + c_sinitb_val => "0", + c_use_byte_web => 0, + c_use_byte_wea => 0, + c_use_default_data => 1); +-- synthesis translate_on +BEGIN +-- synthesis translate_off +U0 : wrapped_monitorrom + port map ( + clka => clka, + addra => addra, + ena => ena, + douta => douta); +-- synthesis translate_on + +END monitorrom_a; + diff --git a/coregen/monitorrom.vhd.bak b/coregen/monitorrom.vhd.bak new file mode 100755 index 0000000..fc79256 --- /dev/null +++ b/coregen/monitorrom.vhd.bak @@ -0,0 +1,118 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2007 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file monitorrom.vhd when simulating +-- the core, monitorrom. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +Library XilinxCoreLib; +-- synthesis translate_on +ENTITY monitorrom IS + port ( + clka: IN std_logic; + addra: IN std_logic_VECTOR(10 downto 0); + douta: OUT std_logic_VECTOR(7 downto 0)); +END monitorrom; + +ARCHITECTURE monitorrom_a OF monitorrom IS +-- synthesis translate_off +component wrapped_monitorrom + port ( + clka: IN std_logic; + addra: IN std_logic_VECTOR(10 downto 0); + douta: OUT std_logic_VECTOR(7 downto 0)); +end component; + +-- Configuration specification + for all : wrapped_monitorrom use entity XilinxCoreLib.blk_mem_gen_v2_6(behavioral) + generic map( + c_has_regceb => 0, + c_has_regcea => 0, + c_mem_type => 3, + c_prim_type => 1, + c_sinita_val => "0", + c_read_width_b => 8, + c_family => "spartan3", + c_read_width_a => 8, + c_disable_warn_bhv_coll => 0, + c_write_mode_b => "WRITE_FIRST", + c_init_file_name => "monitorrom.mif", + c_write_mode_a => "WRITE_FIRST", + c_mux_pipeline_stages => 0, + c_has_mem_output_regs_b => 0, + c_load_init_file => 1, + c_xdevicefamily => "spartan3a", + c_has_mem_output_regs_a => 0, + c_write_depth_b => 2048, + c_write_depth_a => 2048, + c_has_ssrb => 0, + c_has_mux_output_regs_b => 0, + c_has_ssra => 0, + c_has_mux_output_regs_a => 0, + c_addra_width => 11, + c_addrb_width => 11, + c_default_data => "0", + c_use_ecc => 0, + c_algorithm => 1, + c_disable_warn_bhv_range => 0, + c_write_width_b => 8, + c_write_width_a => 8, + c_read_depth_b => 2048, + c_read_depth_a => 2048, + c_byte_size => 9, + c_sim_collision_check => "ALL", + c_use_ramb16bwer_rst_bhv => 0, + c_common_clk => 0, + c_wea_width => 1, + c_has_enb => 0, + c_web_width => 1, + c_has_ena => 0, + c_sinitb_val => "0", + c_use_byte_web => 0, + c_use_byte_wea => 0, + c_use_default_data => 1); +-- synthesis translate_on +BEGIN +-- synthesis translate_off +U0 : wrapped_monitorrom + port map ( + clka => clka, + addra => addra, + douta => douta); +-- synthesis translate_on + +END monitorrom_a; + diff --git a/coregen/monitorrom.vho b/coregen/monitorrom.vho new file mode 100755 index 0000000..5c91323 --- /dev/null +++ b/coregen/monitorrom.vho @@ -0,0 +1,58 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2007 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- The following code must appear in the VHDL architecture header: + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +component monitorrom + port ( + clka: IN std_logic; + addra: IN std_logic_VECTOR(10 downto 0); + ena: IN std_logic; + douta: OUT std_logic_VECTOR(7 downto 0)); +end component; + +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : monitorrom + port map ( + clka => clka, + addra => addra, + ena => ena, + douta => douta); +-- INST_TAG_END ------ End INSTANTIATION Template ------------ + +-- You must compile the wrapper file monitorrom.vhd when simulating +-- the core, monitorrom. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + diff --git a/coregen/monitorrom.xco b/coregen/monitorrom.xco new file mode 100755 index 0000000..24b453c --- /dev/null +++ b/coregen/monitorrom.xco @@ -0,0 +1,78 @@ +############################################################## +# +# Xilinx Core Generator version J.40 +# Date: Thu Jan 08 11:30:25 2009 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = False +SET asysymbol = False +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = False +SET designentry = VHDL +SET device = xc3s700an +SET devicefamily = spartan3a +SET flowvendor = Other +SET formalverification = False +SET foundationsym = False +SET implementationfiletype = Ngc +SET package = fgg484 +SET removerpms = False +SET simulationfiles = Behavioral +SET speedgrade = -4 +SET verilogsim = False +SET vhdlsim = True +# END Project Options +# BEGIN Select +SELECT Block_Memory_Generator family Xilinx,_Inc. 2.6 +# END Select +# BEGIN Parameters +CSET algorithm=Minimum_Area +CSET assume_synchronous_clk=false +CSET byte_size=9 +CSET coe_file=C:/vhdl/nascom2_t80/NASSYSI.coe +CSET collision_warnings=ALL +CSET component_name=monitorrom +CSET disable_collision_warnings=false +CSET disable_out_of_range_warnings=false +CSET ecc=false +CSET enable_a=Use_ENA_Pin +CSET enable_b=Always_Enabled +CSET fill_remaining_memory_locations=true +CSET load_init_file=true +CSET memory_type=Single_Port_ROM +CSET operating_mode_a=WRITE_FIRST +CSET operating_mode_b=WRITE_FIRST +CSET output_reset_value_a=0 +CSET output_reset_value_b=0 +CSET pipeline_stages=0 +CSET primitive=8kx2 +CSET read_width_a=8 +CSET read_width_b=8 +CSET register_porta_output_of_memory_core=false +CSET register_porta_output_of_memory_primitives=false +CSET register_portb_output_of_memory_core=false +CSET register_portb_output_of_memory_primitives=false +CSET remaining_memory_locations=0 +CSET single_bit_ecc=false +CSET use_byte_write_enable=false +CSET use_ramb16bwer_reset_behavior=false +CSET use_regcea_pin=false +CSET use_regceb_pin=false +CSET use_ssra_pin=false +CSET use_ssrb_pin=false +CSET write_depth_a=2048 +CSET write_width_a=8 +CSET write_width_b=8 +# END Parameters +GENERATE +# CRC: b5ba28bc + diff --git a/coregen/monitorrom_blk_mem_gen_v2_6_xst_1_vhdl.prj b/coregen/monitorrom_blk_mem_gen_v2_6_xst_1_vhdl.prj new file mode 100755 index 0000000..93d52cf --- /dev/null +++ b/coregen/monitorrom_blk_mem_gen_v2_6_xst_1_vhdl.prj @@ -0,0 +1,24 @@ +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_xst_comp.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_defaults.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_pkg.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_getinit_pkg.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_min_area_pkg.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_bindec.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_mux.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3adsp.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3adsp_init.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3a.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3a_init.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v5.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v5_init.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v4.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v4_init.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v2.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v2_init.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_width.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_generic_cstr.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_input_block.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_output_block.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_top.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_xst.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\monitorrom_blk_mem_gen_v2_6_xst_1.vhd" diff --git a/coregen/monitorrom_flist.txt b/coregen/monitorrom_flist.txt new file mode 100755 index 0000000..2490680 --- /dev/null +++ b/coregen/monitorrom_flist.txt @@ -0,0 +1,9 @@ +# Output products list for +monitorrom.mif +monitorrom.ngc +monitorrom.vhd +monitorrom.vho +monitorrom.xco +monitorrom_blk_mem_gen_v2_6_xst_1_vhdl.prj +monitorrom_flist.txt +monitorrom_xmdf.tcl diff --git a/coregen/monitorrom_readme.txt b/coregen/monitorrom_readme.txt new file mode 100755 index 0000000..4d09c2b --- /dev/null +++ b/coregen/monitorrom_readme.txt @@ -0,0 +1,45 @@ +The following files were generated for 'monitorrom' in directory +C:\vhdl\nascom2_t80\coregen\: + +monitorrom.mif: + Memory Initialization File which is automatically generated by the + CORE Generator System for some modules when a simulation flow is + specified. A MIF data file is used to support HDL functional + simulation of modules which use arrays of values. + +monitorrom.ngc: + Binary Xilinx implementation netlist file containing the information + required to implement the module in a Xilinx (R) FPGA. + +monitorrom.vhd: + VHDL wrapper file provided to support functional simulation. This + file contains simulation model customization data that is passed to + a parameterized simulation model for the core. + +monitorrom.vho: + VHO template file containing code that can be used as a model for + instantiating a CORE Generator module in a VHDL design. + +monitorrom.xco: + CORE Generator input file containing the parameters used to + regenerate a core. + +monitorrom_blk_mem_gen_v2_6_xst_1_vhdl.prj: + Please see the core data sheet. + +monitorrom_flist.txt: + Text file listing all of the output files produced when a customized + core was generated in the CORE Generator. + +monitorrom_readme.txt: + Text file indicating the files generated and how they are used. + +monitorrom_xmdf.tcl: + ISE Project Navigator interface file. ISE uses this file to determine + how the files output by CORE Generator for the core can be integrated + into your ISE project. + + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/coregen/monitorrom_xmdf.tcl b/coregen/monitorrom_xmdf.tcl new file mode 100755 index 0000000..267b49a --- /dev/null +++ b/coregen/monitorrom_xmdf.tcl @@ -0,0 +1,72 @@ +# The package naming convention is _xmdf +package provide monitorrom_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::monitorrom_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::monitorrom_xmdf::xmdfInit { instance } { +# Variable containg name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name monitorrom +} +# ::monitorrom_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::monitorrom_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be magically +# available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path monitorrom.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path monitorrom.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path monitorrom.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path monitorrom.vho +utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path monitorrom.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path monitorrom_blk_mem_gen_v2_6_xst_1_vhdl.prj +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path monitorrom_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module monitorrom +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/coregen/ram2kx8.ngc b/coregen/ram2kx8.ngc new file mode 100755 index 0000000..924effa --- /dev/null +++ b/coregen/ram2kx8.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.4e 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\ No newline at end of file diff --git a/coregen/ram2kx8.vhd b/coregen/ram2kx8.vhd new file mode 100755 index 0000000..6755751 --- /dev/null +++ b/coregen/ram2kx8.vhd @@ -0,0 +1,142 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2007 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file ram2kx8.vhd when simulating +-- the core, ram2kx8. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +Library XilinxCoreLib; +-- synthesis translate_on +ENTITY ram2kx8 IS + port ( + clka: IN std_logic; + dina: IN std_logic_VECTOR(7 downto 0); + addra: IN std_logic_VECTOR(10 downto 0); + ena: IN std_logic; + wea: IN std_logic_VECTOR(0 downto 0); + douta: OUT std_logic_VECTOR(7 downto 0); + clkb: IN std_logic; + dinb: IN std_logic_VECTOR(7 downto 0); + addrb: IN std_logic_VECTOR(10 downto 0); + web: IN std_logic_VECTOR(0 downto 0); + doutb: OUT std_logic_VECTOR(7 downto 0)); +END ram2kx8; + +ARCHITECTURE ram2kx8_a OF ram2kx8 IS +-- synthesis translate_off +component wrapped_ram2kx8 + port ( + clka: IN std_logic; + dina: IN std_logic_VECTOR(7 downto 0); + addra: IN std_logic_VECTOR(10 downto 0); + ena: IN std_logic; + wea: IN std_logic_VECTOR(0 downto 0); + douta: OUT std_logic_VECTOR(7 downto 0); + clkb: IN std_logic; + dinb: IN std_logic_VECTOR(7 downto 0); + addrb: IN std_logic_VECTOR(10 downto 0); + web: IN std_logic_VECTOR(0 downto 0); + doutb: OUT std_logic_VECTOR(7 downto 0)); +end component; + +-- Configuration specification + for all : wrapped_ram2kx8 use entity XilinxCoreLib.blk_mem_gen_v2_6(behavioral) + generic map( + c_has_regceb => 0, + c_has_regcea => 0, + c_mem_type => 2, + c_prim_type => 1, + c_sinita_val => "0", + c_read_width_b => 8, + c_family => "spartan3", + c_read_width_a => 8, + c_disable_warn_bhv_coll => 0, + c_write_mode_b => "READ_FIRST", + c_init_file_name => "no_coe_file_loaded", + c_write_mode_a => "READ_FIRST", + c_mux_pipeline_stages => 0, + c_has_mem_output_regs_b => 0, + c_load_init_file => 0, + c_xdevicefamily => "spartan3a", + c_has_mem_output_regs_a => 0, + c_write_depth_b => 2048, + c_write_depth_a => 2048, + c_has_ssrb => 0, + c_has_mux_output_regs_b => 0, + c_has_ssra => 0, + c_has_mux_output_regs_a => 0, + c_addra_width => 11, + c_addrb_width => 11, + c_default_data => "0", + c_use_ecc => 0, + c_algorithm => 1, + c_disable_warn_bhv_range => 0, + c_write_width_b => 8, + c_write_width_a => 8, + c_read_depth_b => 2048, + c_read_depth_a => 2048, + c_byte_size => 9, + c_sim_collision_check => "ALL", + c_use_ramb16bwer_rst_bhv => 0, + c_common_clk => 0, + c_wea_width => 1, + c_has_enb => 0, + c_web_width => 1, + c_has_ena => 1, + c_sinitb_val => "0", + c_use_byte_web => 0, + c_use_byte_wea => 0, + c_use_default_data => 1); +-- synthesis translate_on +BEGIN +-- synthesis translate_off +U0 : wrapped_ram2kx8 + port map ( + clka => clka, + dina => dina, + addra => addra, + ena => ena, + wea => wea, + douta => douta, + clkb => clkb, + dinb => dinb, + addrb => addrb, + web => web, + doutb => doutb); +-- synthesis translate_on + +END ram2kx8_a; + diff --git a/coregen/ram2kx8.vho b/coregen/ram2kx8.vho new file mode 100755 index 0000000..53f3039 --- /dev/null +++ b/coregen/ram2kx8.vho @@ -0,0 +1,72 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2007 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- The following code must appear in the VHDL architecture header: + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +component ram2kx8 + port ( + clka: IN std_logic; + dina: IN std_logic_VECTOR(7 downto 0); + addra: IN std_logic_VECTOR(10 downto 0); + ena: IN std_logic; + wea: IN std_logic_VECTOR(0 downto 0); + douta: OUT std_logic_VECTOR(7 downto 0); + clkb: IN std_logic; + dinb: IN std_logic_VECTOR(7 downto 0); + addrb: IN std_logic_VECTOR(10 downto 0); + web: IN std_logic_VECTOR(0 downto 0); + doutb: OUT std_logic_VECTOR(7 downto 0)); +end component; + +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : ram2kx8 + port map ( + clka => clka, + dina => dina, + addra => addra, + ena => ena, + wea => wea, + douta => douta, + clkb => clkb, + dinb => dinb, + addrb => addrb, + web => web, + doutb => doutb); +-- INST_TAG_END ------ End INSTANTIATION Template ------------ + +-- You must compile the wrapper file ram2kx8.vhd when simulating +-- the core, ram2kx8. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + diff --git a/coregen/ram2kx8.xco b/coregen/ram2kx8.xco new file mode 100755 index 0000000..50bd751 --- /dev/null +++ b/coregen/ram2kx8.xco @@ -0,0 +1,78 @@ +############################################################## +# +# Xilinx Core Generator version J.40 +# Date: Sat Jan 03 15:42:53 2009 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = False +SET asysymbol = False +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = False +SET designentry = VHDL +SET device = xc3s700an +SET devicefamily = spartan3a +SET flowvendor = Other +SET formalverification = False +SET foundationsym = False +SET implementationfiletype = Ngc +SET package = fgg484 +SET removerpms = False +SET simulationfiles = Behavioral +SET speedgrade = -4 +SET verilogsim = False +SET vhdlsim = True +# END Project Options +# BEGIN Select +SELECT Block_Memory_Generator family Xilinx,_Inc. 2.6 +# END Select +# BEGIN Parameters +CSET algorithm=Minimum_Area +CSET assume_synchronous_clk=false +CSET byte_size=9 +CSET coe_file=no_coe_file_loaded +CSET collision_warnings=ALL +CSET component_name=ram2kx8 +CSET disable_collision_warnings=false +CSET disable_out_of_range_warnings=false +CSET ecc=false +CSET enable_a=Use_ENA_Pin +CSET enable_b=Always_Enabled +CSET fill_remaining_memory_locations=true +CSET load_init_file=false +CSET memory_type=True_Dual_Port_RAM +CSET operating_mode_a=READ_FIRST +CSET operating_mode_b=READ_FIRST +CSET output_reset_value_a=0 +CSET output_reset_value_b=0 +CSET pipeline_stages=0 +CSET primitive=8kx2 +CSET read_width_a=8 +CSET read_width_b=8 +CSET register_porta_output_of_memory_core=false +CSET register_porta_output_of_memory_primitives=false +CSET register_portb_output_of_memory_core=false +CSET register_portb_output_of_memory_primitives=false +CSET remaining_memory_locations=0 +CSET single_bit_ecc=false +CSET use_byte_write_enable=false +CSET use_ramb16bwer_reset_behavior=false +CSET use_regcea_pin=false +CSET use_regceb_pin=false +CSET use_ssra_pin=false +CSET use_ssrb_pin=false +CSET write_depth_a=2048 +CSET write_width_a=8 +CSET write_width_b=8 +# END Parameters +GENERATE +# CRC: bde5567c + diff --git a/coregen/ram2kx8_blk_mem_gen_v2_6_xst_1_vhdl.prj b/coregen/ram2kx8_blk_mem_gen_v2_6_xst_1_vhdl.prj new file mode 100755 index 0000000..6660009 --- /dev/null +++ b/coregen/ram2kx8_blk_mem_gen_v2_6_xst_1_vhdl.prj @@ -0,0 +1,24 @@ +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_xst_comp.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_defaults.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_pkg.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_getinit_pkg.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_min_area_pkg.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_bindec.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_mux.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3adsp.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3adsp_init.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3a.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_s3a_init.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v5.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v5_init.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v4.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v4_init.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v2.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_wrapper_v2_init.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_prim_width.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_generic_cstr.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_input_block.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_output_block.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_top.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\blk_mem_gen_v2_6\blk_mem_gen_v2_6_xst.vhd" +vhdl blk_mem_gen_v2_6 "c:\vhdl\nascom2\coregen\tmp\_cg\_bbx\ram2kx8_blk_mem_gen_v2_6_xst_1.vhd" diff --git a/coregen/ram2kx8_flist.txt b/coregen/ram2kx8_flist.txt new file mode 100755 index 0000000..617b5d9 --- /dev/null +++ b/coregen/ram2kx8_flist.txt @@ -0,0 +1,8 @@ +# Output products list for +ram2kx8.ngc +ram2kx8.vhd +ram2kx8.vho +ram2kx8.xco +ram2kx8_blk_mem_gen_v2_6_xst_1_vhdl.prj +ram2kx8_flist.txt +ram2kx8_xmdf.tcl diff --git a/coregen/ram2kx8_readme.txt b/coregen/ram2kx8_readme.txt new file mode 100755 index 0000000..ea45a08 --- /dev/null +++ b/coregen/ram2kx8_readme.txt @@ -0,0 +1,39 @@ +The following files were generated for 'ram2kx8' in directory +C:\vhdl\nascom2_t80\coregen\: + +ram2kx8.ngc: + Binary Xilinx implementation netlist file containing the information + required to implement the module in a Xilinx (R) FPGA. + +ram2kx8.vhd: + VHDL wrapper file provided to support functional simulation. This + file contains simulation model customization data that is passed to + a parameterized simulation model for the core. + +ram2kx8.vho: + VHO template file containing code that can be used as a model for + instantiating a CORE Generator module in a VHDL design. + +ram2kx8.xco: + CORE Generator input file containing the parameters used to + regenerate a core. + +ram2kx8_blk_mem_gen_v2_6_xst_1_vhdl.prj: + Please see the core data sheet. + +ram2kx8_flist.txt: + Text file listing all of the output files produced when a customized + core was generated in the CORE Generator. + +ram2kx8_readme.txt: + Text file indicating the files generated and how they are used. + +ram2kx8_xmdf.tcl: + ISE Project Navigator interface file. ISE uses this file to determine + how the files output by CORE Generator for the core can be integrated + into your ISE project. + + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/coregen/ram2kx8_xmdf.tcl b/coregen/ram2kx8_xmdf.tcl new file mode 100755 index 0000000..459b5e0 --- /dev/null +++ b/coregen/ram2kx8_xmdf.tcl @@ -0,0 +1,68 @@ +# The package naming convention is _xmdf +package provide ram2kx8_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::ram2kx8_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::ram2kx8_xmdf::xmdfInit { instance } { +# Variable containg name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name ram2kx8 +} +# ::ram2kx8_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::ram2kx8_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be magically +# available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram2kx8.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram2kx8.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram2kx8.vho +utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram2kx8.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram2kx8_blk_mem_gen_v2_6_xst_1_vhdl.prj +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram2kx8_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module ram2kx8 +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/dcm_in50_sim.vhd b/dcm_in50_sim.vhd new file mode 100755 index 0000000..5a375ea --- /dev/null +++ b/dcm_in50_sim.vhd @@ -0,0 +1,49 @@ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + + +entity dcm_in50 is + + port ( + CLKIN_IN : in std_logic; + RST_IN : in std_logic; + CLKFX_OUT : out std_logic; + CLKIN_IBUFG_OUT : out std_logic; + CLK0_OUT : out std_logic; + LOCKED_OUT : out std_logic); + +end dcm_in50; + +architecture Behavioral of dcm_in50 is + +begin -- Behavioral + + LOCKED_OUT <= '1'; + CLKIN_IBUFG_OUT <= CLKIN_IN; + + process + begin + wait until CLKIN_IN = '1'; + while true loop + CLK0_OUT <= '1'; + wait for 20 ns; + CLK0_OUT <= '0'; + wait for 20 ns; + end loop; + end process; + + process + begin + wait until CLKIN_IN = '1'; + while true loop + CLKFX_OUT <= '1'; + wait for 31.25 ns; + CLKFX_OUT <= '0'; + wait for 31.25 ns; + end loop; + end process; + +end Behavioral; diff --git a/fifo16x8.vhd b/fifo16x8.vhd new file mode 100755 index 0000000..a76dfc7 --- /dev/null +++ b/fifo16x8.vhd @@ -0,0 +1,72 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 14:10:50 12/28/2008 +-- Design Name: +-- Module Name: fifo16x8 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +library UNISIM; +use UNISIM.VComponents.all; + +entity fifo16x8 is + Port ( DATAIN : in STD_LOGIC_VECTOR (7 downto 0); + WRITESTB : in STD_LOGIC; + DATAOUT : out STD_LOGIC_VECTOR (7 downto 0); + READSTB : in STD_LOGIC; + CLK : in STD_LOGIC; + FULL : out STD_LOGIC; + EMPTY : out STD_LOGIC); +end fifo16x8; + +architecture Behavioral of fifo16x8 is +signal counter: std_logic_vector(3 downto 0) := "1111"; +begin + +shift: for i in 0 to 7 generate + srl16e_inst: SRL16E port map( + Q => DATAOUT(i), + A0 => counter(0), + A1 => counter(1), + A2 => counter(2), + A3 => counter(3), + CE => WRITESTB, + CLK => CLK, + D => DATAIN(i)); +end generate; + +fifo: process(CLK) + begin + if rising_edge(CLK) then + if (WRITESTB = '0') and (READSTB = '1') then + counter <= counter - 1; + elsif (WRITESTB = '1') and (READSTB = '0') then + counter <= counter + 1; + else + counter <= counter; + end if; + end if; + end process; + +FULL <= '1' when counter = "1110" else '0'; +EMPTY <= '1' when counter = "1111" else '0'; +end Behavioral; + diff --git a/kcpsm3.vhd b/kcpsm3.vhd new file mode 100755 index 0000000..e1e5804 --- /dev/null +++ b/kcpsm3.vhd @@ -0,0 +1,1901 @@ +-- PicoBlaze +-- +-- Constant (K) Coded Programmable State Machine for Spartan-3 Devices. +-- Also suitable for use with Virtex-II(PRO) and Virtex-4 devices. +-- +-- Includes additional code for enhanced VHDL simulation. +-- +-- Version : 1.30 +-- Version Date : 14th June 2004 +-- Reasons : Avoid issue caused when ENABLE INTERRUPT is used when interrupts are +-- already enabled when an an interrupt input is applied. +-- Improved design for faster ZERO and CARRY flag logic +-- +-- +-- Previous Version : 1.20 +-- Version Date : 9th July 2003 +-- +-- Start of design entry : 19th May 2003 +-- +-- Ken Chapman +-- Xilinx Ltd +-- Benchmark House +-- 203 Brooklands Road +-- Weybridge +-- Surrey KT13 ORH +-- United Kingdom +-- +-- chapman@xilinx.com +-- +-- Instruction disassembly concept inspired by the work of Prof. Dr.-Ing. Bernhard Lang. +-- University of Applied Sciences, Osnabrueck, Germany. +-- +------------------------------------------------------------------------------------ +-- +-- NOTICE: +-- +-- Copyright Xilinx, Inc. 2003. This code may be contain portions patented by other +-- third parties. By providing this core as one possible implementation of a standard, +-- Xilinx is making no representation that the provided implementation of this standard +-- is free from any claims of infringement by any third party. Xilinx expressly +-- disclaims any warranty with respect to the adequacy of the implementation, including +-- but not limited to any warranty or representation that the implementation is free +-- from claims of any third party. Furthermore, Xilinx is providing this core as a +-- courtesy to you and suggests that you contact all third parties to obtain the +-- necessary rights to use this implementation. +-- +------------------------------------------------------------------------------------ +-- +-- Format of this file. +-- +-- This file contains the definition of KCPSM3 as one complete module with sections +-- created using generate loops. This 'flat' approach has been adopted to decrease +-- the time taken to load the module into simulators and the synthesis process. +-- +-- The module defines the implementation of the logic using Xilinx primitives. +-- These ensure predictable synthesis results and maximise the density of the implementation. +-- The Unisim Library is used to define Xilinx primitives. It is also used during +-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd +-- +------------------------------------------------------------------------------------ +-- +-- Library declarations +-- +-- Standard IEEE libraries +-- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +library unisim; +use unisim.vcomponents.all; +-- +------------------------------------------------------------------------------------ +-- +-- Main Entity for KCPSM3 +-- +entity kcpsm3 is + Port ( address : out std_logic_vector(9 downto 0); + instruction : in std_logic_vector(17 downto 0); + port_id : out std_logic_vector(7 downto 0); + write_strobe : out std_logic; + out_port : out std_logic_vector(7 downto 0); + read_strobe : out std_logic; + in_port : in std_logic_vector(7 downto 0); + interrupt : in std_logic; + interrupt_ack : out std_logic; + reset : in std_logic; + clk : in std_logic); + end kcpsm3; +-- +------------------------------------------------------------------------------------ +-- +-- Start of Main Architecture for KCPSM3 +-- +architecture low_level_definition of kcpsm3 is +-- +------------------------------------------------------------------------------------ +-- +-- Signals used in KCPSM3 +-- +------------------------------------------------------------------------------------ +-- +-- Fundamental control and decode signals +-- +signal t_state : std_logic; +signal not_t_state : std_logic; +signal internal_reset : std_logic; +signal reset_delay : std_logic; +signal move_group : std_logic; +signal condition_met : std_logic; +signal normal_count : std_logic; +signal call_type : std_logic; +signal push_or_pop_type : std_logic; +signal valid_to_move : std_logic; +-- +-- Flag signals +-- +signal flag_type : std_logic; +signal flag_write : std_logic; +signal flag_enable : std_logic; +signal zero_flag : std_logic; +signal sel_shadow_zero : std_logic; +signal low_zero : std_logic; +signal high_zero : std_logic; +signal low_zero_carry : std_logic; +signal high_zero_carry : std_logic; +signal zero_carry : std_logic; +signal zero_fast_route : std_logic; +signal low_parity : std_logic; +signal high_parity : std_logic; +signal parity_carry : std_logic; +signal parity : std_logic; +signal carry_flag : std_logic; +signal sel_parity : std_logic; +signal sel_arith_carry : std_logic; +signal sel_shift_carry : std_logic; +signal sel_shadow_carry : std_logic; +signal sel_carry : std_logic_vector(3 downto 0); +signal carry_fast_route : std_logic; +-- +-- Interrupt signals +-- +signal active_interrupt : std_logic; +signal int_pulse : std_logic; +signal clean_int : std_logic; +signal shadow_carry : std_logic; +signal shadow_zero : std_logic; +signal int_enable : std_logic; +signal int_update_enable : std_logic; +signal int_enable_value : std_logic; +signal interrupt_ack_internal : std_logic; +-- +-- Program Counter signals +-- +signal pc : std_logic_vector(9 downto 0); +signal pc_vector : std_logic_vector(9 downto 0); +signal pc_vector_carry : std_logic_vector(8 downto 0); +signal inc_pc_vector : std_logic_vector(9 downto 0); +signal pc_value : std_logic_vector(9 downto 0); +signal pc_value_carry : std_logic_vector(8 downto 0); +signal inc_pc_value : std_logic_vector(9 downto 0); +signal pc_enable : std_logic; +-- +-- Data Register signals +-- +signal sx : std_logic_vector(7 downto 0); +signal sy : std_logic_vector(7 downto 0); +signal register_type : std_logic; +signal register_write : std_logic; +signal register_enable : std_logic; +signal second_operand : std_logic_vector(7 downto 0); +-- +-- Scratch Pad Memory signals +-- +signal memory_data : std_logic_vector(7 downto 0); +signal store_data : std_logic_vector(7 downto 0); +signal memory_type : std_logic; +signal memory_write : std_logic; +signal memory_enable : std_logic; +-- +-- Stack signals +-- +signal stack_pop_data : std_logic_vector(9 downto 0); +signal stack_ram_data : std_logic_vector(9 downto 0); +signal stack_address : std_logic_vector(4 downto 0); +signal half_stack_address : std_logic_vector(4 downto 0); +signal stack_address_carry : std_logic_vector(3 downto 0); +signal next_stack_address : std_logic_vector(4 downto 0); +signal stack_write_enable : std_logic; +signal not_active_interrupt : std_logic; +-- +-- ALU signals +-- +signal logical_result : std_logic_vector(7 downto 0); +signal logical_value : std_logic_vector(7 downto 0); +signal sel_logical : std_logic; +signal shift_result : std_logic_vector(7 downto 0); +signal shift_value : std_logic_vector(7 downto 0); +signal sel_shift : std_logic; +signal high_shift_in : std_logic; +signal low_shift_in : std_logic; +signal shift_in : std_logic; +signal shift_carry : std_logic; +signal shift_carry_value : std_logic; +signal arith_result : std_logic_vector(7 downto 0); +signal arith_value : std_logic_vector(7 downto 0); +signal half_arith : std_logic_vector(7 downto 0); +signal arith_internal_carry : std_logic_vector(7 downto 0); +signal sel_arith_carry_in : std_logic; +signal arith_carry_in : std_logic; +signal invert_arith_carry : std_logic; +signal arith_carry_out : std_logic; +signal sel_arith : std_logic; +signal arith_carry : std_logic; +-- +-- ALU multiplexer signals +-- +signal input_fetch_type : std_logic; +signal sel_group : std_logic; +signal alu_group : std_logic_vector(7 downto 0); +signal input_group : std_logic_vector(7 downto 0); +signal alu_result : std_logic_vector(7 downto 0); +-- +-- read and write strobes +-- +signal io_initial_decode : std_logic; +signal write_active : std_logic; +signal read_active : std_logic; +-- +-- +------------------------------------------------------------------------------------ +-- +-- Attributes to define LUT contents during implementation for primitives not +-- contained within generate loops. In each case the information is repeated +-- in the generic map for functional simulation +-- +attribute INIT : string; +attribute INIT of t_state_lut : label is "1"; +attribute INIT of int_pulse_lut : label is "0080"; +attribute INIT of int_update_lut : label is "EAAA"; +attribute INIT of int_value_lut : label is "04"; +attribute INIT of move_group_lut : label is "7400"; +attribute INIT of condition_met_lut : label is "5A3C"; +attribute INIT of normal_count_lut : label is "2F"; +attribute INIT of call_type_lut : label is "1000"; +attribute INIT of push_pop_lut : label is "5400"; +attribute INIT of valid_move_lut : label is "D"; +attribute INIT of flag_type_lut : label is "41FC"; +attribute INIT of flag_enable_lut : label is "8"; +attribute INIT of low_zero_lut : label is "0001"; +attribute INIT of high_zero_lut : label is "0001"; +attribute INIT of sel_shadow_zero_lut : label is "3F"; +attribute INIT of low_parity_lut : label is "6996"; +attribute INIT of high_parity_lut : label is "6996"; +attribute INIT of sel_parity_lut : label is "F3FF"; +attribute INIT of sel_arith_carry_lut : label is "F3"; +attribute INIT of sel_shift_carry_lut : label is "C"; +attribute INIT of sel_shadow_carry_lut : label is "3"; +attribute INIT of register_type_lut : label is "0145"; +attribute INIT of register_enable_lut : label is "8"; +attribute INIT of memory_type_lut : label is "0400"; +attribute INIT of memory_enable_lut : label is "8000"; +attribute INIT of sel_logical_lut : label is "FFE2"; +attribute INIT of low_shift_in_lut : label is "E4"; +attribute INIT of high_shift_in_lut : label is "E4"; +attribute INIT of shift_carry_lut : label is "E4"; +attribute INIT of sel_arith_lut : label is "1F"; +attribute INIT of input_fetch_type_lut : label is "0002"; +attribute INIT of io_decode_lut : label is "0010"; +attribute INIT of write_active_lut : label is "4000"; +attribute INIT of read_active_lut : label is "0100"; +-- +------------------------------------------------------------------------------------ +-- +-- Start of KCPSM3 circuit description +-- +------------------------------------------------------------------------------------ +-- +begin +-- +------------------------------------------------------------------------------------ +-- +-- Fundamental Control +-- +-- Definition of T-state and internal reset +-- +------------------------------------------------------------------------------------ +-- + t_state_lut: LUT1 + --synthesis translate_off + generic map (INIT => X"1") + --synthesis translate_on + port map( I0 => t_state, + O => not_t_state ); + + toggle_flop: FDR + port map ( D => not_t_state, + Q => t_state, + R => internal_reset, + C => clk); + + reset_flop1: FDS + port map ( D => '0', + Q => reset_delay, + S => reset, + C => clk); + + reset_flop2: FDS + port map ( D => reset_delay, + Q => internal_reset, + S => reset, + C => clk); +-- +------------------------------------------------------------------------------------ +-- +-- Interrupt input logic, Interrupt enable and shadow Flags. +-- +-- Captures interrupt input and enables the shadow flags. +-- Decodes instructions which set and reset the interrupt enable flip-flop. +-- +------------------------------------------------------------------------------------ +-- + + -- Interrupt capture + + int_capture_flop: FDR + port map ( D => interrupt, + Q => clean_int, + R => internal_reset, + C => clk); + + int_pulse_lut: LUT4 + --synthesis translate_off + generic map (INIT => X"0080") + --synthesis translate_on + port map( I0 => t_state, + I1 => clean_int, + I2 => int_enable, + I3 => active_interrupt, + O => int_pulse ); + + int_flop: FDR + port map ( D => int_pulse, + Q => active_interrupt, + R => internal_reset, + C => clk); + + ack_flop: FD + port map ( D => active_interrupt, + Q => interrupt_ack_internal, + C => clk); + + interrupt_ack <= interrupt_ack_internal; + + -- Shadow flags + + shadow_carry_flop: FDE + port map ( D => carry_flag, + Q => shadow_carry, + CE => active_interrupt, + C => clk); + + shadow_zero_flop: FDE + port map ( D => zero_flag, + Q => shadow_zero, + CE => active_interrupt, + C => clk); + + -- Decode instructions that set or reset interrupt enable + + int_update_lut: LUT4 + --synthesis translate_off + generic map (INIT => X"EAAA") + --synthesis translate_on + port map( I0 => active_interrupt, + I1 => instruction(15), + I2 => instruction(16), + I3 => instruction(17), + O => int_update_enable ); + + int_value_lut: LUT3 + --synthesis translate_off + generic map (INIT => X"04") + --synthesis translate_on + port map( I0 => active_interrupt, + I1 => instruction(0), + I2 => interrupt_ack_internal, + O => int_enable_value ); + + int_enable_flop: FDRE + port map ( D => int_enable_value, + Q => int_enable, + CE => int_update_enable, + R => internal_reset, + C => clk); +-- +------------------------------------------------------------------------------------ +-- +-- Decodes for the control of the program counter and CALL/RETURN stack +-- +------------------------------------------------------------------------------------ +-- + move_group_lut: LUT4 + --synthesis translate_off + generic map (INIT => X"7400") + --synthesis translate_on + port map( I0 => instruction(14), + I1 => instruction(15), + I2 => instruction(16), + I3 => instruction(17), + O => move_group ); + + condition_met_lut: LUT4 + --synthesis translate_off + generic map (INIT => X"5A3C") + --synthesis translate_on + port map( I0 => carry_flag, + I1 => zero_flag, + I2 => instruction(10), + I3 => instruction(11), + O => condition_met ); + + normal_count_lut: LUT3 + --synthesis translate_off + generic map (INIT => X"2F") + --synthesis translate_on + port map( I0 => instruction(12), + I1 => condition_met, + I2 => move_group, + O => normal_count ); + + call_type_lut: LUT4 + --synthesis translate_off + generic map (INIT => X"1000") + --synthesis translate_on + port map( I0 => instruction(14), + I1 => instruction(15), + I2 => instruction(16), + I3 => instruction(17), + O => call_type ); + + push_pop_lut: LUT4 + --synthesis translate_off + generic map (INIT => X"5400") + --synthesis translate_on + port map( I0 => instruction(14), + I1 => instruction(15), + I2 => instruction(16), + I3 => instruction(17), + O => push_or_pop_type ); + + valid_move_lut: LUT2 + --synthesis translate_off + generic map (INIT => X"D") + --synthesis translate_on + port map( I0 => instruction(12), + I1 => condition_met, + O => valid_to_move ); +-- +------------------------------------------------------------------------------------ +-- +-- The ZERO and CARRY Flags +-- +------------------------------------------------------------------------------------ +-- + -- Enable for flags + + flag_type_lut: LUT4 + --synthesis translate_off + generic map (INIT => X"41FC") + --synthesis translate_on + port map( I0 => instruction(14), + I1 => instruction(15), + I2 => instruction(16), + I3 => instruction(17), + O => flag_type ); + + flag_write_flop: FD + port map ( D => flag_type, + Q => flag_write, + C => clk); + + flag_enable_lut: LUT2 + --synthesis translate_off + generic map (INIT => X"8") + --synthesis translate_on + port map( I0 => t_state, + I1 => flag_write, + O => flag_enable ); + + -- Zero Flag + + low_zero_lut: LUT4 + --synthesis translate_off + generic map (INIT => X"0001") + --synthesis translate_on + port map( I0 => alu_result(0), + I1 => alu_result(1), + I2 => alu_result(2), + I3 => alu_result(3), + O => low_zero ); + + high_zero_lut: LUT4 + --synthesis translate_off + generic map (INIT => X"0001") + --synthesis translate_on + port map( I0 => alu_result(4), + I1 => alu_result(5), + I2 => alu_result(6), + I3 => alu_result(7), + O => high_zero ); + + low_zero_muxcy: MUXCY + port map( DI => '0', + CI => '1', + S => low_zero, + O => low_zero_carry ); + + high_zero_cymux: MUXCY + port map( DI => '0', + CI => low_zero_carry, + S => high_zero, + O => high_zero_carry ); + + sel_shadow_zero_lut: LUT3 + --synthesis translate_off + generic map (INIT => X"3F") + --synthesis translate_on + port map( I0 => shadow_zero, + I1 => instruction(16), + I2 => instruction(17), + O => sel_shadow_zero ); + + zero_cymux: MUXCY + port map( DI => shadow_zero, + CI => high_zero_carry, + S => sel_shadow_zero, + O => zero_carry ); + + zero_xor: XORCY + port map( LI => '0', + CI => zero_carry, + O => zero_fast_route); + + zero_flag_flop: FDRE + port map ( D => zero_fast_route, + Q => zero_flag, + CE => flag_enable, + R => internal_reset, + C => clk); + + -- Parity detection + + low_parity_lut: LUT4 + --synthesis translate_off + generic map (INIT => X"6996") + --synthesis translate_on + port map( I0 => logical_result(0), + I1 => logical_result(1), + I2 => logical_result(2), + I3 => logical_result(3), + O => low_parity ); + + high_parity_lut: LUT4 + --synthesis translate_off + generic map (INIT => X"6996") + --synthesis translate_on + port map( I0 => logical_result(4), + I1 => logical_result(5), + I2 => logical_result(6), + I3 => logical_result(7), + O => high_parity ); + + parity_muxcy: MUXCY + port map( DI => '0', + CI => '1', + S => low_parity, + O => parity_carry ); + + parity_xor: XORCY + port map( LI => high_parity, + CI => parity_carry, + O => parity); + + -- CARRY flag selection + + sel_parity_lut: LUT4 + --synthesis translate_off + generic map (INIT => X"F3FF") + --synthesis translate_on + port map( I0 => parity, + I1 => instruction(13), + I2 => instruction(15), + I3 => instruction(16), + O => sel_parity ); + + sel_arith_carry_lut: LUT3 + --synthesis translate_off + generic map (INIT => X"F3") + --synthesis translate_on + port map( I0 => arith_carry, + I1 => instruction(16), + I2 => instruction(17), + O => sel_arith_carry ); + + sel_shift_carry_lut: LUT2 + --synthesis translate_off + generic map (INIT => X"C") + --synthesis translate_on + port map( I0 => shift_carry, + I1 => instruction(15), + O => sel_shift_carry ); + + sel_shadow_carry_lut: LUT2 + --synthesis translate_off + generic map (INIT => X"3") + --synthesis translate_on + port map( I0 => shadow_carry, + I1 => instruction(17), + O => sel_shadow_carry ); + + sel_shadow_muxcy: MUXCY + port map( DI => shadow_carry, + CI => '0', + S => sel_shadow_carry, + O => sel_carry(0) ); + + sel_shift_muxcy: MUXCY + port map( DI => shift_carry, + CI => sel_carry(0), + S => sel_shift_carry, + O => sel_carry(1) ); + + sel_arith_muxcy: MUXCY + port map( DI => arith_carry, + CI => sel_carry(1), + S => sel_arith_carry, + O => sel_carry(2) ); + + sel_parity_muxcy: MUXCY + port map( DI => parity, + CI => sel_carry(2), + S => sel_parity, + O => sel_carry(3) ); + + carry_xor: XORCY + port map( LI => '0', + CI => sel_carry(3), + O => carry_fast_route); + + carry_flag_flop: FDRE + port map ( D => carry_fast_route, + Q => carry_flag, + CE => flag_enable, + R => internal_reset, + C => clk); +-- +------------------------------------------------------------------------------------ +-- +-- The Program Counter +-- +-- Definition of a 10-bit counter which can be loaded from two sources +-- +------------------------------------------------------------------------------------ +-- + + invert_enable: INV -- Inverter should be implemented in the CE to flip flops + port map( I => t_state, + O => pc_enable); + + pc_loop: for i in 0 to 9 generate + -- + -- Attribute to define LUT contents during implementation + -- The information is repeated in the generic map for functional simulation + -- + attribute INIT : string; + attribute INIT of vector_select_mux : label is "E4"; + attribute INIT of value_select_mux : label is "E4"; + -- + begin + + vector_select_mux: LUT3 + --synthesis translate_off + generic map (INIT => X"E4") + --synthesis translate_on + port map( I0 => instruction(15), + I1 => instruction(i), + I2 => stack_pop_data(i), + O => pc_vector(i) ); + + value_select_mux: LUT3 + --synthesis translate_off + generic map (INIT => X"E4") + --synthesis translate_on + port map( I0 => normal_count, + I1 => inc_pc_vector(i), + I2 => pc(i), + O => pc_value(i) ); + + register_bit: FDRSE + port map ( D => inc_pc_value(i), + Q => pc(i), + R => internal_reset, + S => active_interrupt, + CE => pc_enable, + C => clk); + + pc_lsb_carry: if i=0 generate + begin + + pc_vector_muxcy: MUXCY + port map( DI => '0', + CI => instruction(13), + S => pc_vector(i), + O => pc_vector_carry(i)); + + pc_vector_xor: XORCY + port map( LI => pc_vector(i), + CI => instruction(13), + O => inc_pc_vector(i)); + + pc_value_muxcy: MUXCY + port map( DI => '0', + CI => normal_count, + S => pc_value(i), + O => pc_value_carry(i)); + + pc_value_xor: XORCY + port map( LI => pc_value(i), + CI => normal_count, + O => inc_pc_value(i)); + + end generate pc_lsb_carry; + + pc_mid_carry: if i>0 and i<9 generate + begin + + pc_vector_muxcy: MUXCY + port map( DI => '0', + CI => pc_vector_carry(i-1), + S => pc_vector(i), + O => pc_vector_carry(i)); + + pc_vector_xor: XORCY + port map( LI => pc_vector(i), + CI => pc_vector_carry(i-1), + O => inc_pc_vector(i)); + + pc_value_muxcy: MUXCY + port map( DI => '0', + CI => pc_value_carry(i-1), + S => pc_value(i), + O => pc_value_carry(i)); + + pc_value_xor: XORCY + port map( LI => pc_value(i), + CI => pc_value_carry(i-1), + O => inc_pc_value(i)); + + end generate pc_mid_carry; + + pc_msb_carry: if i=9 generate + begin + + pc_vector_xor: XORCY + port map( LI => pc_vector(i), + CI => pc_vector_carry(i-1), + O => inc_pc_vector(i)); + + pc_value_xor: XORCY + port map( LI => pc_value(i), + CI => pc_value_carry(i-1), + O => inc_pc_value(i)); + + end generate pc_msb_carry; + + end generate pc_loop; + + address <= pc; +-- +------------------------------------------------------------------------------------ +-- +-- Register Bank and second operand selection. +-- +-- Definition of an 8-bit dual port RAM with 16 locations +-- including write enable decode. +-- +-- Outputs are assigned to PORT_ID and OUT_PORT. +-- +------------------------------------------------------------------------------------ +-- + -- Forming decode signal + + register_type_lut: LUT4 + --synthesis translate_off + generic map (INIT => X"0145") + --synthesis translate_on + port map( I0 => active_interrupt, + I1 => instruction(15), + I2 => instruction(16), + I3 => instruction(17), + O => register_type ); + + register_write_flop: FD + port map ( D => register_type, + Q => register_write, + C => clk); + + register_enable_lut: LUT2 + --synthesis translate_off + generic map (INIT => X"8") + --synthesis translate_on + port map( I0 => t_state, + I1 => register_write, + O => register_enable ); + + reg_loop: for i in 0 to 7 generate + -- + -- Attribute to define RAM contents during implementation + -- The information is repeated in the generic map for functional simulation + -- + attribute INIT : string; + attribute INIT of register_bit : label is "0000"; + attribute INIT of operand_select_mux : label is "E4"; + -- + begin + + register_bit: RAM16X1D + --synthesis translate_off + generic map(INIT => X"0000") + --synthesis translate_on + port map ( D => alu_result(i), + WE => register_enable, + WCLK => clk, + A0 => instruction(8), + A1 => instruction(9), + A2 => instruction(10), + A3 => instruction(11), + DPRA0 => instruction(4), + DPRA1 => instruction(5), + DPRA2 => instruction(6), + DPRA3 => instruction(7), + SPO => sx(i), + DPO => sy(i)); + + operand_select_mux: LUT3 + --synthesis translate_off + generic map (INIT => X"E4") + --synthesis translate_on + port map( I0 => instruction(12), + I1 => instruction(i), + I2 => sy(i), + O => second_operand(i) ); + + end generate reg_loop; + + out_port <= sx; + port_id <= second_operand; +-- +------------------------------------------------------------------------------------ +-- +-- Store Memory +-- +-- Definition of an 8-bit single port RAM with 64 locations +-- including write enable decode. +-- +------------------------------------------------------------------------------------ +-- + -- Forming decode signal + + memory_type_lut: LUT4 + --synthesis translate_off + generic map (INIT => X"0400") + --synthesis translate_on + port map( I0 => active_interrupt, + I1 => instruction(15), + I2 => instruction(16), + I3 => instruction(17), + O => memory_type ); + + memory_write_flop: FD + port map ( D => memory_type, + Q => memory_write, + C => clk); + + memory_enable_lut: LUT4 + --synthesis translate_off + generic map (INIT => X"8000") + --synthesis translate_on + port map( I0 => t_state, + I1 => instruction(13), + I2 => instruction(14), + I3 => memory_write, + O => memory_enable ); + + store_loop: for i in 0 to 7 generate + -- + -- Attribute to define RAM contents during implementation + -- The information is repeated in the generic map for functional simulation + -- + attribute INIT : string; + attribute INIT of memory_bit : label is "0000000000000000"; + -- + begin + + memory_bit: RAM64X1S + --synthesis translate_off + generic map(INIT => X"0000000000000000") + --synthesis translate_on + port map ( D => sx(i), + WE => memory_enable, + WCLK => clk, + A0 => second_operand(0), + A1 => second_operand(1), + A2 => second_operand(2), + A3 => second_operand(3), + A4 => second_operand(4), + A5 => second_operand(5), + O => memory_data(i)); + + store_flop: FD + port map ( D => memory_data(i), + Q => store_data(i), + C => clk); + + end generate store_loop; +-- +------------------------------------------------------------------------------------ +-- +-- Logical operations +-- +-- Definition of AND, OR, XOR and LOAD functions which also provides TEST. +-- Includes pipeline stage used to form ALU multiplexer including decode. +-- +------------------------------------------------------------------------------------ +-- + sel_logical_lut: LUT4 + --synthesis translate_off + generic map (INIT => X"FFE2") + --synthesis translate_on + port map( I0 => instruction(14), + I1 => instruction(15), + I2 => instruction(16), + I3 => instruction(17), + O => sel_logical ); + + logical_loop: for i in 0 to 7 generate + -- + -- Attribute to define LUT contents during implementation + -- The information is repeated in the generic map for functional simulation + attribute INIT : string; + attribute INIT of logical_lut : label is "6E8A"; + -- + begin + + logical_lut: LUT4 + --synthesis translate_off + generic map (INIT => X"6E8A") + --synthesis translate_on + port map( I0 => second_operand(i), + I1 => sx(i), + I2 => instruction(13), + I3 => instruction(14), + O => logical_value(i)); + + logical_flop: FDR + port map ( D => logical_value(i), + Q => logical_result(i), + R => sel_logical, + C => clk); + + end generate logical_loop; +-- +-- +------------------------------------------------------------------------------------ +-- +-- Shift and Rotate operations +-- +-- Includes pipeline stage used to form ALU multiplexer including decode. +-- +------------------------------------------------------------------------------------ +-- + sel_shift_inv: INV -- Inverter should be implemented in the reset to flip flops + port map( I => instruction(17), + O => sel_shift); + + -- Bit to input to shift register + + high_shift_in_lut: LUT3 + --synthesis translate_off + generic map (INIT => X"E4") + --synthesis translate_on + port map( I0 => instruction(1), + I1 => sx(0), + I2 => instruction(0), + O => high_shift_in ); + + low_shift_in_lut: LUT3 + --synthesis translate_off + generic map (INIT => X"E4") + --synthesis translate_on + port map( I0 => instruction(1), + I1 => carry_flag, + I2 => sx(7), + O => low_shift_in ); + + shift_in_muxf5: MUXF5 + port map( I1 => high_shift_in, + I0 => low_shift_in, + S => instruction(2), + O => shift_in ); + + -- Forming shift carry signal + + shift_carry_lut: LUT3 + --synthesis translate_off + generic map (INIT => X"E4") + --synthesis translate_on + port map( I0 => instruction(3), + I1 => sx(7), + I2 => sx(0), + O => shift_carry_value ); + + pipeline_bit: FD + port map ( D => shift_carry_value, + Q => shift_carry, + C => clk); + + shift_loop: for i in 0 to 7 generate + begin + + lsb_shift: if i=0 generate + -- + -- Attribute to define LUT contents during implementation + -- The information is repeated in the generic map for functional simulation + attribute INIT : string; + attribute INIT of shift_mux_lut : label is "E4"; + -- + begin + + shift_mux_lut: LUT3 + --synthesis translate_off + generic map (INIT => X"E4") + --synthesis translate_on + port map( I0 => instruction(3), + I1 => shift_in, + I2 => sx(i+1), + O => shift_value(i) ); + + end generate lsb_shift; + + mid_shift: if i>0 and i<7 generate + -- + -- Attribute to define LUT contents during implementation + -- The information is repeated in the generic map for functional simulation + attribute INIT : string; + attribute INIT of shift_mux_lut : label is "E4"; + -- + begin + + shift_mux_lut: LUT3 + --synthesis translate_off + generic map (INIT => X"E4") + --synthesis translate_on + port map( I0 => instruction(3), + I1 => sx(i-1), + I2 => sx(i+1), + O => shift_value(i) ); + + end generate mid_shift; + + msb_shift: if i=7 generate + -- + -- Attribute to define LUT contents during implementation + -- The information is repeated in the generic map for functional simulation + attribute INIT : string; + attribute INIT of shift_mux_lut : label is "E4"; + -- + begin + + shift_mux_lut: LUT3 + --synthesis translate_off + generic map (INIT => X"E4") + --synthesis translate_on + port map( I0 => instruction(3), + I1 => sx(i-1), + I2 => shift_in, + O => shift_value(i) ); + + end generate msb_shift; + + shift_flop: FDR + port map ( D => shift_value(i), + Q => shift_result(i), + R => sel_shift, + C => clk); + + end generate shift_loop; +-- +------------------------------------------------------------------------------------ +-- +-- Arithmetic operations +-- +-- Definition of ADD, ADDCY, SUB and SUBCY functions which also provides COMPARE. +-- Includes pipeline stage used to form ALU multiplexer including decode. +-- +------------------------------------------------------------------------------------ +-- + sel_arith_lut: LUT3 + --synthesis translate_off + generic map (INIT => X"1F") + --synthesis translate_on + port map( I0 => instruction(14), + I1 => instruction(15), + I2 => instruction(16), + O => sel_arith ); + + arith_loop: for i in 0 to 7 generate + -- + -- Attribute to define LUT contents during implementation + -- The information is repeated in the generic map for functional simulation + attribute INIT : string; + attribute INIT of arith_lut : label is "96"; + -- + begin + + lsb_arith: if i=0 generate + -- + -- Attribute to define LUT contents during implementation + -- The information is repeated in the generic map for functional simulation + attribute INIT : string; + attribute INIT of arith_carry_in_lut : label is "6C"; + -- + begin + + arith_carry_in_lut: LUT3 + --synthesis translate_off + generic map (INIT => X"6C") + --synthesis translate_on + port map( I0 => instruction(13), + I1 => instruction(14), + I2 => carry_flag, + O => sel_arith_carry_in ); + + arith_carry_in_muxcy: MUXCY + port map( DI => '0', + CI => '1', + S => sel_arith_carry_in, + O => arith_carry_in); + + arith_muxcy: MUXCY + port map( DI => sx(i), + CI => arith_carry_in, + S => half_arith(i), + O => arith_internal_carry(i)); + + arith_xor: XORCY + port map( LI => half_arith(i), + CI => arith_carry_in, + O => arith_value(i)); + + end generate lsb_arith; + + mid_arith: if i>0 and i<7 generate + begin + + arith_muxcy: MUXCY + port map( DI => sx(i), + CI => arith_internal_carry(i-1), + S => half_arith(i), + O => arith_internal_carry(i)); + + arith_xor: XORCY + port map( LI => half_arith(i), + CI => arith_internal_carry(i-1), + O => arith_value(i)); + + end generate mid_arith; + + msb_arith: if i=7 generate + -- + -- Attribute to define LUT contents during implementation + -- The information is repeated in the generic map for functional simulation + attribute INIT : string; + attribute INIT of arith_carry_out_lut : label is "2"; + -- + begin + + arith_muxcy: MUXCY + port map( DI => sx(i), + CI => arith_internal_carry(i-1), + S => half_arith(i), + O => arith_internal_carry(i)); + + arith_xor: XORCY + port map( LI => half_arith(i), + CI => arith_internal_carry(i-1), + O => arith_value(i)); + + arith_carry_out_lut: LUT1 + --synthesis translate_off + generic map (INIT => X"2") + --synthesis translate_on + port map( I0 => instruction(14), + O => invert_arith_carry ); + + arith_carry_out_xor: XORCY + port map( LI => invert_arith_carry, + CI => arith_internal_carry(i), + O => arith_carry_out); + + arith_carry_flop: FDR + port map ( D => arith_carry_out, + Q => arith_carry, + R => sel_arith, + C => clk); + + end generate msb_arith; + + arith_lut: LUT3 + --synthesis translate_off + generic map (INIT => X"96") + --synthesis translate_on + port map( I0 => sx(i), + I1 => second_operand(i), + I2 => instruction(14), + O => half_arith(i)); + + arith_flop: FDR + port map ( D => arith_value(i), + Q => arith_result(i), + R => sel_arith, + C => clk); + + end generate arith_loop; +-- +-- +------------------------------------------------------------------------------------ +-- +-- ALU multiplexer +-- +------------------------------------------------------------------------------------ +-- + input_fetch_type_lut: LUT4 + --synthesis translate_off + generic map (INIT => X"0002") + --synthesis translate_on + port map( I0 => instruction(14), + I1 => instruction(15), + I2 => instruction(16), + I3 => instruction(17), + O => input_fetch_type ); + + sel_group_flop: FD + port map ( D => input_fetch_type, + Q => sel_group, + C => clk); + + alu_mux_loop: for i in 0 to 7 generate + -- + -- Attribute to define LUT contents during implementation + -- The information is repeated in the generic map for functional simulation + attribute INIT : string; + attribute INIT of or_lut : label is "FE"; + attribute INIT of mux_lut : label is "E4"; + -- + begin + + or_lut: LUT3 + --synthesis translate_off + generic map (INIT => X"FE") + --synthesis translate_on + port map( I0 => logical_result(i), + I1 => arith_result(i), + I2 => shift_result(i), + O => alu_group(i)); + + mux_lut: LUT3 + --synthesis translate_off + generic map (INIT => X"E4") + --synthesis translate_on + port map( I0 => instruction(13), + I1 => in_port(i), + I2 => store_data(i), + O => input_group(i)); + + shift_in_muxf5: MUXF5 + port map( I1 => input_group(i), + I0 => alu_group(i), + S => sel_group, + O => alu_result(i) ); + + end generate alu_mux_loop; +-- +------------------------------------------------------------------------------------ +-- +-- Read and Write Strobes +-- +------------------------------------------------------------------------------------ +-- + io_decode_lut: LUT4 + --synthesis translate_off + generic map (INIT => X"0010") + --synthesis translate_on + port map( I0 => active_interrupt, + I1 => instruction(13), + I2 => instruction(14), + I3 => instruction(16), + O => io_initial_decode ); + + write_active_lut: LUT4 + --synthesis translate_off + generic map (INIT => X"4000") + --synthesis translate_on + port map( I0 => t_state, + I1 => instruction(15), + I2 => instruction(17), + I3 => io_initial_decode, + O => write_active ); + + write_strobe_flop: FDR + port map ( D => write_active, + Q => write_strobe, + R => internal_reset, + C => clk); + + read_active_lut: LUT4 + --synthesis translate_off + generic map (INIT => X"0100") + --synthesis translate_on + port map( I0 => t_state, + I1 => instruction(15), + I2 => instruction(17), + I3 => io_initial_decode, + O => read_active ); + + read_strobe_flop: FDR + port map ( D => read_active, + Q => read_strobe, + R => internal_reset, + C => clk); +-- +------------------------------------------------------------------------------------ +-- +-- Program CALL/RETURN stack +-- +-- Provided the counter and memory for a 32 deep stack supporting nested +-- subroutine calls to a depth of 31 levels. +-- +------------------------------------------------------------------------------------ +-- + -- Stack memory is 32 locations of 10-bit single port. + + stack_ram_inv: INV -- Inverter should be implemented in the WE to RAM + port map( I => t_state, + O => stack_write_enable); + + stack_ram_loop: for i in 0 to 9 generate + -- + -- Attribute to define RAM contents during implementation + -- The information is repeated in the generic map for functional simulation + -- + attribute INIT : string; + attribute INIT of stack_bit : label is "00000000"; + -- + begin + + stack_bit: RAM32X1S + --synthesis translate_off + generic map(INIT => X"00000000") + --synthesis translate_on + port map ( D => pc(i), + WE => stack_write_enable, + WCLK => clk, + A0 => stack_address(0), + A1 => stack_address(1), + A2 => stack_address(2), + A3 => stack_address(3), + A4 => stack_address(4), + O => stack_ram_data(i)); + + stack_flop: FD + port map ( D => stack_ram_data(i), + Q => stack_pop_data(i), + C => clk); + + end generate stack_ram_loop; + + -- Stack address pointer is a 5-bit counter + + stack_count_inv: INV -- Inverter should be implemented in the CE to the flip-flops + port map( I => active_interrupt, + O => not_active_interrupt); + + stack_count_loop: for i in 0 to 4 generate + begin + + register_bit: FDRE + port map ( D => next_stack_address(i), + Q => stack_address(i), + R => internal_reset, + CE => not_active_interrupt, + C => clk); + + lsb_stack_count: if i=0 generate + -- + -- Attribute to define LUT contents during implementation + -- The information is repeated in the generic map for functional simulation + -- + attribute INIT : string; + attribute INIT of count_lut : label is "6555"; + -- + begin + + count_lut: LUT4 + --synthesis translate_off + generic map (INIT => X"6555") + --synthesis translate_on + port map( I0 => stack_address(i), + I1 => t_state, + I2 => valid_to_move, + I3 => push_or_pop_type, + O => half_stack_address(i) ); + + count_muxcy: MUXCY + port map( DI => stack_address(i), + CI => '0', + S => half_stack_address(i), + O => stack_address_carry(i)); + + count_xor: XORCY + port map( LI => half_stack_address(i), + CI => '0', + O => next_stack_address(i)); + + end generate lsb_stack_count; + + mid_stack_count: if i>0 and i<4 generate + -- + -- Attribute to define LUT contents during implementation + -- The information is repeated in the generic map for functional simulation + -- + attribute INIT : string; + attribute INIT of count_lut : label is "A999"; + -- + begin + + count_lut: LUT4 + --synthesis translate_off + generic map (INIT => X"A999") + --synthesis translate_on + port map( I0 => stack_address(i), + I1 => t_state, + I2 => valid_to_move, + I3 => call_type, + O => half_stack_address(i) ); + + count_muxcy: MUXCY + port map( DI => stack_address(i), + CI => stack_address_carry(i-1), + S => half_stack_address(i), + O => stack_address_carry(i)); + + count_xor: XORCY + port map( LI => half_stack_address(i), + CI => stack_address_carry(i-1), + O => next_stack_address(i)); + + end generate mid_stack_count; + + + msb_stack_count: if i=4 generate + -- + -- Attribute to define LUT contents during implementation + -- The information is repeated in the generic map for functional simulation + -- + attribute INIT : string; + attribute INIT of count_lut : label is "A999"; + -- + begin + + count_lut: LUT4 + --synthesis translate_off + generic map (INIT => X"A999") + --synthesis translate_on + port map( I0 => stack_address(i), + I1 => t_state, + I2 => valid_to_move, + I3 => call_type, + O => half_stack_address(i) ); + + count_xor: XORCY + port map( LI => half_stack_address(i), + CI => stack_address_carry(i-1), + O => next_stack_address(i)); + + end generate msb_stack_count; + + end generate stack_count_loop; + +-- +------------------------------------------------------------------------------------ +-- +-- End of description for KCPSM3 macro. +-- +------------------------------------------------------------------------------------ +-- +--********************************************************************************** +-- Code for simulation purposes only after this line +--********************************************************************************** +-- +------------------------------------------------------------------------------------ +-- +-- Code for simulation. +-- +-- Disassemble the instruction codes to form a text string variable for display. +-- Determine status of reset and flags and present in the form of a text string. +-- Provide a local variables to simulate the contents of each register and scratch +-- pad memory location. +-- +------------------------------------------------------------------------------------ +-- + --All of this section is ignored during synthesis. + --synthesis translate off + + simulation: process (clk, instruction) + -- + --complete instruction decode + -- + variable kcpsm3_opcode : string(1 to 19); + -- + --Status of flags and processor + -- + variable kcpsm3_status : string(1 to 13):= "NZ, NC, Reset"; + + -- + --contents of each register + -- + variable s0_contents : std_logic_vector(7 downto 0):=X"00"; + variable s1_contents : std_logic_vector(7 downto 0):=X"00"; + variable s2_contents : std_logic_vector(7 downto 0):=X"00"; + variable s3_contents : std_logic_vector(7 downto 0):=X"00"; + variable s4_contents : std_logic_vector(7 downto 0):=X"00"; + variable s5_contents : std_logic_vector(7 downto 0):=X"00"; + variable s6_contents : std_logic_vector(7 downto 0):=X"00"; + variable s7_contents : std_logic_vector(7 downto 0):=X"00"; + variable s8_contents : std_logic_vector(7 downto 0):=X"00"; + variable s9_contents : std_logic_vector(7 downto 0):=X"00"; + variable sa_contents : std_logic_vector(7 downto 0):=X"00"; + variable sb_contents : std_logic_vector(7 downto 0):=X"00"; + variable sc_contents : std_logic_vector(7 downto 0):=X"00"; + variable sd_contents : std_logic_vector(7 downto 0):=X"00"; + variable se_contents : std_logic_vector(7 downto 0):=X"00"; + variable sf_contents : std_logic_vector(7 downto 0):=X"00"; + -- + --contents of each scratch pad memory location + -- + variable spm00_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm01_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm02_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm03_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm04_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm05_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm06_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm07_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm08_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm09_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm0a_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm0b_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm0c_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm0d_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm0e_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm0f_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm10_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm11_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm12_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm13_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm14_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm15_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm16_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm17_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm18_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm19_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm1a_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm1b_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm1c_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm1d_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm1e_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm1f_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm20_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm21_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm22_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm23_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm24_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm25_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm26_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm27_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm28_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm29_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm2a_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm2b_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm2c_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm2d_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm2e_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm2f_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm30_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm31_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm32_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm33_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm34_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm35_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm36_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm37_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm38_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm39_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm3a_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm3b_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm3c_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm3d_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm3e_contents : std_logic_vector(7 downto 0):=X"00"; + variable spm3f_contents : std_logic_vector(7 downto 0):=X"00"; + -- + --temporary variables + -- + variable sx_decode : string(1 to 2); --sX register specification + variable sy_decode : string(1 to 2); --sY register specification + variable kk_decode : string(1 to 2); --constant value specification + variable aaa_decode : string(1 to 3); --address specification + -- + -------------------------------------------------------------------------------- + -- + -- Function to convert 4-bit binary nibble to hexadecimal character + -- + -------------------------------------------------------------------------------- + -- + function hexcharacter (nibble: std_logic_vector(3 downto 0)) + return character is + variable hex: character; + begin + case nibble is + when "0000" => hex := '0'; + when "0001" => hex := '1'; + when "0010" => hex := '2'; + when "0011" => hex := '3'; + when "0100" => hex := '4'; + when "0101" => hex := '5'; + when "0110" => hex := '6'; + when "0111" => hex := '7'; + when "1000" => hex := '8'; + when "1001" => hex := '9'; + when "1010" => hex := 'A'; + when "1011" => hex := 'B'; + when "1100" => hex := 'C'; + when "1101" => hex := 'D'; + when "1110" => hex := 'E'; + when "1111" => hex := 'F'; + when others => hex := 'x'; + end case; + return hex; + end hexcharacter; + -- + -------------------------------------------------------------------------------- + -- + begin + + -- decode first register + sx_decode(1) := 's'; + sx_decode(2) := hexcharacter(instruction(11 downto 8)); + + -- decode second register + sy_decode(1) := 's'; + sy_decode(2) := hexcharacter(instruction(7 downto 4)); + + -- decode constant value + kk_decode(1) := hexcharacter(instruction(7 downto 4)); + kk_decode(2) := hexcharacter(instruction(3 downto 0)); + + -- address value + aaa_decode(1) := hexcharacter("00" & instruction(9 downto 8)); + aaa_decode(2) := hexcharacter(instruction(7 downto 4)); + aaa_decode(3) := hexcharacter(instruction(3 downto 0)); + + -- decode instruction + case instruction(17 downto 12) is + when "000000" => kcpsm3_opcode := "LOAD " & sx_decode & ',' & kk_decode & " "; + when "000001" => kcpsm3_opcode := "LOAD " & sx_decode & ',' & sy_decode & " "; + when "001010" => kcpsm3_opcode := "AND " & sx_decode & ',' & kk_decode & " "; + when "001011" => kcpsm3_opcode := "AND " & sx_decode & ',' & sy_decode & " "; + when "001100" => kcpsm3_opcode := "OR " & sx_decode & ',' & kk_decode & " "; + when "001101" => kcpsm3_opcode := "OR " & sx_decode & ',' & sy_decode & " "; + when "001110" => kcpsm3_opcode := "XOR " & sx_decode & ',' & kk_decode & " "; + when "001111" => kcpsm3_opcode := "XOR " & sx_decode & ',' & sy_decode & " "; + when "010010" => kcpsm3_opcode := "TEST " & sx_decode & ',' & kk_decode & " "; + when "010011" => kcpsm3_opcode := "TEST " & sx_decode & ',' & sy_decode & " "; + when "011000" => kcpsm3_opcode := "ADD " & sx_decode & ',' & kk_decode & " "; + when "011001" => kcpsm3_opcode := "ADD " & sx_decode & ',' & sy_decode & " "; + when "011010" => kcpsm3_opcode := "ADDCY " & sx_decode & ',' & kk_decode & " "; + when "011011" => kcpsm3_opcode := "ADDCY " & sx_decode & ',' & sy_decode & " "; + when "011100" => kcpsm3_opcode := "SUB " & sx_decode & ',' & kk_decode & " "; + when "011101" => kcpsm3_opcode := "SUB " & sx_decode & ',' & sy_decode & " "; + when "011110" => kcpsm3_opcode := "SUBCY " & sx_decode & ',' & kk_decode & " "; + when "011111" => kcpsm3_opcode := "SUBCY " & sx_decode & ',' & sy_decode & " "; + when "010100" => kcpsm3_opcode := "COMPARE " & sx_decode & ',' & kk_decode & " "; + when "010101" => kcpsm3_opcode := "COMPARE " & sx_decode & ',' & sy_decode & " "; + when "100000" => + case instruction(3 downto 0) is + when "0110" => kcpsm3_opcode := "SL0 " & sx_decode & " "; + when "0111" => kcpsm3_opcode := "SL1 " & sx_decode & " "; + when "0100" => kcpsm3_opcode := "SLX " & sx_decode & " "; + when "0000" => kcpsm3_opcode := "SLA " & sx_decode & " "; + when "0010" => kcpsm3_opcode := "RL " & sx_decode & " "; + when "1110" => kcpsm3_opcode := "SR0 " & sx_decode & " "; + when "1111" => kcpsm3_opcode := "SR1 " & sx_decode & " "; + when "1010" => kcpsm3_opcode := "SRX " & sx_decode & " "; + when "1000" => kcpsm3_opcode := "SRA " & sx_decode & " "; + when "1100" => kcpsm3_opcode := "RR " & sx_decode & " "; + when others => kcpsm3_opcode := "Invalid Instruction"; + end case; + when "101100" => kcpsm3_opcode := "OUTPUT " & sx_decode & ',' & kk_decode & " "; + when "101101" => kcpsm3_opcode := "OUTPUT " & sx_decode & ",(" & sy_decode & ") "; + when "000100" => kcpsm3_opcode := "INPUT " & sx_decode & ',' & kk_decode & " "; + when "000101" => kcpsm3_opcode := "INPUT " & sx_decode & ",(" & sy_decode & ") "; + when "101110" => kcpsm3_opcode := "STORE " & sx_decode & ',' & kk_decode & " "; + when "101111" => kcpsm3_opcode := "STORE " & sx_decode & ",(" & sy_decode & ") "; + when "000110" => kcpsm3_opcode := "FETCH " & sx_decode & ',' & kk_decode & " "; + when "000111" => kcpsm3_opcode := "FETCH " & sx_decode & ",(" & sy_decode & ") "; + when "110100" => kcpsm3_opcode := "JUMP " & aaa_decode & " "; + when "110101" => + case instruction(11 downto 10) is + when "00" => kcpsm3_opcode := "JUMP Z," & aaa_decode & " "; + when "01" => kcpsm3_opcode := "JUMP NZ," & aaa_decode & " "; + when "10" => kcpsm3_opcode := "JUMP C," & aaa_decode & " "; + when "11" => kcpsm3_opcode := "JUMP NC," & aaa_decode & " "; + when others => kcpsm3_opcode := "Invalid Instruction"; + end case; + when "110000" => kcpsm3_opcode := "CALL " & aaa_decode & " "; + when "110001" => + case instruction(11 downto 10) is + when "00" => kcpsm3_opcode := "CALL Z," & aaa_decode & " "; + when "01" => kcpsm3_opcode := "CALL NZ," & aaa_decode & " "; + when "10" => kcpsm3_opcode := "CALL C," & aaa_decode & " "; + when "11" => kcpsm3_opcode := "CALL NC," & aaa_decode & " "; + when others => kcpsm3_opcode := "Invalid Instruction"; + end case; + when "101010" => kcpsm3_opcode := "RETURN "; + when "101011" => + case instruction(11 downto 10) is + when "00" => kcpsm3_opcode := "RETURN Z "; + when "01" => kcpsm3_opcode := "RETURN NZ "; + when "10" => kcpsm3_opcode := "RETURN C "; + when "11" => kcpsm3_opcode := "RETURN NC "; + when others => kcpsm3_opcode := "Invalid Instruction"; + end case; + when "111000" => + case instruction(0) is + when '0' => kcpsm3_opcode := "RETURNI DISABLE "; + when '1' => kcpsm3_opcode := "RETURNI ENABLE "; + when others => kcpsm3_opcode := "Invalid Instruction"; + end case; + when "111100" => + case instruction(0) is + when '0' => kcpsm3_opcode := "DISABLE INTERRUPT "; + when '1' => kcpsm3_opcode := "ENABLE INTERRUPT "; + when others => kcpsm3_opcode := "Invalid Instruction"; + end case; + when others => kcpsm3_opcode := "Invalid Instruction"; + end case; + + if clk'event and clk='1' then + + --reset and flag status information + if reset='1' or reset_delay='1' then + kcpsm3_status := "NZ, NC, Reset"; + else + kcpsm3_status(7 to 13) := " "; + if flag_enable='1' then + if zero_carry='1' then + kcpsm3_status(1 to 4) := " Z, "; + else + kcpsm3_status(1 to 4) := "NZ, "; + end if; + if sel_carry(3)='1' then + kcpsm3_status(5 to 6) := " C"; + else + kcpsm3_status(5 to 6) := "NC"; + end if; + end if; + end if; + + --simulation of register contents + if register_enable='1' then + case instruction(11 downto 8) is + when "0000" => s0_contents := alu_result; + when "0001" => s1_contents := alu_result; + when "0010" => s2_contents := alu_result; + when "0011" => s3_contents := alu_result; + when "0100" => s4_contents := alu_result; + when "0101" => s5_contents := alu_result; + when "0110" => s6_contents := alu_result; + when "0111" => s7_contents := alu_result; + when "1000" => s8_contents := alu_result; + when "1001" => s9_contents := alu_result; + when "1010" => sa_contents := alu_result; + when "1011" => sb_contents := alu_result; + when "1100" => sc_contents := alu_result; + when "1101" => sd_contents := alu_result; + when "1110" => se_contents := alu_result; + when "1111" => sf_contents := alu_result; + when others => null; + end case; + end if; + + --simulation of scratch pad memory contents + if memory_enable='1' then + case second_operand(5 downto 0) is + when "000000" => spm00_contents := sx; + when "000001" => spm01_contents := sx; + when "000010" => spm02_contents := sx; + when "000011" => spm03_contents := sx; + when "000100" => spm04_contents := sx; + when "000101" => spm05_contents := sx; + when "000110" => spm06_contents := sx; + when "000111" => spm07_contents := sx; + when "001000" => spm08_contents := sx; + when "001001" => spm09_contents := sx; + when "001010" => spm0a_contents := sx; + when "001011" => spm0b_contents := sx; + when "001100" => spm0c_contents := sx; + when "001101" => spm0d_contents := sx; + when "001110" => spm0e_contents := sx; + when "001111" => spm0f_contents := sx; + when "010000" => spm10_contents := sx; + when "010001" => spm11_contents := sx; + when "010010" => spm12_contents := sx; + when "010011" => spm13_contents := sx; + when "010100" => spm14_contents := sx; + when "010101" => spm15_contents := sx; + when "010110" => spm16_contents := sx; + when "010111" => spm17_contents := sx; + when "011000" => spm18_contents := sx; + when "011001" => spm19_contents := sx; + when "011010" => spm1a_contents := sx; + when "011011" => spm1b_contents := sx; + when "011100" => spm1c_contents := sx; + when "011101" => spm1d_contents := sx; + when "011110" => spm1e_contents := sx; + when "011111" => spm1f_contents := sx; + when "100000" => spm20_contents := sx; + when "100001" => spm21_contents := sx; + when "100010" => spm22_contents := sx; + when "100011" => spm23_contents := sx; + when "100100" => spm24_contents := sx; + when "100101" => spm25_contents := sx; + when "100110" => spm26_contents := sx; + when "100111" => spm27_contents := sx; + when "101000" => spm28_contents := sx; + when "101001" => spm29_contents := sx; + when "101010" => spm2a_contents := sx; + when "101011" => spm2b_contents := sx; + when "101100" => spm2c_contents := sx; + when "101101" => spm2d_contents := sx; + when "101110" => spm2e_contents := sx; + when "101111" => spm2f_contents := sx; + when "110000" => spm30_contents := sx; + when "110001" => spm31_contents := sx; + when "110010" => spm32_contents := sx; + when "110011" => spm33_contents := sx; + when "110100" => spm34_contents := sx; + when "110101" => spm35_contents := sx; + when "110110" => spm36_contents := sx; + when "110111" => spm37_contents := sx; + when "111000" => spm38_contents := sx; + when "111001" => spm39_contents := sx; + when "111010" => spm3a_contents := sx; + when "111011" => spm3b_contents := sx; + when "111100" => spm3c_contents := sx; + when "111101" => spm3d_contents := sx; + when "111110" => spm3e_contents := sx; + when "111111" => spm3f_contents := sx; + when others => null; + end case; + end if; + + end if; + + end process simulation; + + --synthesis translate on +-- +--********************************************************************************** +-- End of simulation code. +--********************************************************************************** +-- +-- +end low_level_definition; +-- +------------------------------------------------------------------------------------ +-- +-- END OF FILE KCPSM3.VHD +-- +------------------------------------------------------------------------------------ diff --git a/keyboard.vhd b/keyboard.vhd new file mode 100755 index 0000000..86904a7 --- /dev/null +++ b/keyboard.vhd @@ -0,0 +1,206 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 15:52:22 12/30/2008 +-- Design Name: +-- Module Name: toplevel - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +library UNISIM; +use UNISIM.VComponents.all; + +entity keyboard is + + port ( + -- PS/2 Interface + PS2_CLK : inout std_logic; + PS2_DATA : inout std_logic; + -- Z80 interface + CLK_16M : in std_logic; + IORQ_n : in std_logic; + RD_n, WR_n : in std_logic; + DATA_I : in std_logic_vector(7 downto 0); + DATA_O : out std_logic_vector(7 downto 0); + -- DEBUG + DEBUG : out std_logic_vector(7 downto 0) +-- DEBUGLED : out std_logic_vector(7 downto 0) + ); + +end keyboard; + +architecture Behavioral of keyboard is +type states is (ST_RESET, ST_IDLE, ST_READ, ST_PARITY, ST_ERROR, ST_STOP); +signal state : states := ST_RESET; +signal parity_r, up_r, ext_r : std_logic := '0'; +signal key_in_r : std_logic_vector(7 downto 0); +signal count : unsigned(2 downto 0); +type line_lut_t is array (0 to 255) of integer range 0 to 9; +type bit_lut_t is array (0 to 255) of integer range 0 to 7; +signal line_lut : line_lut_t; +signal bit_lut : bit_lut_t; + +signal ps2clk_s, ps2data_s : std_logic_vector(2 downto 0) := "111"; +signal debug_evt_counter : std_logic_vector(7 downto 0) := X"00"; + +type key_buffer_t is array (0 to 9) of std_logic_vector(7 downto 0); +signal key_buffer : key_buffer_t; +signal keyb_row_r : unsigned(3 downto 0) := to_unsigned(0, 4); +signal lastin_r : std_logic_vector(1 downto 0) := "00"; +begin -- Behavioral + -- 0 1 2 3 4 5 6 7 8 9 A B C D E F + line_lut <= (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, -- 0_ + 0, 0, 0, 0, 0, 5, 6, 0, 0, 0, 2, 3, 4, 4, 6, 0, -- 1_ + 0, 7, 1, 2, 3, 7, 5, 0, 0, 7, 7, 1, 1, 7, 1, 0, -- 2_ + 0, 2, 1, 1, 7, 2, 2, 0, 0, 0, 3, 2, 3, 3, 4, 0, -- 3_ + + 0, 4, 3, 4, 5, 6, 5, 0, 0, 5, 6, 4, 5, 6, 8, 0, -- 4_ + 0, 0, 6, 0, 6, 0, 0, 0, 0, 0, 8, 7, 0, 5, 0, 0, -- 5_ + 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, -- 6_ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -- 7_ + + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -- e0 0_ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -- e0 1_ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -- e0 2_ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -- e0 3_ + + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -- e0 4_ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -- e0 5_ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, -- e0 6_ + 0, 0, 3, 0, 4, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); -- e0 7_ + + -- 0 1 2 3 4 5 6 7 8 9 A B C D E F + bit_lut <= (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, -- 0_ + 0, 0, 4, 0, 0, 4, 4, 0, 0, 0, 5, 4, 4, 3, 3, 0, -- 1_ + 0, 3, 4, 3, 3, 2, 3, 0, 0, 4, 1, 3, 5, 5, 2, 0, -- 2_ + 0, 1, 1, 0, 0, 4, 2, 0, 0, 0, 1, 0, 5, 2, 2, 0, -- 3_ + + 0, 1, 0, 5, 5, 2, 2, 0, 0, 1, 1, 0, 0, 5, 2, 0, -- 4_ + 0, 0, 0, 0, 6, 0, 0, 0, 0, 4, 1, 6, 0, 6, 0, 0, -- 5_ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -- 6_ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -- 7_ + + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -- e0 0_ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -- e0 1_ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -- e0 2_ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -- e0 3_ + + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -- e0 4_ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -- e0 5_ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 0, 0, -- e0 6_ + 0, 0, 6, 0, 6, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); -- e0 7_ + + z80bus: process(CLK_16M) + begin + if rising_edge(CLK_16M) then + if (IORQ_n = '0') and (WR_n = '0') then + if (DATA_I(0) = '0') and (lastin_r(0) = '1') then + if keyb_row_r < 9 then + keyb_row_r <= keyb_row_r + 1; + end if; + elsif (DATA_I(1) = '0') and (lastin_r(1) = '1') then + keyb_row_r <= to_unsigned(0, keyb_row_r'length); + end if; + lastin_r <= DATA_I(1 downto 0); + end if; + end if; + end process; + + DATA_O <= key_buffer(to_integer(keyb_row_r)); + + process (CLK_16M) + begin + if rising_edge(CLK_16M) then + ps2clk_s <= ps2clk_s(1 downto 0) & PS2_CLK; + ps2data_s <= ps2data_s(1 downto 0) & PS2_DATA; + end if; + end process; + + fsm: process (CLK_16M) + variable next_state : states; + variable line_v : integer range 0 to 8; + variable bit_v : integer range 0 to 7; + begin + if rising_edge(CLK_16M) then + next_state := state; + case state is + when ST_RESET => + key_buffer <= (X"FF", X"FF", X"FF", X"FF", + X"FF", X"FF", X"FF", X"FF", + X"FF", X"FF"); + next_state := ST_IDLE; + when ST_IDLE => + if (ps2clk_s(2) = '1') and (ps2clk_s(1) = '0') then -- falling edge + if ps2data_s(2) = '0' then + count <= to_unsigned(0, count'length); + parity_r <= '0'; + next_state := ST_READ; + end if; + end if; + when ST_READ => + if (ps2clk_s(2) = '1') and (ps2clk_s(1) = '0') then -- falling edge + key_in_r(to_integer(count)) <= ps2data_s(2); + parity_r <= parity_r xor ps2data_s(2); + if count = 7 then + next_state := ST_PARITY; + else + count <= count + 1; + end if; + end if; + when ST_PARITY => + if (ps2clk_s(2) = '1') and (ps2clk_s(1) = '0') then -- falling edge + if parity_r = ps2data_s(2) then +-- ext_r <= '0'; +-- up_r <= '0'; + next_state := ST_ERROR; + else + if key_in_r = X"E0" then + ext_r <= '1'; + elsif key_in_r = X"F0" then + up_r <= '1'; + else + -- process key code + line_v := line_lut(conv_integer(ext_r & key_in_r(6 downto 0))); + bit_v := bit_lut(conv_integer(ext_r & key_in_r(6 downto 0))); + if not ((line_v = 0) and (bit_v = 0)) then + key_buffer(line_v)(bit_v) <= up_r; + end if; + ext_r <= '0'; + up_r <= '0'; + end if; + next_state := ST_STOP; + end if; + end if; + when ST_ERROR => + debug_evt_counter <= debug_evt_counter + 1; + next_state := ST_IDLE; + when ST_STOP => + next_state := ST_IDLE; + when others => null; + end case; + state <= next_state; + end if; + end process; + +-- DEBUGLED <= debug_evt_counter; + + PS2_CLK <= 'Z'; + PS2_DATA <= 'Z'; +end Behavioral; diff --git a/memory.vhd b/memory.vhd new file mode 100755 index 0000000..a752e48 --- /dev/null +++ b/memory.vhd @@ -0,0 +1,128 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 15:22:46 12/30/2008 +-- Design Name: +-- Module Name: memory - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity memory is + Port ( + -- interface to Z80 bus + DATA_I : in STD_LOGIC_VECTOR (7 downto 0); + DATA_O : out STD_LOGIC_VECTOR (7 downto 0); + ADDR_I : in STD_LOGIC_VECTOR (15 downto 0); + RD_N : in STD_LOGIC; + WR_N : in STD_LOGIC; + MREQ_N : in STD_LOGIC; + CLK : in STD_LOGIC; + CLKEN : in STD_LOGIC; + -- interface to video generator + VID_DATA_O : out STD_LOGIC_VECTOR(7 downto 0); + VID_ADDR_I : in STD_LOGIC_VECTOR(9 downto 0); + VID_CLK : in STD_LOGIC); +end memory; + +architecture Behavioral of memory is +component monitorrom IS + port ( clka: IN std_logic; + addra: IN std_logic_VECTOR(10 downto 0); + douta: OUT std_logic_VECTOR(7 downto 0); + ena: in std_logic); +END component; + +component basic_rom + port ( + clka : IN std_logic; + addra : IN std_logic_VECTOR(12 downto 0); + douta : OUT std_logic_VECTOR(7 downto 0); + ena : in std_logic); +end component; + +component ram2kx8 IS + port ( clka: IN std_logic; + dina: IN std_logic_VECTOR(7 downto 0); + addra: IN std_logic_VECTOR(10 downto 0); + wea: IN std_logic_VECTOR(0 downto 0); + douta: OUT std_logic_VECTOR(7 downto 0); + ena: in std_logic; + clkb: IN std_logic; + dinb: IN std_logic_VECTOR(7 downto 0); + addrb: IN std_logic_VECTOR(10 downto 0); + web: IN std_logic_VECTOR(0 downto 0); + doutb: OUT std_logic_VECTOR(7 downto 0)); +END component; + +signal monitorrom_data, basicrom_data, ram2kx8_1_dout, ram2kx8_2_dout, ram2kx8_1_doutb: std_logic_vector(7 downto 0); +signal ram2kx8_1_addrb : std_logic_vector(10 downto 0); +signal ram2kx8_1_we, ram2kx8_2_we: std_logic_vector(0 downto 0); +begin +monitorrom_inst: monitorrom port map( clka => CLK, + addra => ADDR_I(10 downto 0), + douta => monitorrom_data, + ena => CLKEN); + +basicrom_inst : basic_rom port map ( + clka => CLK, + addra => ADDR_I(12 downto 0), + douta => basicrom_data, + ena => CLKEN); + +ram2kx8_1_we(0) <= '1' when (WR_N = '0') and (ADDR_I(15 downto 11) = "00001") and (MREQ_N = '0') else '0'; +ram2kx8_2_we(0) <= '1' when (WR_N = '0') and (ADDR_I(15 downto 11) = "00010") and (MREQ_N = '0') else '0'; +ram2kx8_1_addrb <= '0' & VID_ADDR_I; + +ram2kx8_inst_1: ram2kx8 port map( clka => CLK, + dina => DATA_I, + addra => ADDR_I(10 downto 0), + wea => ram2kx8_1_we, + douta => ram2kx8_1_dout, + ena => CLKEN, + clkb => VID_CLK, + dinb => "00000000", + addrb => ram2kx8_1_addrb, + web => "0", + doutb => ram2kx8_1_doutb); + +ram2kx8_inst_2: ram2kx8 port map( clka => CLK, + dina => DATA_I, + addra => ADDR_I(10 downto 0), + wea => ram2kx8_2_we, + douta => ram2kx8_2_dout, + ena => CLKEN, + clkb => VID_CLK, + dinb => "00000000", + addrb => "00000000000", + web => "0", + doutb => open); + +DATA_O <= monitorrom_data when ADDR_I(15 downto 11) = "00000" else + ram2kx8_1_dout when ADDR_I(15 downto 11) = "00001" else + ram2kx8_2_dout when ADDR_I(15 downto 11) = "00010" else + basicrom_data when ADDR_I(15 downto 13) = "111" else + "XXXXXXXX"; + +VID_DATA_O <= ram2kx8_1_doutb; +end Behavioral; + diff --git a/nascom2.prj b/nascom2.prj new file mode 100755 index 0000000..02b364b --- /dev/null +++ b/nascom2.prj @@ -0,0 +1,23 @@ +vhdl work memory.vhd +vhdl work coregen/charrom.vhd +vhdl work coregen/monitorrom.vhd +vhdl work coregen/basic_rom.vhd +vhdl work coregen/ram2kx8.vhd +vhdl work coregen/dcm_in50.vhd +vhdl work toplevel.vhd +vhdl work T80a.vhd +vhdl work T80.vhd +vhdl work T80_ALU.vhd +vhdl work T80_MCode.vhd +vhdl work T80_RegX.vhd +vhdl work T80_Pack.vhd +vhdl work T80se.vhd +vhdl work video.vhd +vhdl work videogen.vhd +vhdl work syncgen.vhd +vhdl work keyboard.vhd +vhdl work uart.vhd +vhdl work kcpsm3.vhd +vhdl work uartprog.vhd +vhdl work fifo16x8.vhd +vhdl work spi.vhd \ No newline at end of file diff --git a/nascom2.ucf b/nascom2.ucf new file mode 100755 index 0000000..2e82451 --- /dev/null +++ b/nascom2.ucf @@ -0,0 +1,159 @@ +################################################### +# TIMING CONSTRAINTS +################################################### +# System Clock +NET "CLKIN_50M" LOC = "E12"| IOSTANDARD = LVCMOS33; +NET "CLKIN_50M" PERIOD = 20 ns HIGH 40 %; +#NET "CLKIN_50M" TNM_NET = "CLKIN_50M"; +# VGA +INST "BLUE<0>" TNM = "VGA"; +INST "BLUE<1>" TNM = "VGA"; +INST "BLUE<2>" TNM = "VGA"; +INST "BLUE<3>" TNM = "VGA"; +INST "GREEN<0>" TNM = "VGA"; +INST "GREEN<1>" TNM = "VGA"; +INST "GREEN<2>" TNM = "VGA"; +INST "GREEN<3>" TNM = "VGA"; +INST "HSYNC" TNM = "VGA"; +INST "RED<0>" TNM = "VGA"; +INST "RED<1>" TNM = "VGA"; +INST "RED<2>" TNM = "VGA"; +INST "RED<3>" TNM = "VGA"; +INST "VSYNC" TNM = "VGA"; +TIMEGRP "VGA" OFFSET = OUT 5.2 ns AFTER "CLKIN_50M" ; +# Z80 BUS +#INST "ADDR<0>" TNM = "Z80BUS"; +#INST "ADDR<1>" TNM = "Z80BUS"; +#INST "ADDR<10>" TNM = "Z80BUS"; +#INST "ADDR<11>" TNM = "Z80BUS"; +#INST "ADDR<12>" TNM = "Z80BUS"; +#INST "ADDR<13>" TNM = "Z80BUS"; +#INST "ADDR<14>" TNM = "Z80BUS"; +#INST "ADDR<15>" TNM = "Z80BUS"; +#INST "ADDR<2>" TNM = "Z80BUS"; +#INST "ADDR<3>" TNM = "Z80BUS"; +#INST "ADDR<4>" TNM = "Z80BUS"; +#INST "ADDR<5>" TNM = "Z80BUS"; +#INST "ADDR<6>" TNM = "Z80BUS"; +#INST "ADDR<7>" TNM = "Z80BUS"; +#INST "ADDR<8>" TNM = "Z80BUS"; +#INST "ADDR<9>" TNM = "Z80BUS"; +#INST "BUSAK_n" TNM = "Z80BUS"; +#INST "BUSRQ_n" TNM = "Z80BUS"; +#INST "DATA<0>" TNM = "Z80BUS"; +#INST "DATA<1>" TNM = "Z80BUS"; +#INST "DATA<2>" TNM = "Z80BUS"; +#INST "DATA<3>" TNM = "Z80BUS"; +#INST "DATA<4>" TNM = "Z80BUS"; +#INST "DATA<5>" TNM = "Z80BUS"; +#INST "DATA<6>" TNM = "Z80BUS"; +#INST "DATA<7>" TNM = "Z80BUS"; +#INST "HALT_n" TNM = "Z80BUS"; +#INST "INT_n" TNM = "Z80BUS"; +#INST "IORQ_n" TNM = "Z80BUS"; +#INST "M1_n" TNM = "Z80BUS"; +#INST "NMI_n" TNM = "Z80BUS"; +#INST "RD_n" TNM = "Z80BUS"; +#INST "RFSH_n" TNM = "Z80BUS"; +#INST "WAIT_n" TNM = "Z80BUS"; +#INST "WR_n" TNM = "Z80BUS"; +#TIMEGRP "Z80BUS" OFFSET = IN 10 ns BEFORE "CLKIN_50M" ; +#TIMEGRP "Z80BUS" OFFSET = OUT 10 ns AFTER "CLKIN_50M" ; + +################################################### +# LOCATION CONSTRAINTS +################################################### +# For S3AN-Board +# VGA +NET "RED<3>" LOC = "C8" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; +NET "RED<2>" LOC = "B8" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; +NET "RED<1>" LOC = "B3" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; +NET "RED<0>" LOC = "A3" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; +NET "GREEN<3>" LOC = "D6" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; +NET "GREEN<2>" LOC = "C6" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; +NET "GREEN<1>" LOC = "D5" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; +NET "GREEN<0>" LOC = "C5" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; +NET "BLUE<3>" LOC = "C9" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; +NET "BLUE<2>" LOC = "B9" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; +NET "BLUE<1>" LOC = "D7" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; +NET "BLUE<0>" LOC = "C7" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; +NET "HSYNC" LOC = "C11" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; +NET "VSYNC" LOC = "B11" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; +# Z80BUS -> FX2 connector +#NET "ADDR<0>" LOC = "A13" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW; +#NET "ADDR<1>" LOC = "B13" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW; +#NET "ADDR<2>" LOC = "A14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW; +#NET "ADDR<3>" LOC = "B15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW; +#NET "ADDR<4>" LOC = "A15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW; +#NET "ADDR<5>" LOC = "A16" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW; +#NET "ADDR<6>" LOC = "A17" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW; +#NET "ADDR<7>" LOC = "B17" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW; +#NET "ADDR<8>" LOC = "A18" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW; +#NET "ADDR<9>" LOC = "C18" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW; +#NET "ADDR<10>" LOC = "A19" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW; +#NET "ADDR<11>" LOC = "B19" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW; +#NET "ADDR<12>" LOC = "A20" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW; +#NET "ADDR<13>" LOC = "B20" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW; +#NET "ADDR<14>" LOC = "C19" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW; +#NET "ADDR<15>" LOC = "D19" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW; +#NET "DATA<0>" LOC = "D18" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW; +#NET "DATA<1>" LOC = "E17" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW; +#NET "DATA<2>" LOC = "D20" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW; +#NET "DATA<3>" LOC = "D21" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW; +#NET "DATA<4>" LOC = "D22" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW; +#NET "DATA<5>" LOC = "E22" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW; +#NET "DATA<6>" LOC = "F18" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW; +#NET "DATA<7>" LOC = "F19" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW; +#NET "BUSAK_n" LOC = "F20" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW; +#NET "BUSRQ_n" LOC = "E20" | IOSTANDARD = LVTTL; +#NET "HALT_n" LOC = "G20" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW; +#NET "INT_n" LOC = "G19" | IOSTANDARD = LVTTL; +#NET "IORQ_n" LOC = "H19" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW; +#NET "M1_n" LOC = "J18" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW; +#NET "NMI_n" LOC = "K18" | IOSTANDARD = LVTTL; +#NET "RD_n" LOC = "K17" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW; +#NET "WR_n" LOC = "K19" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW; +#NET "RFSH_n" LOC = "K20" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW; +#NET "WAIT_n" LOC = "L19" | IOSTANDARD = LVTTL; +# PS/2 Keyboard +NET "PS2_CLK1" LOC = "W12" | IOSTANDARD = LVCMOS33 | PULLUP | DRIVE = 8 | SLEW = SLOW; +NET "PS2_DATA1" LOC = "V11" | IOSTANDARD = LVCMOS33 | PULLUP | DRIVE = 8 | SLEW = SLOW; +# LEDs +NET "LED<7>" LOC = "W21" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8; +NET "LED<6>" LOC = "Y22" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8; +NET "LED<5>" LOC = "V20" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8; +NET "LED<4>" LOC = "V19" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8; +NET "LED<3>" LOC = "U19" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8; +NET "LED<2>" LOC = "U20" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8; +NET "LED<1>" LOC = "T19" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8; +NET "LED<0>" LOC = "R20" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8; +# Buttons +NET "BTN_NORTH" LOC = "T14" | IOSTANDARD = LVCMOS33 | PULLDOWN; +NET "BTN_SOUTH" LOC = "T15" | IOSTANDARD = LVCMOS33 | PULLDOWN; +NET "BTN_EAST" LOC = "T16" | IOSTANDARD = LVCMOS33 | PULLDOWN; +NET "BTN_WEST" LOC = "U15" | IOSTANDARD = LVCMOS33 | PULLDOWN; +NET "ROT_CENTER" LOC = "R13" | IOSTANDARD = LVCMOS33 | PULLDOWN; +# Switches +NET "SW<3>" LOC = "T9" | IOSTANDARD = LVCMOS33; +NET "SW<2>" LOC = "U8" | IOSTANDARD = LVCMOS33; +NET "SW<1>" LOC = "U10" | IOSTANDARD = LVCMOS33; +NET "SW<0>" LOC = "V8" | IOSTANDARD = LVCMOS33; +# SPI +NET "SPI_MISO" LOC = "AB20" | IOSTANDARD = LVCMOS33; +NET "SPI_MOSI" LOC = "AB14" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8; +NET "SPI_SCK" LOC = "AA20" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8; +NET "SPI_SS_B" LOC = "Y4" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8; +NET "DATAFLASH_WP" LOC = "C14" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8; +NET "DATAFLASH_RST" LOC = "C15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8; +# LCD interface +NET "LCD_E" LOC = "AB4" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; +NET "LCD_RS" LOC = "Y14" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; +NET "LCD_RW" LOC = "W13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; +NET "LCD_DB<7>" LOC = "Y15" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; +NET "LCD_DB<6>" LOC = "AB16" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; +NET "LCD_DB<5>" LOC = "Y16" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; +NET "LCD_DB<4>" LOC = "AA12" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; +NET "LCD_DB<3>" LOC = "AB12" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; +NET "LCD_DB<2>" LOC = "AB17" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; +NET "LCD_DB<1>" LOC = "AB18" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; +NET "LCD_DB<0>" LOC = "Y13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; \ No newline at end of file diff --git a/nascom2.xst b/nascom2.xst new file mode 100755 index 0000000..fcb747c --- /dev/null +++ b/nascom2.xst @@ -0,0 +1,15 @@ +run +-ifn nascom2.prj +-ifmt mixed +-top toplevel +-ofn nascom2.ngc +-ofmt NGC +-p xc3s700an-fgg484-4 +-opt_mode Speed +-opt_level 1 +-fsm_encoding auto +-slice_utilization_ratio 1500# +-bram_utilization_ratio 3# +-sd coregen/ +-rtlview no +-iob auto \ No newline at end of file diff --git a/nascom2_t80.mpf b/nascom2_t80.mpf new file mode 100755 index 0000000..a9f79c1 --- /dev/null +++ b/nascom2_t80.mpf @@ -0,0 +1,288 @@ +; +; Copyright Model Technology, a Mentor Graphics +; Corporation company 2006, - All rights reserved. +; +; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF +; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. +; +[Library] +std = $MODEL_TECH/../std +ieee = $MODEL_TECH/../ieee +verilog = $MODEL_TECH/../verilog +vital2000 = $MODEL_TECH/../vital2000 +std_developerskit = $MODEL_TECH/../std_developerskit +synopsys = $MODEL_TECH/../synopsys +modelsim_lib = $MODEL_TECH/../modelsim_lib + + +; VHDL Section +unisim = $MODEL_TECH/../xilinx/vhdl/unisim +simprim = $MODEL_TECH/../xilinx/vhdl/simprim +xilinxcorelib = $MODEL_TECH/../xilinx/vhdl/xilinxcorelib +aim = $MODEL_TECH/../xilinx/vhdl/aim +pls = $MODEL_TECH/../xilinx/vhdl/pls +cpld = $MODEL_TECH/../xilinx/vhdl/cpld + +; Verilog Section +unisims_ver = $MODEL_TECH/../xilinx/verilog/unisims_ver +uni9000_ver = $MODEL_TECH/../xilinx/verilog/uni9000_ver +simprims_ver = $MODEL_TECH/../xilinx/verilog/simprims_ver +xilinxcorelib_ver = $MODEL_TECH/../xilinx/verilog/xilinxcorelib_ver +aim_ver = $MODEL_TECH/../xilinx/verilog/aim_ver +cpld_ver = $MODEL_TECH/../xilinx/verilog/cpld_ver + +work = work +[vcom] +; Turn on VHDL-1993 as the default. Normally is off. +VHDL93 = 1 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn off unbound-component warnings. Default is on. +; Show_Warning1 = 0 + +; Turn off process-without-a-wait-statement warnings. Default is on. +; Show_Warning2 = 0 + +; Turn off null-range warnings. Default is on. +; Show_Warning3 = 0 + +; Turn off no-space-in-time-literal warnings. Default is on. +; Show_Warning4 = 0 + +; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. +; Show_Warning5 = 0 + +; Turn off optimization for IEEE std_logic_1164 package. Default is on. +; Optimize_1164 = 0 + +; Turn on resolving of ambiguous function overloading in favor of the +; "explicit" function declaration (not the one automatically created by +; the compiler for each type declaration). Default is off. + Explicit = 1 + +; Turn off VITAL compliance checking. Default is checking on. +; NoVitalCheck = 1 + +; Ignore VITAL compliance checking errors. Default is to not ignore. +; IgnoreVitalErrors = 1 + +; Turn off VITAL compliance checking warnings. Default is to show warnings. +; Show_VitalChecksWarnings = false + +; Turn off "loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on some limited synthesis rule compliance checking. Checks only: +; -- signals used (read) by a process must be in the sensitivity list +; CheckSynthesis = 1 + +[vlog] + +; Turn off "loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on Verilog hazard checking (order-dependent accessing of global vars). +; Default is off. +; Hazard = 1 + +; Turn on converting regular Verilog identifiers to uppercase. Allows case +; insensitivity for module names. Default is no conversion. +; UpCase = 1 + +; Turns on incremental compilation of modules +; Incremental = 1 + +[vsim] +; Simulator resolution +; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. +resolution = 1ps + +; User time unit for run commands +; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the +; unit specified for Resolution. For example, if Resolution is 100ps, +; then UserTimeUnit defaults to ps. +UserTimeUnit = default + +; Default run length +RunLength = 20 ns + +; Maximum iterations that can be run without advancing simulation time +IterationLimit = 5000 + +; Directive to license manager: +; vhdl Immediately reserve a VHDL license +; vlog Immediately reserve a Verilog license +; plus Immediately reserve a VHDL and Verilog license +; nomgc Do not look for Mentor Graphics Licenses +; nomti Do not look for Model Technology Licenses +; noqueue Do not wait in the license queue when a license isn't available +; License = plus + +; Stop the simulator after an assertion message +; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal +BreakOnAssertion = 3 + +; Assertion Message Format +; %S - Severity Level +; %R - Report Message +; %T - Time of assertion +; %D - Delta +; %I - Instance or Region pathname (if available) +; %% - print '%' character +; AssertionFormat = "** %S: %R\n Timf: %T Iteration: %D%I\n" + +; Assertion File - alternate file for storing assertion messages +; AssertFile = assert.log + +; Default radix for all windows and commands... +; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned +DefaultRadix = symbolic + +; VSIM Startup command +; Startup = do startup.do + +; File for saving command transcript +TranscriptFile = transcript + +; File for saving command history +;CommandHistory = cmdhist.log + +; Specify whether paths in simulator commands should be described +; in VHDL or Verilog format. For VHDL, PathSeparator = / +; for Verilog, PathSeparator = . +PathSeparator = / + +; Specify the dataset separator for fully rooted contexts. +; The default is ':'. For example, sim:/top +; Must not be the same character as PathSeparator. +DatasetSeparator = : + +; Disable assertion messages +; IgnoreNote = 1 +; IgnoreWarning = 1 +; IgnoreError = 1 +; IgnoreFailure = 1 + +; Default force kind. May be freeze, drive, or deposit +; or in other terms, fixed, wired or charged. +; DefaultForceKind = freeze + +; If zero, open files when elaborated +; else open files on first read or write +; DelayFileOpen = 0 + +; Control VHDL files opened for write +; 0 = Buffered, 1 = Unbuffered +UnbufferedOutput = 0 + +; Control number of VHDL files open concurrently +; This number should always be less then the +; current ulimit setting for max file descriptors +; 0 = unlimited +ConcurrentFileLimit = 40 + +; This controls the number of hierarchical regions displayed as +; part of a signal name shown in the waveform window. The default +; value or a value of zero tells VSIM to display the full name. +; WaveSignalNameWidth = 0 + +; Turn off warnings from the std_logic_arith, std_logic_unsigned +; and std_logic_signed packages. +; StdArithNoWarnings = 1 + +; Turn off warnings from the IEEE numeric_std and numeric_bit +; packages. +; NumericStdNoWarnings = 1 + +; Control the format of a generate statement label. Don't quote it. +; GenerateFormat = %s__%d + +; Specify whether checkpoint files should be compressed. +; The default is to be compressed. +; CheckpointCompressMode = 0 + +; List of dynamically loaded objects for Verilog PLI applications +; Veriuser = veriuser.sl + +[lmc] +[Project] +Project_Version = 6 +Project_DefaultLib = work +Project_SortMethod = unused +Project_Files_Count = 21 +Project_File_0 = C:/vhdl/nascom2_t80/toplevel.vhd +Project_File_P_0 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1231501485 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_vopt 0 vhdl_showsource 0 vhdl_warn2 1 vhdl_explicit 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 1 compile_to work compile_order 10 dont_compile 0 cover_nosub 0 vhdl_use93 93 +Project_File_1 = C:/vhdl/nascom2_t80/T80se.vhd +Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1230996942 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_vopt 0 vhdl_showsource 0 vhdl_warn2 1 vhdl_explicit 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 1 compile_to work compile_order 13 dont_compile 0 cover_nosub 0 vhdl_use93 93 +Project_File_2 = C:/vhdl/nascom2_t80/T80.vhd +Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1230941814 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_vopt 0 vhdl_showsource 0 vhdl_warn2 1 vhdl_explicit 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 1 compile_to work compile_order 2 dont_compile 0 cover_nosub 0 vhdl_use93 93 +Project_File_3 = C:/vhdl/nascom2_t80/T80a.vhd +Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1230943266 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_vopt 0 vhdl_showsource 0 vhdl_warn2 1 vhdl_explicit 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 1 compile_to work compile_order 8 dont_compile 0 cover_nosub 0 vhdl_use93 93 +Project_File_4 = C:/vhdl/nascom2_t80/dcm_in50_sim.vhd +Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1231002309 vhdl_disableopt 0 vhdl_vital 0 vhdl_vopt 0 vhdl_warn1 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_showsource 0 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 0 compile_to work compile_order 18 cover_nosub 0 dont_compile 0 vhdl_use93 93 +Project_File_5 = C:/vhdl/nascom2_t80/syncgen.vhd +Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1230988654 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_vopt 0 vhdl_showsource 0 vhdl_warn2 1 vhdl_explicit 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 1 compile_to work compile_order 16 dont_compile 0 cover_nosub 0 vhdl_use93 93 +Project_File_6 = C:/vhdl/nascom2_t80/T80s.vhd +Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1230943564 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_vopt 0 vhdl_showsource 0 vhdl_warn2 1 vhdl_explicit 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 1 compile_to work compile_order 9 dont_compile 0 cover_nosub 0 vhdl_use93 93 +Project_File_7 = C:/vhdl/nascom2_t80/videogen.vhd +Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1231006634 vhdl_disableopt 0 vhdl_vital 0 vhdl_vopt 0 vhdl_warn1 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_showsource 0 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 0 compile_to work compile_order 15 cover_nosub 0 dont_compile 0 vhdl_use93 93 +Project_File_8 = C:/vhdl/nascom2_t80/T80_Pack.vhd +Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1230941826 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_vopt 0 vhdl_showsource 0 vhdl_warn2 1 vhdl_explicit 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 1 compile_to work compile_order 5 dont_compile 0 cover_nosub 0 vhdl_use93 93 +Project_File_9 = C:/vhdl/nascom2_t80/T80_MCode.vhd +Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1230941915 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_vopt 0 vhdl_showsource 0 vhdl_warn2 1 vhdl_explicit 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 1 compile_to work compile_order 4 dont_compile 0 cover_nosub 0 vhdl_use93 93 +Project_File_10 = C:/vhdl/nascom2_t80/T80_ALU.vhd +Project_File_P_10 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1230941923 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_vopt 0 vhdl_showsource 0 vhdl_warn2 1 vhdl_explicit 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 1 compile_to work compile_order 3 dont_compile 0 cover_nosub 0 vhdl_use93 93 +Project_File_11 = C:/vhdl/bmp_bench/sim_bmppack.vhd +Project_File_P_11 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1231008643 vhdl_disableopt 0 vhdl_vital 0 vhdl_vopt 0 vhdl_warn1 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_showsource 0 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 0 compile_to work compile_order 19 cover_nosub 0 dont_compile 0 vhdl_use93 93 +Project_File_12 = C:/vhdl/nascom2_t80/coregen/charrom.vhd +Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1230983803 vhdl_disableopt 0 vhdl_vital 0 vhdl_vopt 0 vhdl_warn1 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_showsource 0 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 0 compile_to work compile_order 17 cover_nosub 0 dont_compile 0 vhdl_use93 93 +Project_File_13 = C:/vhdl/nascom2_t80/coregen/ram2kx8.vhd +Project_File_P_13 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1230997369 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_vopt 0 vhdl_showsource 0 vhdl_warn2 1 vhdl_explicit 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 1 compile_to work compile_order 11 dont_compile 0 cover_nosub 0 vhdl_use93 93 +Project_File_14 = C:/vhdl/nascom2_t80/video.vhd +Project_File_P_14 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1230995258 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_vopt 0 vhdl_showsource 0 vhdl_warn2 1 vhdl_explicit 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 1 compile_to work compile_order 14 dont_compile 0 cover_nosub 0 vhdl_use93 93 +Project_File_15 = C:/vhdl/nascom2_t80/toplevel_tb.vhd +Project_File_P_15 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1231010153 vhdl_disableopt 0 vhdl_vital 0 vhdl_vopt 0 vhdl_warn1 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_showsource 0 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 0 compile_to work compile_order 0 cover_nosub 0 dont_compile 0 vhdl_use93 93 +Project_File_16 = C:/vhdl/nascom2_t80/coregen/monitorrom.vhd +Project_File_P_16 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1231414214 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_vopt 0 vhdl_showsource 0 vhdl_warn2 1 vhdl_explicit 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 1 compile_to work compile_order 12 dont_compile 0 cover_nosub 0 vhdl_use93 93 +Project_File_17 = C:/vhdl/nascom2_t80/T80_Reg.vhd +Project_File_P_17 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1230941873 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_vopt 0 vhdl_showsource 0 vhdl_warn2 1 vhdl_explicit 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 1 compile_to work compile_order 6 dont_compile 0 cover_nosub 0 vhdl_use93 93 +Project_File_18 = C:/vhdl/nascom2_t80/memory.vhd +Project_File_P_18 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1231511876 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_vopt 0 vhdl_showsource 0 vhdl_warn2 1 vhdl_explicit 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 1 compile_to work compile_order 1 dont_compile 0 cover_nosub 0 vhdl_use93 93 +Project_File_19 = C:/vhdl/nascom2_t80/T80_RegX.vhd +Project_File_P_19 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1230977546 vhdl_disableopt 0 vhdl_vital 0 vhdl_vopt 0 vhdl_warn1 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_showsource 0 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 0 compile_to work compile_order 7 cover_nosub 0 dont_compile 0 vhdl_use93 93 +Project_File_20 = C:/vhdl/nascom2_t80/keyboard.vhd +Project_File_P_20 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1231514379 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_vopt 0 vhdl_showsource 0 vhdl_warn2 1 vhdl_explicit 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 1 compile_to work compile_order 20 dont_compile 0 cover_nosub 0 vhdl_use93 93 +Project_Sim_Count = 0 +Project_Folder_Count = 0 +Echo_Compile_Output = 0 +Save_Compile_Report = 1 +Project_Opt_Count = 0 +ForceSoftPaths = 0 +ReOpenSourceFiles = 1 +VERILOG_DoubleClick = Edit +VERILOG_CustomDoubleClick = +VHDL_DoubleClick = Edit +VHDL_CustomDoubleClick = +PSL_DoubleClick = Edit +PSL_CustomDoubleClick = +TEXT_DoubleClick = Edit +TEXT_CustomDoubleClick = +SYSTEMC_DoubleClick = Edit +SYSTEMC_CustomDoubleClick = +TCL_DoubleClick = Edit +TCL_CustomDoubleClick = +MACRO_DoubleClick = Edit +MACRO_CustomDoubleClick = +VCD_DoubleClick = Edit +VCD_CustomDoubleClick = +SDF_DoubleClick = Edit +SDF_CustomDoubleClick = +XML_DoubleClick = Edit +XML_CustomDoubleClick = +LOGFILE_DoubleClick = Edit +LOGFILE_CustomDoubleClick = +EditorState = {tabbed horizontal 1} +Project_Major_Version = 6 +Project_Minor_Version = 2 diff --git a/nascom2_vhdl.prj b/nascom2_vhdl.prj new file mode 100755 index 0000000..17fa49d --- /dev/null +++ b/nascom2_vhdl.prj @@ -0,0 +1,23 @@ +vhdl work "C:\vhdl\nascom2_t80\memory.vhd" +vhdl work "C:\vhdl\nascom2_t80\coregen\charrom.vhd" +vhdl work "C:\vhdl\nascom2_t80\coregen\monitorrom.vhd" +vhdl work "C:\vhdl\nascom2_t80\coregen\basic_rom.vhd" +vhdl work "C:\vhdl\nascom2_t80\coregen\ram2kx8.vhd" +vhdl work "C:\vhdl\nascom2_t80\coregen\dcm_in50.vhd" +vhdl work "C:\vhdl\nascom2_t80\toplevel.vhd" +vhdl work "C:\vhdl\nascom2_t80\T80a.vhd" +vhdl work "C:\vhdl\nascom2_t80\T80.vhd" +vhdl work "C:\vhdl\nascom2_t80\T80_ALU.vhd" +vhdl work "C:\vhdl\nascom2_t80\T80_MCode.vhd" +vhdl work "C:\vhdl\nascom2_t80\T80_RegX.vhd" +vhdl work "C:\vhdl\nascom2_t80\T80_Pack.vhd" +vhdl work "C:\vhdl\nascom2_t80\T80se.vhd" +vhdl work "C:\vhdl\nascom2_t80\video.vhd" +vhdl work "C:\vhdl\nascom2_t80\videogen.vhd" +vhdl work "C:\vhdl\nascom2_t80\syncgen.vhd" +vhdl work "C:\vhdl\nascom2_t80\keyboard.vhd" +vhdl work "C:\vhdl\nascom2_t80\uart.vhd" +vhdl work "C:\vhdl\nascom2_t80\kcpsm3.vhd" +vhdl work "C:\vhdl\nascom2_t80\uartprog.vhd" +vhdl work "C:\vhdl\nascom2_t80\fifo16x8.vhd" +vhdl work "C:\vhdl\nascom2_t80\spi.vhd" diff --git a/spi.vhd b/spi.vhd new file mode 100755 index 0000000..029dff9 --- /dev/null +++ b/spi.vhd @@ -0,0 +1,99 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 15:52:22 12/30/2008 +-- Design Name: +-- Module Name: toplevel - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +library UNISIM; +use UNISIM.VComponents.all; + +entity spi is + + port ( + -- SPI + MISO : in std_logic; + MOSI, SCK : out std_logic; + -- System bus + DATA_I : in std_logic_vector(7 downto 0); + DATA_O : out std_logic_vector(7 downto 0); + START : in std_logic; + BUSY : out std_logic; + CLK : in std_logic); + +end spi; + +architecture Behavioral of spi is +type states is (ST_IDLE, ST_TRANSMIT); +signal state : states := ST_IDLE; + +signal dout_r, din_r : std_logic_vector(7 downto 0) := X"00"; +signal count : unsigned(2 downto 0) := to_unsigned(0, 3); +signal spicycle : unsigned(1 downto 0) := to_unsigned(0, 2); + +attribute iob : string; +attribute iob of MOSI, SCK : signal is "true"; +begin -- Behavioral + + fsm: process (CLK) + variable next_state : states; + begin + if rising_edge(CLK) then + next_state := state; + case state is + when ST_IDLE => + BUSY <= '0'; + SCK <= '0'; + if START = '1' then + dout_r <= DATA_I; + spicycle <= to_unsigned(0, spicycle'length); + count <= to_unsigned(0, count'length); + next_state := ST_TRANSMIT; + end if; + when ST_TRANSMIT => + BUSY <= '1'; + if spicycle = 0 then -- data out + MOSI <= dout_r(7); + dout_r <= dout_r(6 downto 0) & '0'; + elsif spicycle = 1 then -- clock up + SCK <= '1'; + elsif spicycle = 2 then -- nop + elsif spicycle = 3 then -- clock down, sample data + SCK <= '0'; + din_r(0) <= MISO; + din_r(7 downto 1) <= din_r(6 downto 0); + if count = 7 then + next_state := ST_IDLE; + else + count <= count + 1; + end if; + end if; + spicycle <= spicycle + 1; + when others => null; + end case; + state <= next_state; + end if; + end process; + + DATA_O <= din_r; + +end Behavioral; diff --git a/syncgen.vhd b/syncgen.vhd new file mode 100755 index 0000000..b3d778b --- /dev/null +++ b/syncgen.vhd @@ -0,0 +1,87 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 10:37:34 12/08/2008 +-- Design Name: +-- Module Name: syncgen - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity syncgen is + Port ( CLKPIXEL : in STD_LOGIC; + VSYNC : out STD_LOGIC; + HSYNC : out STD_LOGIC; + COLUMN : out STD_LOGIC_VECTOR (9 downto 0); + ROW : out STD_LOGIC_VECTOR (9 downto 0)); +end syncgen; + +architecture Behavioral of syncgen is +signal hsync_i, hsync_i_old: std_logic := '1'; +signal vsync_i: std_logic := '1'; +signal row_i: std_logic_vector(9 downto 0) := "0000000000"; +signal column_i: std_logic_vector(9 downto 0) := "0000000000"; +begin + hsync_p: process(CLKPIXEL) + begin + if rising_edge(CLKPIXEL) then + if column_i = 799 then + column_i <= "0000000000"; + else + column_i <= column_i + 1; + end if; + + if column_i >= 658 and column_i <= 753 then -- generate hsync pulse (one clock early, it is delayed later) + hsync_i <= '0'; -- hsync is low active + else + hsync_i <= '1'; + end if; + + HSYNC <= hsync_i; -- delay hsync 1 clock + end if; + end process; + + vsync_p: process(CLKPIXEL) + begin + if rising_edge(CLKPIXEL) then + if (hsync_i = '0') and (hsync_i_old = '1') then + if row_i = 524 then + row_i <= "0000000000"; + else + row_i <= row_i + 1; + end if; + + if row_i = 493 then -- generate vsync pulse + vsync_i <= '0'; -- vsync is low active + else + vsync_i <= '1'; + end if; + end if; + hsync_i_old <= hsync_i; + end if; + end process; + +COLUMN <= column_i; +ROW <= row_i; +VSYNC <= vsync_i; +end Behavioral; + diff --git a/test.coe b/test.coe new file mode 100755 index 0000000..3765494 --- /dev/null +++ b/test.coe @@ -0,0 +1,9 @@ +memory_initialization_radix = 16; +memory_initialization_vector = +31, 00, 10, +dd, 21, ad, de, +fd, 21, ef, be, +dd, e5, +fd, e3, +dd, e1, +76; \ No newline at end of file diff --git a/textgen.vhd b/textgen.vhd new file mode 100755 index 0000000..2f86d6e --- /dev/null +++ b/textgen.vhd @@ -0,0 +1,104 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 16:50:00 12/08/2008 +-- Design Name: +-- Module Name: textgen - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity textgen is + Port ( OE : in STD_LOGIC; + CHRX : in STD_LOGIC_VECTOR (2 downto 0); + CHRY : in STD_LOGIC_VECTOR (3 downto 0); + SCRADR : in STD_LOGIC_VECTOR (11 downto 0); + RED : out STD_LOGIC_VECTOR (3 downto 0); + GREEN : out STD_LOGIC_VECTOR (3 downto 0); + BLUE : out STD_LOGIC_VECTOR (3 downto 0); + CLK : in STD_LOGIC); +end textgen; + +architecture Behavioral of textgen is + +component charrom IS + port ( + clka: IN std_logic; + addra: IN std_logic_VECTOR(11 downto 0); + douta: OUT std_logic_VECTOR(7 downto 0)); +END component; + +component textram IS + port ( + clka: IN std_logic; + dina: IN std_logic_VECTOR(7 downto 0); + addra: IN std_logic_VECTOR(11 downto 0); + wea: IN std_logic_VECTOR(0 downto 0); + douta: OUT std_logic_VECTOR(7 downto 0)); +END component; +signal out_i, oe_i: std_logic := '0'; +signal charrom_adr, textram_adr: std_logic_vector(11 downto 0); +signal charrom_data, textram_data: std_logic_vector(7 downto 0); +signal oe_d1, oe_d2, oe_d3: std_logic := '0'; +begin + textram_adr <= SCRADR; + + textram_inst: textram port map( clka => CLK, + dina => "00000000", + addra => textram_adr, + wea => "0", + douta => textram_data); + + charrom_adr(11 downto 4) <= textram_data; + charrom_adr(3 downto 0) <= CHRY; + + charrom_inst: charrom port map( clka => CLK, + addra => charrom_adr, + douta => charrom_data); + + + process (CLK) + variable bitmap: std_logic_vector(7 downto 0) := "00000000"; + begin + if rising_edge(CLK) then + if CHRX = 3 then + bitmap := charrom_data; + end if; + out_i <= bitmap((conv_integer(2 - CHRX))); + end if; + end process; + +oe_delay: process (CLK) + begin + if rising_edge(CLK) then + oe_d1 <= OE; + oe_d2 <= oe_d1; + oe_d3 <= oe_d2; + oe_i <= oe_d3; + end if; + end process; + +RED <= (others => out_i) when oe_i = '1' else "0000"; +GREEN <= (others => out_i) when oe_i = '1' else "0000"; +BLUE <= (others => out_i) when oe_i = '1' else "0000"; +end Behavioral; + diff --git a/toplevel.vhd b/toplevel.vhd new file mode 100755 index 0000000..5ef01a0 --- /dev/null +++ b/toplevel.vhd @@ -0,0 +1,318 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 15:52:22 12/30/2008 +-- Design Name: +-- Module Name: toplevel - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +use work.T80_Pack.all; + +entity toplevel is + Port ( + -- Clock (50 MHz) + CLKIN_50M : in STD_LOGIC; + -- VGA out + RED, GREEN, BLUE : out STD_LOGIC_VECTOR(3 downto 0); + HSYNC, VSYNC : out STD_LOGIC; + -- PS2 Keyboard + PS2_CLK1, PS2_DATA1 : inout STD_LOGIC; + -- LEDs + LED : out STD_LOGIC_VECTOR(7 downto 0); + -- Buttons + BTN_NORTH : in STD_LOGIC; + BTN_SOUTH : in STD_LOGIC; + BTN_EAST : in STD_LOGIC; + BTN_WEST : in STD_LOGIC; + ROT_CENTER : in STD_LOGIC; + -- Switches - 3=Enable IORQ breakpoint, 2,1,0=N/A + SW : in STD_LOGIC_VECTOR(3 downto 0); + -- SPI for Atmel Dataflash + SPI_MISO : in std_logic; + SPI_MOSI : out std_logic; + SPI_SCK : out std_logic; + SPI_SS_B : out std_logic := '1'; + DATAFLASH_WP : out std_logic; + DATAFLASH_RST : out std_logic; + -- LCD interface + LCD_DB : inout std_logic_vector(7 downto 0); + LCD_E, LCD_RS, LCD_RW : out std_logic + ); +end toplevel; + +architecture Behavioral of toplevel is + component dcm_in50 + port ( + CLKIN_IN : in std_logic; + RST_IN : in std_logic; + CLKFX_OUT : out std_logic; + CLKIN_IBUFG_OUT : out std_logic; + CLK0_OUT : out std_logic; + LOCKED_OUT : out std_logic); + end component; + +component memory + port ( + DATA_I : in STD_LOGIC_VECTOR (7 downto 0); + DATA_O : out STD_LOGIC_VECTOR (7 downto 0); + ADDR_I : in STD_LOGIC_VECTOR (15 downto 0); + RD_N : in STD_LOGIC; + WR_N : in STD_LOGIC; + MREQ_N : in STD_LOGIC; + CLK : in STD_LOGIC; + CLKEN : in STD_LOGIC; + VID_DATA_O : out STD_LOGIC_VECTOR(7 downto 0); + VID_ADDR_I : in STD_LOGIC_VECTOR(9 downto 0); + VID_CLK : in STD_LOGIC); + end component; + +component T80se + generic ( + Mode : integer := 0; + T2Write : integer := 0; + IOWait : integer := 0); + port ( + RESET_n : in std_logic; + CLK_n : in std_logic; + CLKEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0)); +end component; + +component video + port ( + CLK : in std_logic; + DATA_I : in std_logic_vector(7 downto 0); + ADDR_O : out std_logic_vector(9 downto 0); + RED, GREEN, BLUE : out std_logic_vector(3 downto 0); + VSYNC, HSYNC : out std_logic); +end component; + +component keyboard + port ( + PS2_CLK : inout std_logic; + PS2_DATA : inout std_logic; + CLK_16M : in std_logic; + IORQ_n : in std_logic; + RD_n, WR_n : in std_logic; + DATA_I : in std_logic_vector(7 downto 0); + DATA_O : out std_logic_vector(7 downto 0); + DEBUG : out std_logic_vector(7 downto 0)); +end component; + +component uart + port ( + CLK_16M : in std_logic; + DATA_I : in std_logic_vector(7 downto 0); + ADDR_I : in std_logic_vector(1 downto 0); + IORQ_n, RD_n, WR_n : in std_logic; + DATA_O : out std_logic_vector(7 downto 0); + -- SPI for Atmel Dataflash + SPI_MISO : in std_logic; + SPI_MOSI : out std_logic; + SPI_SCK : out std_logic; + SPI_SS_B : out std_logic := '1'; + DATAFLASH_WP : out std_logic; + DATAFLASH_RST : out std_logic; + -- LCD interface + LCD_DB : inout std_logic_vector(7 downto 0); + LCD_E, LCD_RS, LCD_RW : out std_logic; + -- Buttons + BTN_NORTH : in STD_LOGIC; + BTN_SOUTH : in STD_LOGIC; + BTN_EAST : in STD_LOGIC; + BTN_WEST : in STD_LOGIC; + ROT_CENTER : in STD_LOGIC); +end component; + +signal CLK_16M, CLK_25M : std_logic; + +signal z80cpu_addr: std_logic_vector(15 downto 0); +signal z80cpu_datao, z80cpu_datai, memory_datao: std_logic_vector(7 downto 0); +signal z80cpu_mreq_n, z80cpu_iorq_n, z80cpu_wr_n, z80cpu_rd_n, + z80cpu_clken, z80cpu_halt_n, z80cpu_busak_n, z80cpu_m1_n, + z80cpu_rfsh_n, z80cpu_reset_n: std_logic; + +signal video_datai : std_logic_vector(7 downto 0); +signal video_addro : std_logic_vector(9 downto 0); + +signal red_out, blue_out, green_out : std_logic_vector(3 downto 0); +signal hsync_out, vsync_out : std_logic; + +signal keyb_datao : std_logic_vector(7 downto 0); +signal keyb_iorq_n : std_logic; + +signal uart_datao : std_logic_vector(7 downto 0); +signal uart_iorq_n : std_logic; + +-- shift register for z80 CLKEN +-- signal z80cpu_clken_gen : std_logic_vector(1 downto 0) := "01"; -- = 8 MHz +-- signal z80cpu_clken_gen : std_logic_vector(3 downto 0) := "0001"; -- = 4 MHz + signal z80cpu_clken_gen : std_logic_vector(7 downto 0) := "00000001"; -- = 2 MHz +-- signal z80cpu_clken_gen : std_logic_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000001"; -- = 62.5 KHz +signal stop : std_logic := '0'; +begin +dcm_in50_inst: dcm_in50 + port map ( + CLKIN_IN => CLKIN_50M, + RST_IN => '0', + CLKFX_OUT => CLK_16M, + CLKIN_IBUFG_OUT => open, + CLK0_OUT => CLK_25M, + LOCKED_OUT => open); + +clken: process(CLK_16M) + begin + if rising_edge(CLK_16M) then + z80cpu_clken_gen <= z80cpu_clken_gen((z80cpu_clken_gen'left-1) downto 0) + & z80cpu_clken_gen(z80cpu_clken_gen'left); + if BTN_NORTH = '1' then + stop <= '0'; + elsif (z80cpu_iorq_n = '0') and (SW(3) = '1') then + stop <= '1'; + end if; + end if; + end process; + +z80cpu_clken <= '1' when (stop = '0') and (z80cpu_clken_gen(z80cpu_clken_gen'left) = '1') else + '0'; + +z80cpu_reset_n <= '0' when (BTN_SOUTH = '1') else + '1'; + +z80cpu_datai <= memory_datao when z80cpu_mreq_n = '0' else + keyb_datao when (z80cpu_iorq_n = '0') and (z80cpu_addr(2 downto 0) = "000") else + uart_datao when (z80cpu_iorq_n = '0') and (z80cpu_addr(2 downto 0) = "001") else + uart_datao when (z80cpu_iorq_n = '0') and (z80cpu_addr(2 downto 0) = "010") else + "XXXXXXXX"; + +z80cpu_inst : T80se port map ( + RESET_n => z80cpu_reset_n, + CLK_n => CLK_16M, + CLKEN => z80cpu_clken, + WAIT_n => '1', + INT_n => '1', + NMI_n => '1', + BUSRQ_n => '1', + M1_n => z80cpu_m1_n, + MREQ_n => z80cpu_mreq_n, + IORQ_n => z80cpu_iorq_n, + RD_n => z80cpu_rd_n, + WR_n => z80cpu_wr_n, + RFSH_n => z80cpu_rfsh_n, + HALT_n => z80cpu_halt_n, + BUSAK_n => z80cpu_busak_n, + A => z80cpu_addr, + DI => z80cpu_datai, + DO => z80cpu_datao); + + +--LED <= z80cpu_iorq_n & z80cpu_rd_n & z80cpu_wr_n & z80cpu_addr(1) & "0000"; + +memory_inst: memory port map( DATA_I => z80cpu_datao, + DATA_O => memory_datao, + ADDR_I => z80cpu_addr, + RD_N => z80cpu_rd_n, + WR_N => z80cpu_wr_n, + MREQ_N => z80cpu_mreq_n, + CLK => CLK_16M, + CLKEN => z80cpu_clken, + VID_DATA_O => video_datai, + VID_ADDR_I => video_addro, + VID_CLK => CLK_25M); + + +keyb_iorq_n <= '0' when (z80cpu_iorq_n = '0') and (z80cpu_addr(2 downto 0) = "000") else + '1'; + +keyboard_inst : keyboard port map ( + PS2_CLK => PS2_CLK1, + PS2_DATA => PS2_DATA1, + CLK_16M => CLK_16M, + IORQ_n => keyb_iorq_n, + RD_n => z80cpu_rd_n, + WR_n => z80cpu_wr_n, + DATA_I => z80cpu_datao, + DATA_O => keyb_datao, + DEBUG => LED); + +uart_iorq_n <= '0' when (z80cpu_iorq_n = '0') and ((z80cpu_addr(2 downto 0) = "001") or + (z80cpu_addr(2 downto 0) = "010")) else + '1'; + +uart_inst : uart port map ( + CLK_16M => CLK_16M, + DATA_I => z80cpu_datao, + ADDR_I => z80cpu_addr(1 downto 0), + RD_n => z80cpu_rd_n, + WR_n => z80cpu_wr_n, + IORQ_n => uart_iorq_n, + DATA_O => uart_datao, + SPI_MISO => SPI_MISO, + SPI_MOSI => SPI_MOSI, + SPI_SCK => SPI_SCK, + SPI_SS_B => SPI_SS_B, + DATAFLASH_WP => DATAFLASH_WP, + DATAFLASH_RST => DATAFLASH_RST, + LCD_DB => LCD_DB, + LCD_E => LCD_E, + LCD_RS => LCD_RS, + LCD_RW => LCD_RW, + BTN_NORTH => BTN_NORTH, + BTN_EAST => BTN_EAST, + BTN_SOUTH => BTN_SOUTH, + BTN_WEST => BTN_WEST, + ROT_CENTER => ROT_CENTER + ); + +video_inst : video port map ( + CLK => CLK_25M, + DATA_I => video_datai, + ADDR_O => video_addro, + RED => red_out, + GREEN => green_out, + BLUE => blue_out, + VSYNC => vsync_out, + HSYNC => hsync_out); + +RED <= red_out; +GREEN <= green_out; +BLUE <= blue_out; +HSYNC <= hsync_out; +VSYNC <= vsync_out; +end Behavioral; + diff --git a/toplevel_tb.vhd b/toplevel_tb.vhd new file mode 100755 index 0000000..bd3b6fe --- /dev/null +++ b/toplevel_tb.vhd @@ -0,0 +1,155 @@ +------------------------------------------------------------------------------- +-- Title : Testbench for design "toplevel" +-- Project : +------------------------------------------------------------------------------- +-- File : toplevel_tb.vhd +-- Author : U-MATTHIAS-THINKP\Matthias +-- Company : +-- Created : 2009-01-03 +-- Last update: 2009-01-03 +-- Platform : +-- Standard : VHDL'87 +------------------------------------------------------------------------------- +-- Description: +------------------------------------------------------------------------------- +-- Copyright (c) 2009 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2009-01-03 1.0 Matthias Created +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +use work.sim_bmppack.all; + +------------------------------------------------------------------------------- + +entity toplevel_tb is + +end toplevel_tb; + +------------------------------------------------------------------------------- + +architecture tb of toplevel_tb is + + component toplevel + port ( + -- Clock (50 MHz) + CLKIN_50M : in STD_LOGIC; + -- NASBUS + ADDR : out STD_LOGIC_VECTOR (15 downto 0); + DATA : inout STD_LOGIC_VECTOR (7 downto 0); + M1_n : out STD_LOGIC; + MREQ_n : out STD_LOGIC; + IORQ_n : out STD_LOGIC; + WR_n : out STD_LOGIC; + RD_n : out STD_LOGIC; + RFSH_n : out STD_LOGIC; + HALT_n : out STD_LOGIC; + BUSAK_n : out STD_LOGIC; + RESET_n : in STD_LOGIC; + WAIT_n : in STD_LOGIC; + INT_n : in STD_LOGIC; + NMI_n : in STD_LOGIC; + BUSRQ_n : in STD_LOGIC; + -- VGA out + RED, GREEN, BLUE : out STD_LOGIC_VECTOR(3 downto 0); + HSYNC, VSYNC : out STD_LOGIC + ); + end component; + + -- component ports + signal CLKIN_50M : STD_LOGIC := '0'; + signal ADDR : STD_LOGIC_VECTOR (15 downto 0); + signal DATA : STD_LOGIC_VECTOR (7 downto 0); + signal M1_n : STD_LOGIC; + signal MREQ_n : STD_LOGIC; + signal IORQ_n : STD_LOGIC; + signal WR_n : STD_LOGIC; + signal RD_n : STD_LOGIC; + signal RFSH_n : STD_LOGIC; + signal HALT_n : STD_LOGIC; + signal BUSAK_n : STD_LOGIC; + signal RESET_n : STD_LOGIC := '0'; + signal WAIT_n : STD_LOGIC := '1'; + signal INT_n : STD_LOGIC := '1'; + signal NMI_n : STD_LOGIC := '1'; + signal BUSRQ_n : STD_LOGIC := '1'; + signal RED, GREEN, BLUE : std_logic_vector(3 downto 0); + signal VSYNC, HSYNC : std_logic; + +begin -- tb + + -- component instantiation + DUT: toplevel + port map ( + CLKIN_50M => CLKIN_50M, + ADDR => ADDR, + DATA => DATA, + M1_n => M1_n, + MREQ_n => MREQ_n, + IORQ_n => IORQ_n, + WR_n => WR_n, + RD_n => RD_n, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + BUSAK_n => BUSAK_n, + RESET_n => RESET_n, + WAIT_n => WAIT_n, + INT_n => INT_n, + NMI_n => NMI_n, + BUSRQ_n => BUSRQ_n, + RED => RED, + GREEN => GREEN, + BLUE => BLUE, + VSYNC => VSYNC, + HSYNC => HSYNC + ); + + -- clock generation + CLKIN_50M <= not CLKIN_50M after 10 ns; + + -- waveform generation + WaveGen_Proc: process + begin + -- insert signal assignments here + wait for 100 ns; + RESET_n <= '1'; + wait; + end process WaveGen_Proc; + + VGARead: process + variable i: integer := 0; + variable pixeldata : std_logic_vector(23 downto 0); + begin + ReadFile("vga.bmp"); + wait until CLKIN_50M = '1'; -- wait for uut to stat + wait for 260 ns; -- wait for vga frame to start (depends + -- on latency of UUT) + while true loop + for y in 479 downto 0 loop + for x in 0 to 639 loop + pixeldata := RED & "0000" & GREEN & "0000" & BLUE & "0000"; + SetPixel(x, y, pixeldata); + wait for 40 ns; + end loop; -- x + wait for 6400 ns; + end loop; -- x + wait for 1440 us; + WriteFile("vga" & integer'image(i) & ".bmp"); + i := i + 1; + end loop; + end process; + +end tb; + +------------------------------------------------------------------------------- + +configuration toplevel_tb_tb_cfg of toplevel_tb is + for tb + end for; +end toplevel_tb_tb_cfg; + +------------------------------------------------------------------------------- diff --git a/uart.vhd b/uart.vhd new file mode 100755 index 0000000..10eda40 --- /dev/null +++ b/uart.vhd @@ -0,0 +1,259 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 15:52:22 12/30/2008 +-- Design Name: +-- Module Name: toplevel - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +library UNISIM; +use UNISIM.VComponents.all; + +entity uart is + + port ( + CLK_16M : in std_logic; + DATA_I : in std_logic_vector(7 downto 0); + ADDR_I : in std_logic_vector(1 downto 0); + IORQ_n, RD_n, WR_n : in std_logic; + DATA_O : out std_logic_vector(7 downto 0); + -- SPI for Atmel Dataflash + SPI_MISO : in std_logic; + SPI_MOSI : out std_logic; + SPI_SCK : out std_logic; + SPI_SS_B : out std_logic := '1'; + DATAFLASH_WP : out std_logic; + DATAFLASH_RST : out std_logic; + -- LCD interface + LCD_DB : inout std_logic_vector(7 downto 0); + LCD_E, LCD_RS, LCD_RW : out std_logic; + -- Buttons + BTN_NORTH : in STD_LOGIC; + BTN_SOUTH : in STD_LOGIC; + BTN_EAST : in STD_LOGIC; + BTN_WEST : in STD_LOGIC; + ROT_CENTER : in STD_LOGIC); + +end uart; + +architecture Behavioral of uart is + +component kcpsm3 + port ( + address : out std_logic_vector(9 downto 0); + instruction : in std_logic_vector(17 downto 0); + port_id : out std_logic_vector(7 downto 0); + write_strobe : out std_logic; + out_port : out std_logic_vector(7 downto 0); + read_strobe : out std_logic; + in_port : in std_logic_vector(7 downto 0); + interrupt : in std_logic; + interrupt_ack : out std_logic; + reset : in std_logic; + clk : in std_logic); + end component; + +component uartprog + port ( + address : in std_logic_vector(9 downto 0); + instruction : out std_logic_vector(17 downto 0); + clk : in std_logic); + end component; + +component fifo16x8 + port ( + DATAIN : in STD_LOGIC_VECTOR (7 downto 0); + WRITESTB : in STD_LOGIC; + DATAOUT : out STD_LOGIC_VECTOR (7 downto 0); + READSTB : in STD_LOGIC; + CLK : in STD_LOGIC; + FULL : out STD_LOGIC; + EMPTY : out STD_LOGIC); +end component; + +component spi + port ( + MISO : in std_logic; + MOSI, SCK : out std_logic; + DATA_I : in std_logic_vector(7 downto 0); + DATA_O : out std_logic_vector(7 downto 0); + START : in std_logic; + BUSY : out std_logic; + CLK : in std_logic); +end component; + +signal receive_r, transmit_r : std_logic_vector(7 downto 0); +signal drt_r, drr_r : std_logic := '0'; + +signal kcpsm3_addr : std_logic_vector(9 downto 0); +signal kcpsm3_instr : std_logic_vector(17 downto 0); +signal kcpsm3_portid, kcpsm3_outport, kcpsm3_inport : std_logic_vector(7 downto 0); +signal kcpsm3_wrstb, kcpsm3_rdstb : std_logic; + +attribute iob : string; +signal lcdctrl_r : std_logic_vector(2 downto 0) := "000"; +signal lcdout_r : std_logic_vector(7 downto 0) := X"00"; +attribute iob of lcdout_r : signal is "true"; +attribute iob of lcdctrl_r : signal is "true"; + +signal spi_datao : std_logic_vector(7 downto 0); +signal spi_start, spi_busy : std_logic; + +signal iorq_old : std_logic := '0'; + +signal fifo_t_wrstb, fifo_t_rdstb, fifo_t_full, fifo_t_empty, fifo_r_wrstb, fifo_r_rdstb, fifo_r_full, fifo_r_empty : std_logic; +signal fifo_r_din, fifo_r_dout, fifo_t_din, fifo_t_dout : std_logic_vector(7 downto 0); +begin -- Behavioral + + kcpsm3_inst : kcpsm3 port map ( + address => kcpsm3_addr, + instruction => kcpsm3_instr, + port_id => kcpsm3_portid, + write_strobe => kcpsm3_wrstb, + out_port => kcpsm3_outport, + read_strobe => kcpsm3_rdstb, + in_port => kcpsm3_inport, + interrupt => '0', + interrupt_ack => open, + reset => '0', + clk => CLK_16M); + + prog_inst : uartprog port map ( + address => kcpsm3_addr, + instruction => kcpsm3_instr, + clk => CLK_16M); + + spi_inst : spi port map ( + MISO => SPI_MISO, + MOSI => SPI_MOSI, + SCK => SPI_SCK, + DATA_I => kcpsm3_outport, + DATA_O => spi_datao, + START => spi_start, + BUSY => spi_busy, + CLK => CLK_16M); + + spi_start <= '1' when (kcpsm3_wrstb = '1') and (kcpsm3_portid = X"02") else + '0'; + + spi_iface: process (CLK_16M) + begin -- process spi_iface + if rising_edge(CLK_16M) then + if (kcpsm3_wrstb = '1') then + if (kcpsm3_portid = X"03") then + SPI_SS_B <= kcpsm3_outport(0); + end if; + end if; + end if; + end process; + + lcd_iface: process (CLK_16M) + begin -- process lcd_iface + if rising_edge(CLK_16M) then + if (kcpsm3_wrstb = '1') then + if (kcpsm3_portid = X"04") then + lcdctrl_r <= kcpsm3_outport(2 downto 0); + elsif kcpsm3_portid = X"05" then + lcdout_r <= kcpsm3_outport; + end if; + end if; + end if; + end process lcd_iface; + +kcpsm3_inport <= fifo_t_dout when kcpsm3_portid = X"00" else + "000000" & fifo_t_empty & fifo_r_full when kcpsm3_portid = X"01" else + spi_datao when kcpsm3_portid = X"02" else + "0000000" & spi_busy when kcpsm3_portid = X"03" else + LCD_DB when kcpsm3_portid = X"05" else + "00000" & lcdctrl_r when kcpsm3_portid = X"04" else + "000" & ROT_CENTER & BTN_NORTH & BTN_EAST & BTN_SOUTH & BTN_WEST when kcpsm3_portid = X"06" else + "XXXXXXXX"; + + process (CLK_16M) + begin + if rising_edge(CLK_16M) then + fifo_r_wrstb <= '0'; + fifo_t_rdstb <= '0'; + if (kcpsm3_wrstb = '1') then + if (kcpsm3_portid = X"00") then + fifo_r_din <= kcpsm3_outport; + fifo_r_wrstb <= '1'; + end if; + elsif (kcpsm3_rdstb = '1') then + if (kcpsm3_portid = X"00") then + fifo_t_rdstb <= '1'; + end if; + end if; + end if; + end process; + + fifo16x8_inst_transmit : fifo16x8 port map ( + DATAIN => fifo_t_din, + WRITESTB => fifo_t_wrstb, + DATAOUT => fifo_t_dout, + READSTB => fifo_t_rdstb, + CLK => CLK_16M, + FULL => fifo_t_full, + EMPTY => fifo_t_empty); + + fifo16x8_inst_receive : fifo16x8 port map ( + DATAIN => fifo_r_din, + WRITESTB => fifo_r_wrstb, + DATAOUT => fifo_r_dout, + READSTB => fifo_r_rdstb, + CLK => CLK_16M, + FULL => fifo_r_full, + EMPTY => fifo_r_empty); + + z80bus: process (CLK_16M) + begin + if rising_edge(CLK_16M) then + fifo_r_rdstb <= '0'; + fifo_t_wrstb <= '0'; + if (iorq_old = '1') and (IORQ_n = '0') then + if ADDR_I = "01" then + if RD_n = '0' then -- read receiver register + DATA_O <= fifo_r_dout; + fifo_r_rdstb <= '1'; + elsif WR_n = '0' then -- transmitter buffer load + fifo_t_din <= DATA_I; + fifo_t_wrstb <= '1'; + end if; + elsif ADDR_I = "10" then + if RD_n = '0' then -- read status flags + DATA_O <= not fifo_r_empty & not fifo_t_full & "XX000X"; -- DR, TBRE, x, x, FE, PE, OE, x + end if; + end if; + end if; + iorq_old <= IORQ_n; + end if; + end process; + + LCD_DB <= lcdout_r when lcdctrl_r(2) = '0' else + "ZZZZZZZZ"; + LCD_E <= lcdctrl_r(0); + LCD_RS <= lcdctrl_r(1); + LCD_RW <= lcdctrl_r(2); + + DATAFLASH_RST <= '1'; + DATAFLASH_WP <= '1'; + +end Behavioral; diff --git a/uart_prog.psm b/uart_prog.psm new file mode 100755 index 0000000..94194eb --- /dev/null +++ b/uart_prog.psm @@ -0,0 +1,2 @@ +done: +JUMP done \ No newline at end of file diff --git a/uartprog.psm b/uartprog.psm new file mode 100755 index 0000000..4d29e84 --- /dev/null +++ b/uartprog.psm @@ -0,0 +1,445 @@ +CONSTANT UART_DATA, 00 +CONSTANT UART_CTRL, 01 +CONSTANT LCD_DATA, 05 +CONSTANT LCD_CTRL, 04 +CONSTANT SPI_DATA, 02 +CONSTANT SPI_CTRL, 03 +CONSTANT KEYS, 06 + +CONSTANT KEY_CENTER, 10 +CONSTANT KEY_NORTH, 08 +CONSTANT KEY_EAST, 04 +CONSTANT KEY_SOUTH, 02 +CONSTANT KEY_WEST, 01 + +NAMEREG sF, PAGE_LSB +NAMEREG sE, PAGE_MSB +NAMEREG sD, MODE + +; wait 10 ms (6*256*256) +LOAD s0, 06 +loop0: +LOAD s1, FF +loop1: +LOAD s2, FF +loop2: +SUB s2, 01 +JUMP NZ, loop2 +SUB s1, 01 +JUMP NZ, loop1 +SUB s0, 01 +JUMP NZ, loop0 + +LOAD s0, 38 +CALL write_display_i +CALL wait_busy +LOAD s0, 0E +CALL write_display_i +CALL wait_busy +LOAD s0, 01 +CALL write_display_i +CALL wait_busy +LOAD s0, 06 +CALL write_display_i +CALL wait_busy +LOAD s0, 80 +CALL write_display_i +CALL wait_busy + +; clear page register +LOAD PAGE_LSB, 00 +LOAD PAGE_MSB, 00 +LOAD s0, PAGE_MSB +CALL write_hex +LOAD s0, PAGE_LSB +CALL write_hex +; clear mode register +LOAD MODE, 00 +CALL wait_busy +LOAD s0, 85 +CALL write_display_i +LOAD s0, MODE +CALL write_hex +main_loop: +INPUT s0, KEYS +AND s0, 1D +JUMP NZ, main_loop +main_loop_1: +INPUT s0, KEYS +TEST s0, KEY_EAST +JUMP NZ, east +TEST s0, KEY_WEST +JUMP NZ, west +TEST s0, KEY_NORTH +JUMP NZ, north +TEST s0, KEY_CENTER +JUMP NZ, center +JUMP main_loop_1 + +;; increment page +east: +ADD PAGE_LSB, 01 +ADDCY PAGE_MSB, 00 +COMPARE PAGE_MSB, 10 +JUMP NZ, east_write +LOAD PAGE_LSB, 00 +LOAD PAGE_MSB, 00 +east_write: +CALL wait_busy +LOAD s0, 80 +CALL write_display_i +LOAD s0, PAGE_MSB +CALL write_hex +LOAD s0, PAGE_LSB +CALL write_hex +JUMP main_loop + +;; decrement page +west: +SUB PAGE_LSB, 01 +SUBCY PAGE_MSB, 00 +COMPARE PAGE_MSB, FF +JUMP NZ, west_write +LOAD PAGE_LSB, FF +LOAD PAGE_MSB, 0F +west_write: +CALL wait_busy +LOAD s0, 80 +CALL write_display_i +LOAD s0, PAGE_MSB +CALL write_hex +LOAD s0, PAGE_LSB +CALL write_hex +JUMP main_loop + +;; toggle mode +north: +XOR MODE, 01 +CALL wait_busy +LOAD s0, 85 +CALL write_display_i +LOAD s0, MODE +CALL write_hex +JUMP main_loop + +;; enter recv/send state +center: +TEST MODE, 01 +JUMP Z, send +CALL recv_page +JUMP main_loop +send: +CALL send_page +JUMP main_loop + +; receive and write page, s0..s5 overwritten +recv_page: +CALL clear_buffer +LOAD s2, PAGE_MSB +LOAD s3, PAGE_LSB +SL0 s3 ; shift top 2 bits to s2 +SLA s2 +SL0 s3 +SLA s2 +CALL spi_busy +; recv and write data +LOAD s0, 00 +OUTPUT s0, SPI_CTRL ; Chip select low +LOAD s0, 82 ; Buffer Write +CALL do_spi ; write command +LOAD s0, s2 +CALL do_spi ; write addr +LOAD s0, s3 +CALL do_spi ; write addr +LOAD s0, 00 +CALL do_spi ; write addr +LOAD s4, 00 +LOAD s5, 00 +recv_page_loop: +ADD s5, 01 +ADDCY s4, 00 +COMPARE s4, 02 +JUMP NZ, recv_page_recv +COMPARE s5, 11 +JUMP Z, recv_page_exit +recv_page_recv: +INPUT s0, KEYS +AND s0, KEY_CENTER +JUMP Z, recv_page_end +INPUT s0, UART_CTRL +AND s0, 02 +JUMP NZ, recv_page_recv +INPUT s0, UART_DATA +CALL do_spi ; write data +JUMP recv_page_loop +recv_page_end: ; check if 528 bytes were written +COMPARE s4, 02 +JUMP NZ, recv_page_wff +COMPARE s5, 10 +JUMP Z, recv_page_exit +recv_page_wff: ; write terminating FF if bytes < 528 +LOAD s0, FF +CALL do_spi +recv_page_exit: +LOAD s0, 01 +OUTPUT s0, SPI_CTRL ; Chip select high +RETURN + + +; send page; s0..s5 overwritten +send_page: +LOAD s2, PAGE_MSB +LOAD s3, PAGE_LSB +SL0 s3 ; shift top 2 bits to s2 +SLA s2 +SL0 s3 +SLA s2 +CALL spi_busy +LOAD s0, 00 +OUTPUT s0, SPI_CTRL ; Chip select low +LOAD s0, D2 ; Main Memory Page Read +CALL do_spi ; write command +LOAD s0, s2 +CALL do_spi ; write addr +LOAD s0, s3 +CALL do_spi ; write addr +LOAD s0, 00 +CALL do_spi ; write addr +CALL do_spi ; write don't care +CALL do_spi ; write don't care +CALL do_spi ; write don't care +CALL do_spi ; write don't care +LOAD s4, 00 +LOAD s5, 00 +send_page_loop: +ADD s5, 01 +ADDCY s4, 00 +COMPARE s4, 02 +JUMP NZ, send_page_send +COMPARE s5, 11 +JUMP Z, send_page_end +send_page_send: +CALL do_spi ; read data +COMPARE s0, FF +JUMP Z, send_page_end +CALL write_data +; dump incoming data +send_page_dump: +INPUT s0, UART_CTRL +AND s0, 02 +JUMP NZ, send_page_loop +INPUT s0, UART_DATA +JUMP send_page_dump +send_page_end: +LOAD s0, 01 +OUTPUT s0, SPI_CTRL ; Chip select high +RETURN + +; data in s0; return in s0; +do_spi: +OUTPUT s0, SPI_DATA +do_spi_wait: +INPUT s0, SPI_CTRL +AND s0, 01 +JUMP NZ, do_spi_wait +INPUT s0, SPI_DATA +RETURN + +; wait for flash to become unbusy +spi_busy: +LOAD s0, 00 +OUTPUT s0, SPI_CTRL ; Chip select low +LOAD s0, D7 +CALL do_spi +spi_busy_loop: +CALL do_spi +TEST s0, 80 +JUMP Z, spi_busy_loop +LOAD s0, 01 +OUTPUT s0, SPI_CTRL ; Chip select high +RETURN + +; clear buffer 1 +clear_buffer: +CALL spi_busy +LOAD s0, 00 +OUTPUT s0, SPI_CTRL ; Chip select low +LOAD s0, 84 ; Buffer Write +CALL do_spi ; write command +LOAD s0, 00 +CALL do_spi ; write addr +LOAD s0, 00 +CALL do_spi ; write addr +LOAD s0, 00 +CALL do_spi ; write addr +LOAD s4, 00 +LOAD s5, 00 +clear_buffer_loop: +ADD s5, 01 +ADDCY s4, 00 +COMPARE s4, 02 +JUMP NZ, clear_buffer_write +COMPARE s5, 11 +JUMP Z, clear_buffer_end +clear_buffer_write: +LOAD s0, FF +CALL do_spi ; read data +JUMP clear_buffer_loop +clear_buffer_end: +LOAD s0, 01 +OUTPUT s0, SPI_CTRL ; Chip select high +RETURN + +; data in s0; s1 overwritten +write_data: +INPUT s1, UART_CTRL +AND s1, 01 +JUMP NZ, write_data +OUTPUT s0, UART_DATA +RETURN + +; return in s0 +read_data: +INPUT s0, UART_CTRL +AND s0, 02 +JUMP NZ, read_data +INPUT s0, UART_DATA +RETURN + +; data in s0; s0, s1, s2, s3 overwritten +write_hex: +LOAD s3, s0 +LOAD s2, s0 +SR0 s2 +SR0 s2 +SR0 s2 +SR0 s2 +ADD s2, 30 +COMPARE s2, 3A +JUMP C, write_hex_outh +ADD s2, 07 +write_hex_outh: +CALL wait_busy +LOAD s0, s2 +CALL write_display_d +LOAD s2, s3 +AND s2, 0F +ADD s2, 30 +COMPARE s2, 3A +JUMP C, write_hex_outl +ADD s2, 07 +write_hex_outl: +CALL wait_busy +LOAD s0, s2 +CALL write_display_d +RETURN + + +; data in s0, s0 overwritten +write_display_i: +OUTPUT s0, LCD_DATA +LOAD s0, 00 +LOAD s0, 00 +OUTPUT s0, LCD_CTRL +LOAD s0, 00 +LOAD s0, 00 +LOAD s0, 01 +OUTPUT s0, LCD_CTRL +LOAD s0, 00 +LOAD s0, 00 +LOAD s0, 00 +LOAD s0, 00 +LOAD s0, 00 +LOAD s0, 00 +LOAD s0, 00 +LOAD s0, 00 +LOAD s0, 00 +LOAD s0, 00 +LOAD s0, 00 +LOAD s0, 00 +OUTPUT s0, LCD_CTRL +LOAD s0, 00 +LOAD s0, 00 +LOAD s0, 00 +LOAD s0, 00 +LOAD s0, 00 +LOAD s0, 00 +LOAD s0, 00 +LOAD s0, 00 +LOAD s0, 00 +LOAD s0, 00 +RETURN + +; zero flag reset if busy; s0, s1 overwritten +busy_display: +LOAD s0, 04 +OUTPUT s0, LCD_CTRL +LOAD s0, 00 +LOAD s0, 05 +OUTPUT s0, LCD_CTRL +LOAD s0, 00 +LOAD s0, 00 +LOAD s0, 00 +LOAD s0, 00 +LOAD s0, 00 +LOAD s0, 00 +LOAD s0, 00 +LOAD s0, 00 +LOAD s0, 00 +LOAD s0, 00 +INPUT s1, LCD_DATA +LOAD s0, 00 +OUTPUT s0, LCD_CTRL +LOAD s0, 00 +LOAD s0, 00 +LOAD s0, 00 +LOAD s0, 00 +LOAD s0, 00 +LOAD s0, 00 +LOAD s0, 00 +LOAD s0, 00 +LOAD s0, 00 +LOAD s0, 00 +LOAD s0, 00 +AND s1, 80 +RETURN + +wait_busy: +CALL busy_display +JUMP NZ, wait_busy +RETURN + +; data in s0, s0 is overwritten +write_display_d: +OUTPUT s0, LCD_DATA +LOAD s0, 00 +LOAD s0, 02 +OUTPUT s0, LCD_CTRL +LOAD s0, 00 +LOAD s0, 00 +LOAD s0, 03 +OUTPUT s0, LCD_CTRL +LOAD s0, 00 +LOAD s0, 00 +LOAD s0, 00 +LOAD s0, 00 +LOAD s0, 00 +LOAD s0, 00 +LOAD s0, 00 +LOAD s0, 00 +LOAD s0, 00 +LOAD s0, 00 +LOAD s0, 00 +LOAD s0, 02 +OUTPUT s0, LCD_CTRL +LOAD s0, 00 +LOAD s0, 00 +LOAD s0, 00 +LOAD s0, 00 +LOAD s0, 00 +LOAD s0, 00 +LOAD s0, 00 +LOAD s0, 00 +LOAD s0, 00 +LOAD s0, 00 +RETURN diff --git a/video.vhd b/video.vhd new file mode 100755 index 0000000..2f10dbf --- /dev/null +++ b/video.vhd @@ -0,0 +1,121 @@ +------------------------------------------------------------------------------- +-- Title : NASCOM 2 video generator for VGA monitors +-- Project : +------------------------------------------------------------------------------- +-- File : video.vhd +-- Author : U-MATTHIAS-THINKP\Matthias +-- Company : +-- Created : 2009-01-03 +-- Last update: 2009-01-03 +-- Platform : +-- Standard : VHDL'93 +------------------------------------------------------------------------------- +-- Description: +------------------------------------------------------------------------------- +-- Copyright (c) 2009 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2009-01-03 1.0 Matthias Created +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity video is + + port ( + CLK : in std_logic; -- Should be 25.175 MHz + DATA_I : in std_logic_vector(7 downto 0); -- Data from video ram + ADDR_O : out std_logic_vector(9 downto 0); -- Addr to video ram + RED, GREEN, BLUE : out std_logic_vector(3 downto 0); -- VGA output to DAC + VSYNC, HSYNC : out std_logic); -- VGA sync output + +end video; + +architecture Behavioral of video is + component syncgen + port ( + CLKPIXEL : in STD_LOGIC; + VSYNC : out STD_LOGIC; + HSYNC : out STD_LOGIC; + COLUMN : out STD_LOGIC_VECTOR (9 downto 0); + ROW : out STD_LOGIC_VECTOR (9 downto 0)); + end component; + + component videogen + port ( + ROW : in STD_LOGIC_VECTOR (9 downto 0); + COLUMN : in STD_LOGIC_VECTOR (9 downto 0); + CLK : in STD_LOGIC; + RED, GREEN, BLUE : out STD_LOGIC_VECTOR(3 downto 0); + VRAM_ADDR_O : out STD_LOGIC_VECTOR(9 downto 0); + VRAM_DATA_I : in STD_LOGIC_VECTOR(7 downto 0)); + end component; +attribute iob : string; -- pull flip-flop into IOB +signal vsync_int, hsync_int : std_logic := '1'; -- vga sync from syncgen +signal column, row : std_logic_vector(9 downto 0); -- screen position from syncgen +signal red_out, green_out, blue_out : std_logic_vector(3 downto 0); +signal vram_addr_out : std_logic_vector(9 downto 0); +signal vsync_d1, vsync_d2, vsync_d3, vsync_d4, hsync_d1, hsync_d2, hsync_d3, hsync_d4 : std_logic := '1'; -- delay sync signals by videogen latency + +attribute iob of VSYNC, HSYNC : signal is "TRUE"; +attribute iob of RED, GREEN, BLUE : signal is "TRUE"; +begin -- Behavioral + +syncgen_inst : syncgen port map ( + CLKPIXEL => CLK, + VSYNC => vsync_int, + HSYNC => hsync_int, + COLUMN => column, + ROW => row); + +videogen_inst : videogen port map ( + ROW => row, + COLUMN => column, + CLK => CLK, + RED => red_out, + GREEN => green_out, + BLUE => blue_out, + VRAM_ADDR_O => vram_addr_out, + VRAM_DATA_I => DATA_I); + +ADDR_O <= vram_addr_out; + +-- purpose: output register for video data +-- type : sequential +-- inputs : CLK, red_out, blue_out, green_out +-- outputs: RED, BLUE, GREEN +viddataff: process (CLK) +begin -- process viddataff + if rising_edge(CLK) then -- rising clock edge + RED <= red_out; + GREEN <= green_out; + BLUE <= blue_out; + end if; +end process viddataff; + +-- purpose: delay sync signals by 3+1 cycles +-- type : sequential +-- inputs : CLK, vsync_int, hsync_int +-- outputs: VSYNC, HSYNC +syncdelay: process (CLK) +begin -- process + if rising_edge(CLK) then + vsync_d1 <= vsync_int; + vsync_d2 <= vsync_d1; + vsync_d3 <= vsync_d2; + vsync_d4 <= vsync_d3; + VSYNC <= vsync_d4; + + hsync_d1 <= hsync_int; + hsync_d2 <= hsync_d1; + hsync_d3 <= hsync_d2; + hsync_d4 <= hsync_d3; + HSYNC <= hsync_d4; + end if; +end process; + +end Behavioral; diff --git a/videogen.vhd b/videogen.vhd new file mode 100755 index 0000000..de7e1aa --- /dev/null +++ b/videogen.vhd @@ -0,0 +1,132 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 16:39:57 12/11/2008 +-- Design Name: +-- Module Name: adrgen - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity videogen is + Port ( ROW : in STD_LOGIC_VECTOR (9 downto 0); + COLUMN : in STD_LOGIC_VECTOR (9 downto 0); + CLK : in STD_LOGIC; + RED, GREEN, BLUE : out STD_LOGIC_VECTOR(3 downto 0); + VRAM_ADDR_O : out STD_LOGIC_VECTOR(9 downto 0); + VRAM_DATA_I : in STD_LOGIC_VECTOR(7 downto 0) + ); +end videogen; + +architecture Behavioral of videogen is +component charrom IS + port ( + clka: IN std_logic; + addra: IN std_logic_VECTOR(10 downto 0); + douta: OUT std_logic_VECTOR(7 downto 0)); +END component; + +signal chrx_i: std_logic_vector(2 downto 0) := "000"; -- h pos in char +signal chry_i: std_logic_vector(3 downto 0) := "0000"; -- v pos in char +signal scradrx_i: std_logic_vector(6 downto 0) := "0001010"; -- adr in ram line +signal scradry_i: std_logic_vector(11 downto 0) := X"3C0"; -- line ofs + -- in ram +signal oe_i, oe_d1, oe_d2, oe_d3, oe_o: std_logic := '0'; -- output enable + -- delay ff chain + +signal charrom_addr : std_logic_vector(10 downto 0); +signal charrom_data : std_logic_vector(7 downto 0); +signal out_i : std_logic; +begin + +adrgen: process (CLK) + begin + if rising_edge(CLK) then + chrx_i <= COLUMN(2 downto 0); + chry_i <= ROW(3 downto 0); + + if (COLUMN < 384) and (ROW < 256) then -- nascom 48x16 characters mode + oe_i <= '1'; + if (chrx_i = "111") and (COLUMN(2 downto 0) = "000") then + if scradrx_i = 57 then + scradrx_i <= "0001010"; + else + scradrx_i <= scradrx_i + 1; + end if; + end if; + else + oe_i <= '0'; + end if; + + if ROW < 256 then + if (not (chry_i = "0000")) and (ROW(3 downto 0) = "0000") then + if scradry_i = 960 then + scradry_i <= X"000"; + else + scradry_i <= scradry_i + 64; + end if; + end if; + end if; + + end if; + end process; + + VRAM_ADDR_O <= scradry_i(9 downto 0) + scradrx_i; + + charrom_addr(10 downto 4) <= VRAM_DATA_I(6 downto 0); + charrom_addr(3 downto 0) <= chry_i; + + charrom_inst: charrom port map( clka => CLK, + addra => charrom_addr, + douta => charrom_data); + + vgen: process (CLK) + variable bitmap: std_logic_vector(7 downto 0) := "00000000"; + begin + if rising_edge(CLK) then + if chrx_i = 3 then + bitmap := charrom_data; + end if; + out_i <= bitmap(conv_integer(2 - chrx_i)); + end if; + end process; + + oe_delay: process (CLK) + begin + if rising_edge(CLK) then + oe_d1 <= oe_i; + oe_d2 <= oe_d1; + oe_d3 <= oe_d2; + oe_o <= oe_d3; + end if; + end process; + +RED <= (others => out_i) when oe_o = '1' else "0000"; +GREEN <= (others => out_i) when oe_o = '1' else "0000"; +BLUE <= (others => out_i) when oe_o = '1' else "0000"; + +--CHRX <= chrx_i; +--CHRY <= chry_i; +--SCRADR <= scradrx_i + scradry_i; +--OE <= oe_i; +end Behavioral; + diff --git a/vsim.wlf b/vsim.wlf new file mode 100755 index 0000000..d779e3e Binary files /dev/null and b/vsim.wlf differ