library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


entity dcm_in50 is

  port (
    CLKIN_IN        : in  std_logic;
    RST_IN          : in  std_logic;
    CLKFX_OUT       : out std_logic;
    CLKIN_IBUFG_OUT : out std_logic;
    CLK0_OUT        : out std_logic;
    LOCKED_OUT      : out std_logic);

end dcm_in50;

architecture Behavioral of dcm_in50 is

begin  -- Behavioral

  LOCKED_OUT <= '1';
  CLKIN_IBUFG_OUT <= CLKIN_IN;
  
  process
  begin
    wait until CLKIN_IN = '1';
    while true loop
      CLK0_OUT <= '1';
      wait for 20 ns;
      CLK0_OUT <= '0';
      wait for 20 ns;
    end loop;
  end process;

  process
  begin
    wait until CLKIN_IN = '1';
    while true loop
      CLKFX_OUT <= '1';
      wait for 31.25 ns;
      CLKFX_OUT <= '0';
      wait for 31.25 ns;
    end loop;
  end process;

end Behavioral;