CONSTANT UART_DATA, 00 CONSTANT UART_CTRL, 01 CONSTANT LCD_DATA, 05 CONSTANT LCD_CTRL, 04 CONSTANT SPI_DATA, 02 CONSTANT SPI_CTRL, 03 CONSTANT KEYS, 06 CONSTANT KEY_CENTER, 10 CONSTANT KEY_NORTH, 08 CONSTANT KEY_EAST, 04 CONSTANT KEY_SOUTH, 02 CONSTANT KEY_WEST, 01 NAMEREG sF, PAGE_LSB NAMEREG sE, PAGE_MSB NAMEREG sD, MODE ; wait 10 ms (6*256*256) LOAD s0, 06 loop0: LOAD s1, FF loop1: LOAD s2, FF loop2: SUB s2, 01 JUMP NZ, loop2 SUB s1, 01 JUMP NZ, loop1 SUB s0, 01 JUMP NZ, loop0 LOAD s0, 38 CALL write_display_i CALL wait_busy LOAD s0, 0E CALL write_display_i CALL wait_busy LOAD s0, 01 CALL write_display_i CALL wait_busy LOAD s0, 06 CALL write_display_i CALL wait_busy LOAD s0, 80 CALL write_display_i CALL wait_busy ; clear page register LOAD PAGE_LSB, 00 LOAD PAGE_MSB, 00 LOAD s0, PAGE_MSB CALL write_hex LOAD s0, PAGE_LSB CALL write_hex ; clear mode register LOAD MODE, 00 CALL wait_busy LOAD s0, 85 CALL write_display_i LOAD s0, MODE CALL write_hex main_loop: INPUT s0, KEYS AND s0, 1D JUMP NZ, main_loop main_loop_1: INPUT s0, KEYS TEST s0, KEY_EAST JUMP NZ, east TEST s0, KEY_WEST JUMP NZ, west TEST s0, KEY_NORTH JUMP NZ, north TEST s0, KEY_CENTER JUMP NZ, center JUMP main_loop_1 ;; increment page east: ADD PAGE_LSB, 01 ADDCY PAGE_MSB, 00 COMPARE PAGE_MSB, 10 JUMP NZ, east_write LOAD PAGE_LSB, 00 LOAD PAGE_MSB, 00 east_write: CALL wait_busy LOAD s0, 80 CALL write_display_i LOAD s0, PAGE_MSB CALL write_hex LOAD s0, PAGE_LSB CALL write_hex JUMP main_loop ;; decrement page west: SUB PAGE_LSB, 01 SUBCY PAGE_MSB, 00 COMPARE PAGE_MSB, FF JUMP NZ, west_write LOAD PAGE_LSB, FF LOAD PAGE_MSB, 0F west_write: CALL wait_busy LOAD s0, 80 CALL write_display_i LOAD s0, PAGE_MSB CALL write_hex LOAD s0, PAGE_LSB CALL write_hex JUMP main_loop ;; toggle mode north: XOR MODE, 01 CALL wait_busy LOAD s0, 85 CALL write_display_i LOAD s0, MODE CALL write_hex JUMP main_loop ;; enter recv/send state center: TEST MODE, 01 JUMP Z, send CALL recv_page JUMP main_loop send: CALL send_page JUMP main_loop ; receive and write page, s0..s5 overwritten recv_page: CALL clear_buffer LOAD s2, PAGE_MSB LOAD s3, PAGE_LSB SL0 s3 ; shift top 2 bits to s2 SLA s2 SL0 s3 SLA s2 CALL spi_busy ; recv and write data LOAD s0, 00 OUTPUT s0, SPI_CTRL ; Chip select low LOAD s0, 82 ; Buffer Write CALL do_spi ; write command LOAD s0, s2 CALL do_spi ; write addr LOAD s0, s3 CALL do_spi ; write addr LOAD s0, 00 CALL do_spi ; write addr LOAD s4, 00 LOAD s5, 00 recv_page_loop: ADD s5, 01 ADDCY s4, 00 COMPARE s4, 02 JUMP NZ, recv_page_recv COMPARE s5, 11 JUMP Z, recv_page_exit recv_page_recv: INPUT s0, KEYS AND s0, KEY_CENTER JUMP Z, recv_page_end INPUT s0, UART_CTRL AND s0, 02 JUMP NZ, recv_page_recv INPUT s0, UART_DATA CALL do_spi ; write data JUMP recv_page_loop recv_page_end: ; check if 528 bytes were written COMPARE s4, 02 JUMP NZ, recv_page_wff COMPARE s5, 10 JUMP Z, recv_page_exit recv_page_wff: ; write terminating FF if bytes < 528 LOAD s0, FF CALL do_spi recv_page_exit: LOAD s0, 01 OUTPUT s0, SPI_CTRL ; Chip select high RETURN ; send page; s0..s5 overwritten send_page: LOAD s2, PAGE_MSB LOAD s3, PAGE_LSB SL0 s3 ; shift top 2 bits to s2 SLA s2 SL0 s3 SLA s2 CALL spi_busy LOAD s0, 00 OUTPUT s0, SPI_CTRL ; Chip select low LOAD s0, D2 ; Main Memory Page Read CALL do_spi ; write command LOAD s0, s2 CALL do_spi ; write addr LOAD s0, s3 CALL do_spi ; write addr LOAD s0, 00 CALL do_spi ; write addr CALL do_spi ; write don't care CALL do_spi ; write don't care CALL do_spi ; write don't care CALL do_spi ; write don't care LOAD s4, 00 LOAD s5, 00 send_page_loop: ADD s5, 01 ADDCY s4, 00 COMPARE s4, 02 JUMP NZ, send_page_send COMPARE s5, 11 JUMP Z, send_page_end send_page_send: CALL do_spi ; read data COMPARE s0, FF JUMP Z, send_page_end CALL write_data ; dump incoming data send_page_dump: INPUT s0, UART_CTRL AND s0, 02 JUMP NZ, send_page_loop INPUT s0, UART_DATA JUMP send_page_dump send_page_end: LOAD s0, 01 OUTPUT s0, SPI_CTRL ; Chip select high RETURN ; data in s0; return in s0; do_spi: OUTPUT s0, SPI_DATA do_spi_wait: INPUT s0, SPI_CTRL AND s0, 01 JUMP NZ, do_spi_wait INPUT s0, SPI_DATA RETURN ; wait for flash to become unbusy spi_busy: LOAD s0, 00 OUTPUT s0, SPI_CTRL ; Chip select low LOAD s0, D7 CALL do_spi spi_busy_loop: CALL do_spi TEST s0, 80 JUMP Z, spi_busy_loop LOAD s0, 01 OUTPUT s0, SPI_CTRL ; Chip select high RETURN ; clear buffer 1 clear_buffer: CALL spi_busy LOAD s0, 00 OUTPUT s0, SPI_CTRL ; Chip select low LOAD s0, 84 ; Buffer Write CALL do_spi ; write command LOAD s0, 00 CALL do_spi ; write addr LOAD s0, 00 CALL do_spi ; write addr LOAD s0, 00 CALL do_spi ; write addr LOAD s4, 00 LOAD s5, 00 clear_buffer_loop: ADD s5, 01 ADDCY s4, 00 COMPARE s4, 02 JUMP NZ, clear_buffer_write COMPARE s5, 11 JUMP Z, clear_buffer_end clear_buffer_write: LOAD s0, FF CALL do_spi ; read data JUMP clear_buffer_loop clear_buffer_end: LOAD s0, 01 OUTPUT s0, SPI_CTRL ; Chip select high RETURN ; data in s0; s1 overwritten write_data: INPUT s1, UART_CTRL AND s1, 01 JUMP NZ, write_data OUTPUT s0, UART_DATA RETURN ; return in s0 read_data: INPUT s0, UART_CTRL AND s0, 02 JUMP NZ, read_data INPUT s0, UART_DATA RETURN ; data in s0; s0, s1, s2, s3 overwritten write_hex: LOAD s3, s0 LOAD s2, s0 SR0 s2 SR0 s2 SR0 s2 SR0 s2 ADD s2, 30 COMPARE s2, 3A JUMP C, write_hex_outh ADD s2, 07 write_hex_outh: CALL wait_busy LOAD s0, s2 CALL write_display_d LOAD s2, s3 AND s2, 0F ADD s2, 30 COMPARE s2, 3A JUMP C, write_hex_outl ADD s2, 07 write_hex_outl: CALL wait_busy LOAD s0, s2 CALL write_display_d RETURN ; data in s0, s0 overwritten write_display_i: OUTPUT s0, LCD_DATA LOAD s0, 00 LOAD s0, 00 OUTPUT s0, LCD_CTRL LOAD s0, 00 LOAD s0, 00 LOAD s0, 01 OUTPUT s0, LCD_CTRL LOAD s0, 00 LOAD s0, 00 LOAD s0, 00 LOAD s0, 00 LOAD s0, 00 LOAD s0, 00 LOAD s0, 00 LOAD s0, 00 LOAD s0, 00 LOAD s0, 00 LOAD s0, 00 LOAD s0, 00 OUTPUT s0, LCD_CTRL LOAD s0, 00 LOAD s0, 00 LOAD s0, 00 LOAD s0, 00 LOAD s0, 00 LOAD s0, 00 LOAD s0, 00 LOAD s0, 00 LOAD s0, 00 LOAD s0, 00 RETURN ; zero flag reset if busy; s0, s1 overwritten busy_display: LOAD s0, 04 OUTPUT s0, LCD_CTRL LOAD s0, 00 LOAD s0, 05 OUTPUT s0, LCD_CTRL LOAD s0, 00 LOAD s0, 00 LOAD s0, 00 LOAD s0, 00 LOAD s0, 00 LOAD s0, 00 LOAD s0, 00 LOAD s0, 00 LOAD s0, 00 LOAD s0, 00 INPUT s1, LCD_DATA LOAD s0, 00 OUTPUT s0, LCD_CTRL LOAD s0, 00 LOAD s0, 00 LOAD s0, 00 LOAD s0, 00 LOAD s0, 00 LOAD s0, 00 LOAD s0, 00 LOAD s0, 00 LOAD s0, 00 LOAD s0, 00 LOAD s0, 00 AND s1, 80 RETURN wait_busy: CALL busy_display JUMP NZ, wait_busy RETURN ; data in s0, s0 is overwritten write_display_d: OUTPUT s0, LCD_DATA LOAD s0, 00 LOAD s0, 02 OUTPUT s0, LCD_CTRL LOAD s0, 00 LOAD s0, 00 LOAD s0, 03 OUTPUT s0, LCD_CTRL LOAD s0, 00 LOAD s0, 00 LOAD s0, 00 LOAD s0, 00 LOAD s0, 00 LOAD s0, 00 LOAD s0, 00 LOAD s0, 00 LOAD s0, 00 LOAD s0, 00 LOAD s0, 00 LOAD s0, 02 OUTPUT s0, LCD_CTRL LOAD s0, 00 LOAD s0, 00 LOAD s0, 00 LOAD s0, 00 LOAD s0, 00 LOAD s0, 00 LOAD s0, 00 LOAD s0, 00 LOAD s0, 00 LOAD s0, 00 RETURN