Pico-sized STM32F103 dev board
An exercise to learn SMT PCB design. Licensed CC BY-SA 4.0. Signed-off-by: Matthias Blankertz <matthias@blankertz.org>
This commit is contained in:
48
.gitignore
vendored
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48
.gitignore
vendored
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# Created by https://www.toptal.com/developers/gitignore/api/kicad
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# Edit at https://www.toptal.com/developers/gitignore?templates=kicad
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### KiCad ###
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# For PCBs designed using KiCad: https://www.kicad.org/
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# Format documentation: https://kicad.org/help/file-formats/
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# Temporary files
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*.000
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*.bak
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*.bck
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*.kicad_pcb-bak
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*.kicad_sch-bak
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*-backups
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*.kicad_prl
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*.sch-bak
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*~
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_autosave-*
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*.tmp
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*-save.pro
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*-save.kicad_pcb
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fp-info-cache
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# Netlist files (exported from Eeschema)
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*.net
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# Autorouter files (exported from Pcbnew)
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*.dsn
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*.ses
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# Exported BOM files
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*.xml
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*.csv
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### KiCad Patch ###
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rescue-backup/
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*.tsv
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bom/
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# Gerber export output
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out/
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# End of https://www.toptal.com/developers/gitignore/api/kicad
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production/
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~*.lck
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1
fabrication-toolkit-options.json
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1
fabrication-toolkit-options.json
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@@ -0,0 +1 @@
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{"ARCHIVE_NAME": "", "EXTRA_LAYERS": "", "ALL_ACTIVE_LAYERS": false, "EXTEND_EDGE_CUT": false, "ALTERNATIVE_EDGE_CUT": false, "AUTO TRANSLATE": true, "AUTO FILL": true, "EXCLUDE DNP": false}
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138
mini-stm-board.kicad_dru
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138
mini-stm-board.kicad_dru
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(version 1)
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# Custom Design Rules (DRC) for KiCAD 7.0 (Stored in '<project>.kicad_dru' file).
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#
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# Matching JLCPCB capabilities: https://jlcpcb.com/capabilities/pcb-capabilities
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#
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# KiCad documentation: https://docs.kicad.org/master/id/pcbnew/pcbnew_advanced.html#custom_design_rules
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#
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# Inspiration
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# - https://gist.github.com/darkxst/f713268e5469645425eed40115fb8b49 (with comments)
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# - https://gist.github.com/denniskupec/e163d13b0a64c2044bd259f64659485e (with comments)
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# TODO new rule: NPTH pads.
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# Inner diameter of pad should be 0.4-0.5 mm larger than NPTH drill diameter.
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# JLCPCB: "We make NPTH via dry sealing film process, if customer would like a NPTH but around with pad/copper, our engineer will dig out around pad/copper about 0.2mm-0.25mm, otherwise the metal potion will be flowed into the hole and it becomes a PTH. (there will be no copper dig out optimization for single board)."
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# TODO: new rule for plated slots: min diameter/width 0.5mm
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# JLCPCB: "The minimum plated slot width is 0.5mm, which is drawn with a pad."
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# TODO new rule: non-plated slots: min diameter/width 1.0mm
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# JLCPCB: "The minimum Non-Plated Slot Width is 1.0mm, please draw the slot outline in the mechanical layer(GML or GKO)""
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(rule "Track width, outer layer (1oz copper)"
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(layer outer)
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(condition "A.Type == 'track'")
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(constraint track_width (min 0.127mm))
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)
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(rule "Track spacing, outer layer (1oz copper)"
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(layer outer)
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(condition "A.Type == 'track' && B.Type == A.Type")
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(constraint clearance (min 0.127mm))
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)
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(rule "Track width, inner layer"
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(layer inner)
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(condition "A.Type == 'track'")
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(constraint track_width (min 0.09mm))
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)
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(rule "Track spacing, inner layer"
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(layer inner)
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(condition "A.Type == 'track' && B.Type == A.Type")
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(constraint clearance (min 0.09mm))
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)
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(rule "Silkscreen text"
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(layer "?.Silkscreen")
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(condition "A.Type == 'Text' || A.Type == 'Text Box'")
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(constraint text_thickness (min 0.15mm))
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(constraint text_height (min 1mm))
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)
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(rule "Pad to Silkscreen"
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(layer outer)
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(condition "A.Type == 'pad' && B.Layer == '?.Silkscreen'")
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(constraint silk_clearance (min 0.15mm))
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)
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(rule "Edge (routed) to track clearance"
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(condition "A.Type == 'track'")
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(constraint edge_clearance (min 0.3mm))
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)
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#(rule "Edge (v-cut) to track clearance"
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# (condition "A.Type == 'track'")
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# (constraint edge_clearance (min 0.4mm))
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#)
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# JLCPCB restrictions ambiguous:
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# Illustration: 0.2 mm, 1&2 layer: 0.3 mm, multilayer: "(0.15mm more costly)"
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# This rule handles diameter minimum and maximum for ALL holes.
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# Other specialized rules handle restrictions (e.g. Via, PTH, NPTH)
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(rule "Hole diameter"
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(constraint hole_size (min 0.2mm) (max 6.3mm))
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)
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(rule "Hole (NPTH) diameter"
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(layer outer)
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(condition "!A.isPlated()")
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(constraint hole_size (min 0.5mm))
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)
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# TODO: Hole to board edge ≥ 1 mm. Min. board size 10 × 10 mm
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(rule "Hole (castellated) diameter"
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(layer outer)
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(condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'")
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(constraint hole_size (min 0.6mm))
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)
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# JLCPCB: "Via diameter should be 0.1mm(0.15mm preferred) larger than Via hole size" (illustration shows diameters for both dimensions)
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# JLCPCB: PTH: "The annular ring size will be enlarged to 0.15mm in production."
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(rule "Annular ring width (via and PTH)"
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(layer outer)
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(condition "A.isPlated()")
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(constraint annular_width (min 0.075mm))
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)
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(rule "Clearance: hole to hole (perimeter), different nets"
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(layer outer)
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(condition "A.Net != B.Net && (A.Type != 'Via' || B.Type != 'Via')")
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(constraint hole_to_hole (min 0.5mm))
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)
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(rule "Clearance: via to via (perimeter), different nets"
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(layer outer)
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(condition "A.Net != B.Net && A.Type == 'Via' && B.Type == 'Via'")
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(constraint hole_to_hole (min 0.2mm))
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)
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(rule "Clearance: hole to hole (perimeter), same net"
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(layer outer)
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(condition "A.Net == B.Net")
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(constraint hole_to_hole (min 0.254mm))
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)
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(rule "Clearance: track to NPTH hole (perimeter)"
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# (condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track' && A.Net != B.Net")
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(condition "!A.isPlated() && B.Type == 'track' && A.Net != B.Net")
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(constraint hole_clearance (min 0.254mm))
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)
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(rule "Clearance: track to PTH hole perimeter"
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(condition "A.isPlated() && B.Type == 'track' && A.Net != B.Net")
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(constraint hole_clearance (min 0.33mm))
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)
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# TODO: try combining with rule "Clearance: PTH to track, different nets"
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(rule "Clearance: track to pad"
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(condition "A.Type == 'pad' && B.Type == 'track' && A.Net != B.Net")
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(constraint clearance (min 0.2mm))
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)
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(rule "Clearance: pad/via to pad/via"
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(layer outer)
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# (condition "(A.Type == 'Pad' || A.Type == 'Via') && (B.Type == 'Pad' || B.Type == 'Via') && A.Net != B.Net")
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(condition "A.isPlated() && B.isPlated() && A.Net != B.Net")
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(constraint clearance (min 0.2mm))
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)
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19536
mini-stm-board.kicad_pcb
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19536
mini-stm-board.kicad_pcb
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File diff suppressed because it is too large
Load Diff
133
mini-stm-board.kicad_prl
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133
mini-stm-board.kicad_prl
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{
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"board": {
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"active_layer": 5,
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"active_layer_preset": "",
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"auto_track_width": true,
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"hidden_netclasses": [],
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"hidden_nets": [
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"GND"
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],
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"high_contrast_mode": 0,
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"net_color_mode": 1,
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"opacity": {
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"images": 0.6,
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"pads": 1.0,
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"shapes": 1.0,
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"tracks": 1.0,
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"vias": 1.0,
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"zones": 0.6
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},
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"selection_filter": {
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"dimensions": false,
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"footprints": true,
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"graphics": false,
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"keepouts": false,
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"lockedItems": false,
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"otherItems": false,
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"pads": true,
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"text": true,
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"tracks": true,
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"vias": true,
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"zones": true
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},
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"visible_items": [
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"vias",
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"footprint_text",
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"footprint_anchors",
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"ratsnest",
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"grid",
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"footprints_front",
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"footprints_back",
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"footprint_values",
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"footprint_references",
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"tracks",
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"drc_errors",
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"drawing_sheet",
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"bitmaps",
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"pads",
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"zones",
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"drc_warnings",
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"drc_exclusions",
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"locked_item_shadows",
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"conflict_shadows",
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"shapes"
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],
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"visible_layers": "ffffffff_ffffffff_ffffffff_ffffffff",
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"zone_display_mode": 0
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},
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"git": {
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"repo_type": "",
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"repo_username": "",
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"ssh_key": ""
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},
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"meta": {
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"filename": "mini-stm-board.kicad_prl",
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"version": 5
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},
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"net_inspector_panel": {
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"col_hidden": [
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false
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],
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"col_order": [
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0,
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1,
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2,
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3,
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4,
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5,
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6,
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7,
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8,
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9
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],
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"col_widths": [
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0
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],
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"custom_group_rules": [],
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"expanded_rows": [],
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"filter_by_net_name": true,
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"filter_by_netclass": true,
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"filter_text": "",
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"group_by_constraint": false,
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"group_by_netclass": false,
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"show_unconnected_nets": false,
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"show_zero_pad_nets": false,
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"sort_ascending": true,
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"sorting_column": 0
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},
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"open_jobsets": [],
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"project": {
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"files": []
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},
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"schematic": {
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"selection_filter": {
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"graphics": true,
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"images": true,
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"labels": true,
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"lockedItems": false,
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"otherItems": true,
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"pins": true,
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"symbols": true,
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"text": true,
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"wires": true
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}
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}
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}
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1070
mini-stm-board.kicad_pro
Normal file
1070
mini-stm-board.kicad_pro
Normal file
File diff suppressed because it is too large
Load Diff
18947
mini-stm-board.kicad_sch
Normal file
18947
mini-stm-board.kicad_sch
Normal file
File diff suppressed because it is too large
Load Diff
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