rev. 1
This commit is contained in:
470
puya32-breakout.panel.kicad_dru
Normal file
470
puya32-breakout.panel.kicad_dru
Normal file
@@ -0,0 +1,470 @@
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(version 1)
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(rule "Board_0-Track width, outer layer (1oz copper)"
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(layer outer)
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(condition "A.Type == 'track'")
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(constraint track_width (min 0.127mm))
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)
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(rule "Board_0-Track spacing, outer layer (1oz copper)"
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(layer outer)
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(condition "A.Type == 'track' && B.Type == A.Type")
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(constraint clearance (min 0.127mm))
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)
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(rule "Board_0-Track width, inner layer"
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(layer inner)
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(condition "A.Type == 'track'")
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(constraint track_width (min 0.09mm))
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)
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(rule "Board_0-Track spacing, inner layer"
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(layer inner)
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||||
(condition "A.Type == 'track' && B.Type == A.Type")
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(constraint clearance (min 0.09mm))
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)
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(rule "Board_0-Silkscreen text"
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(layer "?.Silkscreen")
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(condition "A.Type == 'Text' || A.Type == 'Text Box'")
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(constraint text_thickness (min 0.15mm))
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(constraint text_height (min 1mm))
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)
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(rule "Board_0-Pad to Silkscreen"
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(layer outer)
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(condition "A.Type == 'pad' && B.Layer == '?.Silkscreen'")
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(constraint silk_clearance (min 0.15mm))
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)
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(rule "Board_0-Edge (routed) to track clearance"
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(condition "A.Type == 'track'")
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(constraint edge_clearance (min 0.3mm))
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)
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#(rule "Edge (v-cut) to track clearance"
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# (condition "A.Type == 'track'")
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# (constraint edge_clearance (min 0.4mm))
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#)
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# JLCPCB restrictions ambiguous:
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# Illustration: 0.2 mm, 1&2 layer: 0.3 mm, multilayer: "(0.15mm more costly)"
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# This rule handles diameter minimum and maximum for ALL holes.
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# Other specialized rules handle restrictions (e.g. Via, PTH, NPTH)
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(rule "Board_0-Hole diameter"
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(constraint hole_size (min 0.3mm) (max 6.3mm))
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)
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(rule "Board_0-Hole (NPTH) diameter"
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(layer outer)
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(condition "!A.isPlated()")
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(constraint hole_size (min 0.5mm))
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)
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# TODO: Hole to board edge ≥ 1 mm. Min. board size 10 × 10 mm
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(rule "Board_0-Hole (castellated) diameter"
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(layer outer)
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(condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'")
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(constraint hole_size (min 0.6mm))
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)
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# JLCPCB: "Via diameter should be 0.1mm(0.15mm preferred) larger than Via hole size" (illustration shows diameters for both dimensions)
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# JLCPCB: PTH: "The annular ring size will be enlarged to 0.15mm in production."
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(rule "Board_0-Annular ring width (via and PTH)"
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(layer outer)
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(condition "A.isPlated()")
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(constraint annular_width (min 0.075mm))
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)
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(rule "Board_0-Clearance: hole to hole (perimeter), different nets"
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(layer outer)
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(condition "A.Net != B.Net && (A.Type != 'Via' || B.Type != 'Via')")
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(constraint hole_to_hole (min 0.5mm))
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)
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(rule "Board_0-Clearance: via to via (perimeter), different nets"
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(layer outer)
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(condition "A.Net != B.Net && A.Type == 'Via' && B.Type == 'Via'")
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(constraint hole_to_hole (min 0.2mm))
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)
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(rule "Board_0-Clearance: hole to hole (perimeter), same net"
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(layer outer)
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(condition "A.Net == B.Net")
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(constraint hole_to_hole (min 0.254mm))
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)
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(rule "Board_0-Clearance: track to NPTH hole (perimeter)"
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# (condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track' && A.Net != B.Net")
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(condition "!A.isPlated() && B.Type == 'track' && A.Net != B.Net")
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(constraint hole_clearance (min 0.254mm))
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)
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(rule "Board_0-Clearance: track to PTH hole perimeter"
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(condition "A.isPlated() && B.Type == 'track' && A.Net != B.Net")
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(constraint hole_clearance (min 0.33mm))
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)
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||||
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# TODO: try combining with rule "Clearance: PTH to track, different nets"
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(rule "Board_0-Clearance: track to pad"
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(condition "A.Type == 'pad' && B.Type == 'track' && A.Net != B.Net")
|
||||
(constraint clearance (min 0.2mm))
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)
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||||
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(rule "Board_0-Clearance: pad/via to pad/via"
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(layer outer)
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# (condition "(A.Type == 'Pad' || A.Type == 'Via') && (B.Type == 'Pad' || B.Type == 'Via') && A.Net != B.Net")
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(condition "A.isPlated() && B.isPlated() && A.Net != B.Net")
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(constraint clearance (min 0.2mm))
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)
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(rule "Board_1-Track width, outer layer (1oz copper)"
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(layer outer)
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(condition "A.Type == 'track'")
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(constraint track_width (min 0.127mm))
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)
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||||
|
||||
(rule "Board_1-Track spacing, outer layer (1oz copper)"
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(layer outer)
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||||
(condition "A.Type == 'track' && B.Type == A.Type")
|
||||
(constraint clearance (min 0.127mm))
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)
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||||
|
||||
(rule "Board_1-Track width, inner layer"
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||||
(layer inner)
|
||||
(condition "A.Type == 'track'")
|
||||
(constraint track_width (min 0.09mm))
|
||||
)
|
||||
|
||||
(rule "Board_1-Track spacing, inner layer"
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||||
(layer inner)
|
||||
(condition "A.Type == 'track' && B.Type == A.Type")
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||||
(constraint clearance (min 0.09mm))
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)
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(rule "Board_1-Silkscreen text"
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(layer "?.Silkscreen")
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(condition "A.Type == 'Text' || A.Type == 'Text Box'")
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(constraint text_thickness (min 0.15mm))
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||||
(constraint text_height (min 1mm))
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||||
)
|
||||
|
||||
(rule "Board_1-Pad to Silkscreen"
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||||
(layer outer)
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||||
(condition "A.Type == 'pad' && B.Layer == '?.Silkscreen'")
|
||||
(constraint silk_clearance (min 0.15mm))
|
||||
)
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||||
|
||||
(rule "Board_1-Edge (routed) to track clearance"
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||||
(condition "A.Type == 'track'")
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(constraint edge_clearance (min 0.3mm))
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||||
)
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||||
|
||||
#(rule "Edge (v-cut) to track clearance"
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||||
# (condition "A.Type == 'track'")
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||||
# (constraint edge_clearance (min 0.4mm))
|
||||
#)
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||||
|
||||
# JLCPCB restrictions ambiguous:
|
||||
# Illustration: 0.2 mm, 1&2 layer: 0.3 mm, multilayer: "(0.15mm more costly)"
|
||||
# This rule handles diameter minimum and maximum for ALL holes.
|
||||
# Other specialized rules handle restrictions (e.g. Via, PTH, NPTH)
|
||||
(rule "Board_1-Hole diameter"
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||||
(constraint hole_size (min 0.3mm) (max 6.3mm))
|
||||
)
|
||||
|
||||
(rule "Board_1-Hole (NPTH) diameter"
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||||
(layer outer)
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||||
(condition "!A.isPlated()")
|
||||
(constraint hole_size (min 0.5mm))
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||||
)
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||||
|
||||
# TODO: Hole to board edge ≥ 1 mm. Min. board size 10 × 10 mm
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||||
(rule "Board_1-Hole (castellated) diameter"
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||||
(layer outer)
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||||
(condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'")
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(constraint hole_size (min 0.6mm))
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||||
)
|
||||
|
||||
# JLCPCB: "Via diameter should be 0.1mm(0.15mm preferred) larger than Via hole size" (illustration shows diameters for both dimensions)
|
||||
# JLCPCB: PTH: "The annular ring size will be enlarged to 0.15mm in production."
|
||||
(rule "Board_1-Annular ring width (via and PTH)"
|
||||
(layer outer)
|
||||
(condition "A.isPlated()")
|
||||
(constraint annular_width (min 0.075mm))
|
||||
)
|
||||
|
||||
(rule "Board_1-Clearance: hole to hole (perimeter), different nets"
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||||
(layer outer)
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||||
(condition "A.Net != B.Net && (A.Type != 'Via' || B.Type != 'Via')")
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(constraint hole_to_hole (min 0.5mm))
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)
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||||
|
||||
(rule "Board_1-Clearance: via to via (perimeter), different nets"
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||||
(layer outer)
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||||
(condition "A.Net != B.Net && A.Type == 'Via' && B.Type == 'Via'")
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(constraint hole_to_hole (min 0.2mm))
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)
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||||
|
||||
(rule "Board_1-Clearance: hole to hole (perimeter), same net"
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||||
(layer outer)
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||||
(condition "A.Net == B.Net")
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||||
(constraint hole_to_hole (min 0.254mm))
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||||
)
|
||||
|
||||
(rule "Board_1-Clearance: track to NPTH hole (perimeter)"
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||||
# (condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track' && A.Net != B.Net")
|
||||
(condition "!A.isPlated() && B.Type == 'track' && A.Net != B.Net")
|
||||
(constraint hole_clearance (min 0.254mm))
|
||||
)
|
||||
|
||||
(rule "Board_1-Clearance: track to PTH hole perimeter"
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||||
(condition "A.isPlated() && B.Type == 'track' && A.Net != B.Net")
|
||||
(constraint hole_clearance (min 0.33mm))
|
||||
)
|
||||
|
||||
# TODO: try combining with rule "Clearance: PTH to track, different nets"
|
||||
(rule "Board_1-Clearance: track to pad"
|
||||
(condition "A.Type == 'pad' && B.Type == 'track' && A.Net != B.Net")
|
||||
(constraint clearance (min 0.2mm))
|
||||
)
|
||||
|
||||
(rule "Board_1-Clearance: pad/via to pad/via"
|
||||
(layer outer)
|
||||
# (condition "(A.Type == 'Pad' || A.Type == 'Via') && (B.Type == 'Pad' || B.Type == 'Via') && A.Net != B.Net")
|
||||
(condition "A.isPlated() && B.isPlated() && A.Net != B.Net")
|
||||
(constraint clearance (min 0.2mm))
|
||||
)
|
||||
(rule "Board_2-Track width, outer layer (1oz copper)"
|
||||
(layer outer)
|
||||
(condition "A.Type == 'track'")
|
||||
(constraint track_width (min 0.127mm))
|
||||
)
|
||||
|
||||
(rule "Board_2-Track spacing, outer layer (1oz copper)"
|
||||
(layer outer)
|
||||
(condition "A.Type == 'track' && B.Type == A.Type")
|
||||
(constraint clearance (min 0.127mm))
|
||||
)
|
||||
|
||||
(rule "Board_2-Track width, inner layer"
|
||||
(layer inner)
|
||||
(condition "A.Type == 'track'")
|
||||
(constraint track_width (min 0.09mm))
|
||||
)
|
||||
|
||||
(rule "Board_2-Track spacing, inner layer"
|
||||
(layer inner)
|
||||
(condition "A.Type == 'track' && B.Type == A.Type")
|
||||
(constraint clearance (min 0.09mm))
|
||||
)
|
||||
|
||||
(rule "Board_2-Silkscreen text"
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(layer "?.Silkscreen")
|
||||
(condition "A.Type == 'Text' || A.Type == 'Text Box'")
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||||
(constraint text_thickness (min 0.15mm))
|
||||
(constraint text_height (min 1mm))
|
||||
)
|
||||
|
||||
(rule "Board_2-Pad to Silkscreen"
|
||||
(layer outer)
|
||||
(condition "A.Type == 'pad' && B.Layer == '?.Silkscreen'")
|
||||
(constraint silk_clearance (min 0.15mm))
|
||||
)
|
||||
|
||||
(rule "Board_2-Edge (routed) to track clearance"
|
||||
(condition "A.Type == 'track'")
|
||||
(constraint edge_clearance (min 0.3mm))
|
||||
)
|
||||
|
||||
#(rule "Edge (v-cut) to track clearance"
|
||||
# (condition "A.Type == 'track'")
|
||||
# (constraint edge_clearance (min 0.4mm))
|
||||
#)
|
||||
|
||||
# JLCPCB restrictions ambiguous:
|
||||
# Illustration: 0.2 mm, 1&2 layer: 0.3 mm, multilayer: "(0.15mm more costly)"
|
||||
# This rule handles diameter minimum and maximum for ALL holes.
|
||||
# Other specialized rules handle restrictions (e.g. Via, PTH, NPTH)
|
||||
(rule "Board_2-Hole diameter"
|
||||
(constraint hole_size (min 0.3mm) (max 6.3mm))
|
||||
)
|
||||
|
||||
(rule "Board_2-Hole (NPTH) diameter"
|
||||
(layer outer)
|
||||
(condition "!A.isPlated()")
|
||||
(constraint hole_size (min 0.5mm))
|
||||
)
|
||||
|
||||
# TODO: Hole to board edge ≥ 1 mm. Min. board size 10 × 10 mm
|
||||
(rule "Board_2-Hole (castellated) diameter"
|
||||
(layer outer)
|
||||
(condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'")
|
||||
(constraint hole_size (min 0.6mm))
|
||||
)
|
||||
|
||||
# JLCPCB: "Via diameter should be 0.1mm(0.15mm preferred) larger than Via hole size" (illustration shows diameters for both dimensions)
|
||||
# JLCPCB: PTH: "The annular ring size will be enlarged to 0.15mm in production."
|
||||
(rule "Board_2-Annular ring width (via and PTH)"
|
||||
(layer outer)
|
||||
(condition "A.isPlated()")
|
||||
(constraint annular_width (min 0.075mm))
|
||||
)
|
||||
|
||||
(rule "Board_2-Clearance: hole to hole (perimeter), different nets"
|
||||
(layer outer)
|
||||
(condition "A.Net != B.Net && (A.Type != 'Via' || B.Type != 'Via')")
|
||||
(constraint hole_to_hole (min 0.5mm))
|
||||
)
|
||||
|
||||
(rule "Board_2-Clearance: via to via (perimeter), different nets"
|
||||
(layer outer)
|
||||
(condition "A.Net != B.Net && A.Type == 'Via' && B.Type == 'Via'")
|
||||
(constraint hole_to_hole (min 0.2mm))
|
||||
)
|
||||
|
||||
(rule "Board_2-Clearance: hole to hole (perimeter), same net"
|
||||
(layer outer)
|
||||
(condition "A.Net == B.Net")
|
||||
(constraint hole_to_hole (min 0.254mm))
|
||||
)
|
||||
|
||||
(rule "Board_2-Clearance: track to NPTH hole (perimeter)"
|
||||
# (condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track' && A.Net != B.Net")
|
||||
(condition "!A.isPlated() && B.Type == 'track' && A.Net != B.Net")
|
||||
(constraint hole_clearance (min 0.254mm))
|
||||
)
|
||||
|
||||
(rule "Board_2-Clearance: track to PTH hole perimeter"
|
||||
(condition "A.isPlated() && B.Type == 'track' && A.Net != B.Net")
|
||||
(constraint hole_clearance (min 0.33mm))
|
||||
)
|
||||
|
||||
# TODO: try combining with rule "Clearance: PTH to track, different nets"
|
||||
(rule "Board_2-Clearance: track to pad"
|
||||
(condition "A.Type == 'pad' && B.Type == 'track' && A.Net != B.Net")
|
||||
(constraint clearance (min 0.2mm))
|
||||
)
|
||||
|
||||
(rule "Board_2-Clearance: pad/via to pad/via"
|
||||
(layer outer)
|
||||
# (condition "(A.Type == 'Pad' || A.Type == 'Via') && (B.Type == 'Pad' || B.Type == 'Via') && A.Net != B.Net")
|
||||
(condition "A.isPlated() && B.isPlated() && A.Net != B.Net")
|
||||
(constraint clearance (min 0.2mm))
|
||||
)
|
||||
(rule "Board_3-Track width, outer layer (1oz copper)"
|
||||
(layer outer)
|
||||
(condition "A.Type == 'track'")
|
||||
(constraint track_width (min 0.127mm))
|
||||
)
|
||||
|
||||
(rule "Board_3-Track spacing, outer layer (1oz copper)"
|
||||
(layer outer)
|
||||
(condition "A.Type == 'track' && B.Type == A.Type")
|
||||
(constraint clearance (min 0.127mm))
|
||||
)
|
||||
|
||||
(rule "Board_3-Track width, inner layer"
|
||||
(layer inner)
|
||||
(condition "A.Type == 'track'")
|
||||
(constraint track_width (min 0.09mm))
|
||||
)
|
||||
|
||||
(rule "Board_3-Track spacing, inner layer"
|
||||
(layer inner)
|
||||
(condition "A.Type == 'track' && B.Type == A.Type")
|
||||
(constraint clearance (min 0.09mm))
|
||||
)
|
||||
|
||||
(rule "Board_3-Silkscreen text"
|
||||
(layer "?.Silkscreen")
|
||||
(condition "A.Type == 'Text' || A.Type == 'Text Box'")
|
||||
(constraint text_thickness (min 0.15mm))
|
||||
(constraint text_height (min 1mm))
|
||||
)
|
||||
|
||||
(rule "Board_3-Pad to Silkscreen"
|
||||
(layer outer)
|
||||
(condition "A.Type == 'pad' && B.Layer == '?.Silkscreen'")
|
||||
(constraint silk_clearance (min 0.15mm))
|
||||
)
|
||||
|
||||
(rule "Board_3-Edge (routed) to track clearance"
|
||||
(condition "A.Type == 'track'")
|
||||
(constraint edge_clearance (min 0.3mm))
|
||||
)
|
||||
|
||||
#(rule "Edge (v-cut) to track clearance"
|
||||
# (condition "A.Type == 'track'")
|
||||
# (constraint edge_clearance (min 0.4mm))
|
||||
#)
|
||||
|
||||
# JLCPCB restrictions ambiguous:
|
||||
# Illustration: 0.2 mm, 1&2 layer: 0.3 mm, multilayer: "(0.15mm more costly)"
|
||||
# This rule handles diameter minimum and maximum for ALL holes.
|
||||
# Other specialized rules handle restrictions (e.g. Via, PTH, NPTH)
|
||||
(rule "Board_3-Hole diameter"
|
||||
(constraint hole_size (min 0.3mm) (max 6.3mm))
|
||||
)
|
||||
|
||||
(rule "Board_3-Hole (NPTH) diameter"
|
||||
(layer outer)
|
||||
(condition "!A.isPlated()")
|
||||
(constraint hole_size (min 0.5mm))
|
||||
)
|
||||
|
||||
# TODO: Hole to board edge ≥ 1 mm. Min. board size 10 × 10 mm
|
||||
(rule "Board_3-Hole (castellated) diameter"
|
||||
(layer outer)
|
||||
(condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'")
|
||||
(constraint hole_size (min 0.6mm))
|
||||
)
|
||||
|
||||
# JLCPCB: "Via diameter should be 0.1mm(0.15mm preferred) larger than Via hole size" (illustration shows diameters for both dimensions)
|
||||
# JLCPCB: PTH: "The annular ring size will be enlarged to 0.15mm in production."
|
||||
(rule "Board_3-Annular ring width (via and PTH)"
|
||||
(layer outer)
|
||||
(condition "A.isPlated()")
|
||||
(constraint annular_width (min 0.075mm))
|
||||
)
|
||||
|
||||
(rule "Board_3-Clearance: hole to hole (perimeter), different nets"
|
||||
(layer outer)
|
||||
(condition "A.Net != B.Net && (A.Type != 'Via' || B.Type != 'Via')")
|
||||
(constraint hole_to_hole (min 0.5mm))
|
||||
)
|
||||
|
||||
(rule "Board_3-Clearance: via to via (perimeter), different nets"
|
||||
(layer outer)
|
||||
(condition "A.Net != B.Net && A.Type == 'Via' && B.Type == 'Via'")
|
||||
(constraint hole_to_hole (min 0.2mm))
|
||||
)
|
||||
|
||||
(rule "Board_3-Clearance: hole to hole (perimeter), same net"
|
||||
(layer outer)
|
||||
(condition "A.Net == B.Net")
|
||||
(constraint hole_to_hole (min 0.254mm))
|
||||
)
|
||||
|
||||
(rule "Board_3-Clearance: track to NPTH hole (perimeter)"
|
||||
# (condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track' && A.Net != B.Net")
|
||||
(condition "!A.isPlated() && B.Type == 'track' && A.Net != B.Net")
|
||||
(constraint hole_clearance (min 0.254mm))
|
||||
)
|
||||
|
||||
(rule "Board_3-Clearance: track to PTH hole perimeter"
|
||||
(condition "A.isPlated() && B.Type == 'track' && A.Net != B.Net")
|
||||
(constraint hole_clearance (min 0.33mm))
|
||||
)
|
||||
|
||||
# TODO: try combining with rule "Clearance: PTH to track, different nets"
|
||||
(rule "Board_3-Clearance: track to pad"
|
||||
(condition "A.Type == 'pad' && B.Type == 'track' && A.Net != B.Net")
|
||||
(constraint clearance (min 0.2mm))
|
||||
)
|
||||
|
||||
(rule "Board_3-Clearance: pad/via to pad/via"
|
||||
(layer outer)
|
||||
# (condition "(A.Type == 'Pad' || A.Type == 'Via') && (B.Type == 'Pad' || B.Type == 'Via') && A.Net != B.Net")
|
||||
(condition "A.isPlated() && B.isPlated() && A.Net != B.Net")
|
||||
(constraint clearance (min 0.2mm))
|
||||
)
|
||||
Reference in New Issue
Block a user