(version 1)

(rule "Board_0-Track width, outer layer (1oz copper)"
	(layer outer)
	(condition "A.Type == 'track'")
	(constraint track_width (min 0.127mm))
)

(rule "Board_0-Track spacing, outer layer (1oz copper)"
	(layer outer)
	(condition "A.Type == 'track' && B.Type == A.Type")
	(constraint clearance (min 0.127mm))
)

(rule "Board_0-Track width, inner layer"
	(layer inner)
	(condition "A.Type == 'track'")
	(constraint track_width (min 0.09mm))
)

(rule "Board_0-Track spacing, inner layer"
	(layer inner)
	(condition "A.Type == 'track' && B.Type == A.Type")
	(constraint clearance (min 0.09mm))
)

(rule "Board_0-Silkscreen text"
	(layer "?.Silkscreen")
	(condition "A.Type == 'Text' || A.Type == 'Text Box'")
	(constraint text_thickness (min 0.15mm))
	(constraint text_height (min 1mm))
)

(rule "Board_0-Pad to Silkscreen"
	(layer outer)
	(condition "A.Type == 'pad' && B.Layer == '?.Silkscreen'")
	(constraint silk_clearance (min 0.15mm))
)

(rule "Board_0-Edge (routed) to track clearance"
	(condition "A.Type == 'track'")
	(constraint edge_clearance (min 0.3mm))
)

#(rule "Edge (v-cut) to track clearance"
#	(condition "A.Type == 'track'")
#	(constraint edge_clearance (min 0.4mm))
#)

# JLCPCB restrictions ambiguous:
# Illustration: 0.2 mm, 1&2 layer: 0.3 mm, multilayer: "(0.15mm more costly)"
# This rule handles diameter minimum and maximum for ALL holes.
# Other specialized rules handle restrictions (e.g. Via, PTH, NPTH) 
(rule "Board_0-Hole diameter"
	(constraint hole_size (min 0.3mm) (max 6.3mm))
)

(rule "Board_0-Hole (NPTH) diameter"
	(layer outer)
	(condition "!A.isPlated()")
	(constraint hole_size (min 0.5mm))
)

# TODO: Hole to board edge ≥ 1 mm. Min. board size 10 × 10 mm
(rule "Board_0-Hole (castellated) diameter"
	(layer outer)
	(condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'")
	(constraint hole_size (min 0.6mm))
)

# JLCPCB: "Via diameter should be 0.1mm(0.15mm preferred) larger than Via hole size" (illustration shows diameters for both dimensions)
# JLCPCB: PTH: "The annular ring size will be enlarged to 0.15mm in production."
(rule "Board_0-Annular ring width (via and PTH)"
	(layer outer)
	(condition "A.isPlated()")
	(constraint annular_width (min 0.075mm))
)

(rule "Board_0-Clearance: hole to hole (perimeter), different nets"
	(layer outer)
	(condition "A.Net != B.Net && (A.Type != 'Via' || B.Type != 'Via')")
	(constraint hole_to_hole (min 0.5mm))
)

(rule "Board_0-Clearance: via to via (perimeter), different nets"
	(layer outer)
	(condition "A.Net != B.Net && A.Type == 'Via' && B.Type == 'Via'")
	(constraint hole_to_hole (min 0.2mm))
)

(rule "Board_0-Clearance: hole to hole (perimeter), same net"
	(layer outer)
	(condition "A.Net == B.Net")
	(constraint hole_to_hole (min 0.254mm))
)

(rule "Board_0-Clearance: track to NPTH hole (perimeter)"
#	(condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track' && A.Net != B.Net")
	(condition "!A.isPlated() && B.Type == 'track' && A.Net != B.Net")
	(constraint hole_clearance (min 0.254mm))
)

(rule "Board_0-Clearance: track to PTH hole perimeter"
	(condition "A.isPlated() && B.Type == 'track' && A.Net != B.Net")
	(constraint hole_clearance (min 0.33mm))
)

# TODO: try combining with rule "Clearance: PTH to track, different nets"
(rule "Board_0-Clearance: track to pad"
	(condition "A.Type == 'pad' && B.Type == 'track' &&  A.Net != B.Net")
	(constraint clearance (min 0.2mm))
)

(rule "Board_0-Clearance: pad/via to pad/via"
	(layer outer)
#	(condition "(A.Type == 'Pad' || A.Type == 'Via') && (B.Type == 'Pad' || B.Type == 'Via') && A.Net != B.Net")	
	(condition "A.isPlated() && B.isPlated() && A.Net != B.Net")
	(constraint clearance (min 0.2mm))
)
(rule "Board_1-Track width, outer layer (1oz copper)"
	(layer outer)
	(condition "A.Type == 'track'")
	(constraint track_width (min 0.127mm))
)

(rule "Board_1-Track spacing, outer layer (1oz copper)"
	(layer outer)
	(condition "A.Type == 'track' && B.Type == A.Type")
	(constraint clearance (min 0.127mm))
)

(rule "Board_1-Track width, inner layer"
	(layer inner)
	(condition "A.Type == 'track'")
	(constraint track_width (min 0.09mm))
)

(rule "Board_1-Track spacing, inner layer"
	(layer inner)
	(condition "A.Type == 'track' && B.Type == A.Type")
	(constraint clearance (min 0.09mm))
)

(rule "Board_1-Silkscreen text"
	(layer "?.Silkscreen")
	(condition "A.Type == 'Text' || A.Type == 'Text Box'")
	(constraint text_thickness (min 0.15mm))
	(constraint text_height (min 1mm))
)

(rule "Board_1-Pad to Silkscreen"
	(layer outer)
	(condition "A.Type == 'pad' && B.Layer == '?.Silkscreen'")
	(constraint silk_clearance (min 0.15mm))
)

(rule "Board_1-Edge (routed) to track clearance"
	(condition "A.Type == 'track'")
	(constraint edge_clearance (min 0.3mm))
)

#(rule "Edge (v-cut) to track clearance"
#	(condition "A.Type == 'track'")
#	(constraint edge_clearance (min 0.4mm))
#)

# JLCPCB restrictions ambiguous:
# Illustration: 0.2 mm, 1&2 layer: 0.3 mm, multilayer: "(0.15mm more costly)"
# This rule handles diameter minimum and maximum for ALL holes.
# Other specialized rules handle restrictions (e.g. Via, PTH, NPTH) 
(rule "Board_1-Hole diameter"
	(constraint hole_size (min 0.3mm) (max 6.3mm))
)

(rule "Board_1-Hole (NPTH) diameter"
	(layer outer)
	(condition "!A.isPlated()")
	(constraint hole_size (min 0.5mm))
)

# TODO: Hole to board edge ≥ 1 mm. Min. board size 10 × 10 mm
(rule "Board_1-Hole (castellated) diameter"
	(layer outer)
	(condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'")
	(constraint hole_size (min 0.6mm))
)

# JLCPCB: "Via diameter should be 0.1mm(0.15mm preferred) larger than Via hole size" (illustration shows diameters for both dimensions)
# JLCPCB: PTH: "The annular ring size will be enlarged to 0.15mm in production."
(rule "Board_1-Annular ring width (via and PTH)"
	(layer outer)
	(condition "A.isPlated()")
	(constraint annular_width (min 0.075mm))
)

(rule "Board_1-Clearance: hole to hole (perimeter), different nets"
	(layer outer)
	(condition "A.Net != B.Net && (A.Type != 'Via' || B.Type != 'Via')")
	(constraint hole_to_hole (min 0.5mm))
)

(rule "Board_1-Clearance: via to via (perimeter), different nets"
	(layer outer)
	(condition "A.Net != B.Net && A.Type == 'Via' && B.Type == 'Via'")
	(constraint hole_to_hole (min 0.2mm))
)

(rule "Board_1-Clearance: hole to hole (perimeter), same net"
	(layer outer)
	(condition "A.Net == B.Net")
	(constraint hole_to_hole (min 0.254mm))
)

(rule "Board_1-Clearance: track to NPTH hole (perimeter)"
#	(condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track' && A.Net != B.Net")
	(condition "!A.isPlated() && B.Type == 'track' && A.Net != B.Net")
	(constraint hole_clearance (min 0.254mm))
)

(rule "Board_1-Clearance: track to PTH hole perimeter"
	(condition "A.isPlated() && B.Type == 'track' && A.Net != B.Net")
	(constraint hole_clearance (min 0.33mm))
)

# TODO: try combining with rule "Clearance: PTH to track, different nets"
(rule "Board_1-Clearance: track to pad"
	(condition "A.Type == 'pad' && B.Type == 'track' &&  A.Net != B.Net")
	(constraint clearance (min 0.2mm))
)

(rule "Board_1-Clearance: pad/via to pad/via"
	(layer outer)
#	(condition "(A.Type == 'Pad' || A.Type == 'Via') && (B.Type == 'Pad' || B.Type == 'Via') && A.Net != B.Net")	
	(condition "A.isPlated() && B.isPlated() && A.Net != B.Net")
	(constraint clearance (min 0.2mm))
)
(rule "Board_2-Track width, outer layer (1oz copper)"
	(layer outer)
	(condition "A.Type == 'track'")
	(constraint track_width (min 0.127mm))
)

(rule "Board_2-Track spacing, outer layer (1oz copper)"
	(layer outer)
	(condition "A.Type == 'track' && B.Type == A.Type")
	(constraint clearance (min 0.127mm))
)

(rule "Board_2-Track width, inner layer"
	(layer inner)
	(condition "A.Type == 'track'")
	(constraint track_width (min 0.09mm))
)

(rule "Board_2-Track spacing, inner layer"
	(layer inner)
	(condition "A.Type == 'track' && B.Type == A.Type")
	(constraint clearance (min 0.09mm))
)

(rule "Board_2-Silkscreen text"
	(layer "?.Silkscreen")
	(condition "A.Type == 'Text' || A.Type == 'Text Box'")
	(constraint text_thickness (min 0.15mm))
	(constraint text_height (min 1mm))
)

(rule "Board_2-Pad to Silkscreen"
	(layer outer)
	(condition "A.Type == 'pad' && B.Layer == '?.Silkscreen'")
	(constraint silk_clearance (min 0.15mm))
)

(rule "Board_2-Edge (routed) to track clearance"
	(condition "A.Type == 'track'")
	(constraint edge_clearance (min 0.3mm))
)

#(rule "Edge (v-cut) to track clearance"
#	(condition "A.Type == 'track'")
#	(constraint edge_clearance (min 0.4mm))
#)

# JLCPCB restrictions ambiguous:
# Illustration: 0.2 mm, 1&2 layer: 0.3 mm, multilayer: "(0.15mm more costly)"
# This rule handles diameter minimum and maximum for ALL holes.
# Other specialized rules handle restrictions (e.g. Via, PTH, NPTH) 
(rule "Board_2-Hole diameter"
	(constraint hole_size (min 0.3mm) (max 6.3mm))
)

(rule "Board_2-Hole (NPTH) diameter"
	(layer outer)
	(condition "!A.isPlated()")
	(constraint hole_size (min 0.5mm))
)

# TODO: Hole to board edge ≥ 1 mm. Min. board size 10 × 10 mm
(rule "Board_2-Hole (castellated) diameter"
	(layer outer)
	(condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'")
	(constraint hole_size (min 0.6mm))
)

# JLCPCB: "Via diameter should be 0.1mm(0.15mm preferred) larger than Via hole size" (illustration shows diameters for both dimensions)
# JLCPCB: PTH: "The annular ring size will be enlarged to 0.15mm in production."
(rule "Board_2-Annular ring width (via and PTH)"
	(layer outer)
	(condition "A.isPlated()")
	(constraint annular_width (min 0.075mm))
)

(rule "Board_2-Clearance: hole to hole (perimeter), different nets"
	(layer outer)
	(condition "A.Net != B.Net && (A.Type != 'Via' || B.Type != 'Via')")
	(constraint hole_to_hole (min 0.5mm))
)

(rule "Board_2-Clearance: via to via (perimeter), different nets"
	(layer outer)
	(condition "A.Net != B.Net && A.Type == 'Via' && B.Type == 'Via'")
	(constraint hole_to_hole (min 0.2mm))
)

(rule "Board_2-Clearance: hole to hole (perimeter), same net"
	(layer outer)
	(condition "A.Net == B.Net")
	(constraint hole_to_hole (min 0.254mm))
)

(rule "Board_2-Clearance: track to NPTH hole (perimeter)"
#	(condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track' && A.Net != B.Net")
	(condition "!A.isPlated() && B.Type == 'track' && A.Net != B.Net")
	(constraint hole_clearance (min 0.254mm))
)

(rule "Board_2-Clearance: track to PTH hole perimeter"
	(condition "A.isPlated() && B.Type == 'track' && A.Net != B.Net")
	(constraint hole_clearance (min 0.33mm))
)

# TODO: try combining with rule "Clearance: PTH to track, different nets"
(rule "Board_2-Clearance: track to pad"
	(condition "A.Type == 'pad' && B.Type == 'track' &&  A.Net != B.Net")
	(constraint clearance (min 0.2mm))
)

(rule "Board_2-Clearance: pad/via to pad/via"
	(layer outer)
#	(condition "(A.Type == 'Pad' || A.Type == 'Via') && (B.Type == 'Pad' || B.Type == 'Via') && A.Net != B.Net")	
	(condition "A.isPlated() && B.isPlated() && A.Net != B.Net")
	(constraint clearance (min 0.2mm))
)
(rule "Board_3-Track width, outer layer (1oz copper)"
	(layer outer)
	(condition "A.Type == 'track'")
	(constraint track_width (min 0.127mm))
)

(rule "Board_3-Track spacing, outer layer (1oz copper)"
	(layer outer)
	(condition "A.Type == 'track' && B.Type == A.Type")
	(constraint clearance (min 0.127mm))
)

(rule "Board_3-Track width, inner layer"
	(layer inner)
	(condition "A.Type == 'track'")
	(constraint track_width (min 0.09mm))
)

(rule "Board_3-Track spacing, inner layer"
	(layer inner)
	(condition "A.Type == 'track' && B.Type == A.Type")
	(constraint clearance (min 0.09mm))
)

(rule "Board_3-Silkscreen text"
	(layer "?.Silkscreen")
	(condition "A.Type == 'Text' || A.Type == 'Text Box'")
	(constraint text_thickness (min 0.15mm))
	(constraint text_height (min 1mm))
)

(rule "Board_3-Pad to Silkscreen"
	(layer outer)
	(condition "A.Type == 'pad' && B.Layer == '?.Silkscreen'")
	(constraint silk_clearance (min 0.15mm))
)

(rule "Board_3-Edge (routed) to track clearance"
	(condition "A.Type == 'track'")
	(constraint edge_clearance (min 0.3mm))
)

#(rule "Edge (v-cut) to track clearance"
#	(condition "A.Type == 'track'")
#	(constraint edge_clearance (min 0.4mm))
#)

# JLCPCB restrictions ambiguous:
# Illustration: 0.2 mm, 1&2 layer: 0.3 mm, multilayer: "(0.15mm more costly)"
# This rule handles diameter minimum and maximum for ALL holes.
# Other specialized rules handle restrictions (e.g. Via, PTH, NPTH) 
(rule "Board_3-Hole diameter"
	(constraint hole_size (min 0.3mm) (max 6.3mm))
)

(rule "Board_3-Hole (NPTH) diameter"
	(layer outer)
	(condition "!A.isPlated()")
	(constraint hole_size (min 0.5mm))
)

# TODO: Hole to board edge ≥ 1 mm. Min. board size 10 × 10 mm
(rule "Board_3-Hole (castellated) diameter"
	(layer outer)
	(condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'")
	(constraint hole_size (min 0.6mm))
)

# JLCPCB: "Via diameter should be 0.1mm(0.15mm preferred) larger than Via hole size" (illustration shows diameters for both dimensions)
# JLCPCB: PTH: "The annular ring size will be enlarged to 0.15mm in production."
(rule "Board_3-Annular ring width (via and PTH)"
	(layer outer)
	(condition "A.isPlated()")
	(constraint annular_width (min 0.075mm))
)

(rule "Board_3-Clearance: hole to hole (perimeter), different nets"
	(layer outer)
	(condition "A.Net != B.Net && (A.Type != 'Via' || B.Type != 'Via')")
	(constraint hole_to_hole (min 0.5mm))
)

(rule "Board_3-Clearance: via to via (perimeter), different nets"
	(layer outer)
	(condition "A.Net != B.Net && A.Type == 'Via' && B.Type == 'Via'")
	(constraint hole_to_hole (min 0.2mm))
)

(rule "Board_3-Clearance: hole to hole (perimeter), same net"
	(layer outer)
	(condition "A.Net == B.Net")
	(constraint hole_to_hole (min 0.254mm))
)

(rule "Board_3-Clearance: track to NPTH hole (perimeter)"
#	(condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track' && A.Net != B.Net")
	(condition "!A.isPlated() && B.Type == 'track' && A.Net != B.Net")
	(constraint hole_clearance (min 0.254mm))
)

(rule "Board_3-Clearance: track to PTH hole perimeter"
	(condition "A.isPlated() && B.Type == 'track' && A.Net != B.Net")
	(constraint hole_clearance (min 0.33mm))
)

# TODO: try combining with rule "Clearance: PTH to track, different nets"
(rule "Board_3-Clearance: track to pad"
	(condition "A.Type == 'pad' && B.Type == 'track' &&  A.Net != B.Net")
	(constraint clearance (min 0.2mm))
)

(rule "Board_3-Clearance: pad/via to pad/via"
	(layer outer)
#	(condition "(A.Type == 'Pad' || A.Type == 'Via') && (B.Type == 'Pad' || B.Type == 'Via') && A.Net != B.Net")	
	(condition "A.isPlated() && B.isPlated() && A.Net != B.Net")
	(constraint clearance (min 0.2mm))
)
(rule "Board_4-Track width, outer layer (1oz copper)"
	(layer outer)
	(condition "A.Type == 'track'")
	(constraint track_width (min 0.127mm))
)

(rule "Board_4-Track spacing, outer layer (1oz copper)"
	(layer outer)
	(condition "A.Type == 'track' && B.Type == A.Type")
	(constraint clearance (min 0.127mm))
)

(rule "Board_4-Track width, inner layer"
	(layer inner)
	(condition "A.Type == 'track'")
	(constraint track_width (min 0.09mm))
)

(rule "Board_4-Track spacing, inner layer"
	(layer inner)
	(condition "A.Type == 'track' && B.Type == A.Type")
	(constraint clearance (min 0.09mm))
)

(rule "Board_4-Silkscreen text"
	(layer "?.Silkscreen")
	(condition "A.Type == 'Text' || A.Type == 'Text Box'")
	(constraint text_thickness (min 0.15mm))
	(constraint text_height (min 1mm))
)

(rule "Board_4-Pad to Silkscreen"
	(layer outer)
	(condition "A.Type == 'pad' && B.Layer == '?.Silkscreen'")
	(constraint silk_clearance (min 0.15mm))
)

(rule "Board_4-Edge (routed) to track clearance"
	(condition "A.Type == 'track'")
	(constraint edge_clearance (min 0.3mm))
)

#(rule "Edge (v-cut) to track clearance"
#	(condition "A.Type == 'track'")
#	(constraint edge_clearance (min 0.4mm))
#)

# JLCPCB restrictions ambiguous:
# Illustration: 0.2 mm, 1&2 layer: 0.3 mm, multilayer: "(0.15mm more costly)"
# This rule handles diameter minimum and maximum for ALL holes.
# Other specialized rules handle restrictions (e.g. Via, PTH, NPTH) 
(rule "Board_4-Hole diameter"
	(constraint hole_size (min 0.3mm) (max 6.3mm))
)

(rule "Board_4-Hole (NPTH) diameter"
	(layer outer)
	(condition "!A.isPlated()")
	(constraint hole_size (min 0.5mm))
)

# TODO: Hole to board edge ≥ 1 mm. Min. board size 10 × 10 mm
(rule "Board_4-Hole (castellated) diameter"
	(layer outer)
	(condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'")
	(constraint hole_size (min 0.6mm))
)

# JLCPCB: "Via diameter should be 0.1mm(0.15mm preferred) larger than Via hole size" (illustration shows diameters for both dimensions)
# JLCPCB: PTH: "The annular ring size will be enlarged to 0.15mm in production."
(rule "Board_4-Annular ring width (via and PTH)"
	(layer outer)
	(condition "A.isPlated()")
	(constraint annular_width (min 0.075mm))
)

(rule "Board_4-Clearance: hole to hole (perimeter), different nets"
	(layer outer)
	(condition "A.Net != B.Net && (A.Type != 'Via' || B.Type != 'Via')")
	(constraint hole_to_hole (min 0.5mm))
)

(rule "Board_4-Clearance: via to via (perimeter), different nets"
	(layer outer)
	(condition "A.Net != B.Net && A.Type == 'Via' && B.Type == 'Via'")
	(constraint hole_to_hole (min 0.2mm))
)

(rule "Board_4-Clearance: hole to hole (perimeter), same net"
	(layer outer)
	(condition "A.Net == B.Net")
	(constraint hole_to_hole (min 0.254mm))
)

(rule "Board_4-Clearance: track to NPTH hole (perimeter)"
#	(condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track' && A.Net != B.Net")
	(condition "!A.isPlated() && B.Type == 'track' && A.Net != B.Net")
	(constraint hole_clearance (min 0.254mm))
)

(rule "Board_4-Clearance: track to PTH hole perimeter"
	(condition "A.isPlated() && B.Type == 'track' && A.Net != B.Net")
	(constraint hole_clearance (min 0.33mm))
)

# TODO: try combining with rule "Clearance: PTH to track, different nets"
(rule "Board_4-Clearance: track to pad"
	(condition "A.Type == 'pad' && B.Type == 'track' &&  A.Net != B.Net")
	(constraint clearance (min 0.2mm))
)

(rule "Board_4-Clearance: pad/via to pad/via"
	(layer outer)
#	(condition "(A.Type == 'Pad' || A.Type == 'Via') && (B.Type == 'Pad' || B.Type == 'Via') && A.Net != B.Net")	
	(condition "A.isPlated() && B.isPlated() && A.Net != B.Net")
	(constraint clearance (min 0.2mm))
)
(rule "Board_5-Track width, outer layer (1oz copper)"
	(layer outer)
	(condition "A.Type == 'track'")
	(constraint track_width (min 0.127mm))
)

(rule "Board_5-Track spacing, outer layer (1oz copper)"
	(layer outer)
	(condition "A.Type == 'track' && B.Type == A.Type")
	(constraint clearance (min 0.127mm))
)

(rule "Board_5-Track width, inner layer"
	(layer inner)
	(condition "A.Type == 'track'")
	(constraint track_width (min 0.09mm))
)

(rule "Board_5-Track spacing, inner layer"
	(layer inner)
	(condition "A.Type == 'track' && B.Type == A.Type")
	(constraint clearance (min 0.09mm))
)

(rule "Board_5-Silkscreen text"
	(layer "?.Silkscreen")
	(condition "A.Type == 'Text' || A.Type == 'Text Box'")
	(constraint text_thickness (min 0.15mm))
	(constraint text_height (min 1mm))
)

(rule "Board_5-Pad to Silkscreen"
	(layer outer)
	(condition "A.Type == 'pad' && B.Layer == '?.Silkscreen'")
	(constraint silk_clearance (min 0.15mm))
)

(rule "Board_5-Edge (routed) to track clearance"
	(condition "A.Type == 'track'")
	(constraint edge_clearance (min 0.3mm))
)

#(rule "Edge (v-cut) to track clearance"
#	(condition "A.Type == 'track'")
#	(constraint edge_clearance (min 0.4mm))
#)

# JLCPCB restrictions ambiguous:
# Illustration: 0.2 mm, 1&2 layer: 0.3 mm, multilayer: "(0.15mm more costly)"
# This rule handles diameter minimum and maximum for ALL holes.
# Other specialized rules handle restrictions (e.g. Via, PTH, NPTH) 
(rule "Board_5-Hole diameter"
	(constraint hole_size (min 0.3mm) (max 6.3mm))
)

(rule "Board_5-Hole (NPTH) diameter"
	(layer outer)
	(condition "!A.isPlated()")
	(constraint hole_size (min 0.5mm))
)

# TODO: Hole to board edge ≥ 1 mm. Min. board size 10 × 10 mm
(rule "Board_5-Hole (castellated) diameter"
	(layer outer)
	(condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'")
	(constraint hole_size (min 0.6mm))
)

# JLCPCB: "Via diameter should be 0.1mm(0.15mm preferred) larger than Via hole size" (illustration shows diameters for both dimensions)
# JLCPCB: PTH: "The annular ring size will be enlarged to 0.15mm in production."
(rule "Board_5-Annular ring width (via and PTH)"
	(layer outer)
	(condition "A.isPlated()")
	(constraint annular_width (min 0.075mm))
)

(rule "Board_5-Clearance: hole to hole (perimeter), different nets"
	(layer outer)
	(condition "A.Net != B.Net && (A.Type != 'Via' || B.Type != 'Via')")
	(constraint hole_to_hole (min 0.5mm))
)

(rule "Board_5-Clearance: via to via (perimeter), different nets"
	(layer outer)
	(condition "A.Net != B.Net && A.Type == 'Via' && B.Type == 'Via'")
	(constraint hole_to_hole (min 0.2mm))
)

(rule "Board_5-Clearance: hole to hole (perimeter), same net"
	(layer outer)
	(condition "A.Net == B.Net")
	(constraint hole_to_hole (min 0.254mm))
)

(rule "Board_5-Clearance: track to NPTH hole (perimeter)"
#	(condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track' && A.Net != B.Net")
	(condition "!A.isPlated() && B.Type == 'track' && A.Net != B.Net")
	(constraint hole_clearance (min 0.254mm))
)

(rule "Board_5-Clearance: track to PTH hole perimeter"
	(condition "A.isPlated() && B.Type == 'track' && A.Net != B.Net")
	(constraint hole_clearance (min 0.33mm))
)

# TODO: try combining with rule "Clearance: PTH to track, different nets"
(rule "Board_5-Clearance: track to pad"
	(condition "A.Type == 'pad' && B.Type == 'track' &&  A.Net != B.Net")
	(constraint clearance (min 0.2mm))
)

(rule "Board_5-Clearance: pad/via to pad/via"
	(layer outer)
#	(condition "(A.Type == 'Pad' || A.Type == 'Via') && (B.Type == 'Pad' || B.Type == 'Via') && A.Net != B.Net")	
	(condition "A.isPlated() && B.isPlated() && A.Net != B.Net")
	(constraint clearance (min 0.2mm))
)
(rule "Board_6-Track width, outer layer (1oz copper)"
	(layer outer)
	(condition "A.Type == 'track'")
	(constraint track_width (min 0.127mm))
)

(rule "Board_6-Track spacing, outer layer (1oz copper)"
	(layer outer)
	(condition "A.Type == 'track' && B.Type == A.Type")
	(constraint clearance (min 0.127mm))
)

(rule "Board_6-Track width, inner layer"
	(layer inner)
	(condition "A.Type == 'track'")
	(constraint track_width (min 0.09mm))
)

(rule "Board_6-Track spacing, inner layer"
	(layer inner)
	(condition "A.Type == 'track' && B.Type == A.Type")
	(constraint clearance (min 0.09mm))
)

(rule "Board_6-Silkscreen text"
	(layer "?.Silkscreen")
	(condition "A.Type == 'Text' || A.Type == 'Text Box'")
	(constraint text_thickness (min 0.15mm))
	(constraint text_height (min 1mm))
)

(rule "Board_6-Pad to Silkscreen"
	(layer outer)
	(condition "A.Type == 'pad' && B.Layer == '?.Silkscreen'")
	(constraint silk_clearance (min 0.15mm))
)

(rule "Board_6-Edge (routed) to track clearance"
	(condition "A.Type == 'track'")
	(constraint edge_clearance (min 0.3mm))
)

#(rule "Edge (v-cut) to track clearance"
#	(condition "A.Type == 'track'")
#	(constraint edge_clearance (min 0.4mm))
#)

# JLCPCB restrictions ambiguous:
# Illustration: 0.2 mm, 1&2 layer: 0.3 mm, multilayer: "(0.15mm more costly)"
# This rule handles diameter minimum and maximum for ALL holes.
# Other specialized rules handle restrictions (e.g. Via, PTH, NPTH) 
(rule "Board_6-Hole diameter"
	(constraint hole_size (min 0.3mm) (max 6.3mm))
)

(rule "Board_6-Hole (NPTH) diameter"
	(layer outer)
	(condition "!A.isPlated()")
	(constraint hole_size (min 0.5mm))
)

# TODO: Hole to board edge ≥ 1 mm. Min. board size 10 × 10 mm
(rule "Board_6-Hole (castellated) diameter"
	(layer outer)
	(condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'")
	(constraint hole_size (min 0.6mm))
)

# JLCPCB: "Via diameter should be 0.1mm(0.15mm preferred) larger than Via hole size" (illustration shows diameters for both dimensions)
# JLCPCB: PTH: "The annular ring size will be enlarged to 0.15mm in production."
(rule "Board_6-Annular ring width (via and PTH)"
	(layer outer)
	(condition "A.isPlated()")
	(constraint annular_width (min 0.075mm))
)

(rule "Board_6-Clearance: hole to hole (perimeter), different nets"
	(layer outer)
	(condition "A.Net != B.Net && (A.Type != 'Via' || B.Type != 'Via')")
	(constraint hole_to_hole (min 0.5mm))
)

(rule "Board_6-Clearance: via to via (perimeter), different nets"
	(layer outer)
	(condition "A.Net != B.Net && A.Type == 'Via' && B.Type == 'Via'")
	(constraint hole_to_hole (min 0.2mm))
)

(rule "Board_6-Clearance: hole to hole (perimeter), same net"
	(layer outer)
	(condition "A.Net == B.Net")
	(constraint hole_to_hole (min 0.254mm))
)

(rule "Board_6-Clearance: track to NPTH hole (perimeter)"
#	(condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track' && A.Net != B.Net")
	(condition "!A.isPlated() && B.Type == 'track' && A.Net != B.Net")
	(constraint hole_clearance (min 0.254mm))
)

(rule "Board_6-Clearance: track to PTH hole perimeter"
	(condition "A.isPlated() && B.Type == 'track' && A.Net != B.Net")
	(constraint hole_clearance (min 0.33mm))
)

# TODO: try combining with rule "Clearance: PTH to track, different nets"
(rule "Board_6-Clearance: track to pad"
	(condition "A.Type == 'pad' && B.Type == 'track' &&  A.Net != B.Net")
	(constraint clearance (min 0.2mm))
)

(rule "Board_6-Clearance: pad/via to pad/via"
	(layer outer)
#	(condition "(A.Type == 'Pad' || A.Type == 'Via') && (B.Type == 'Pad' || B.Type == 'Via') && A.Net != B.Net")	
	(condition "A.isPlated() && B.isPlated() && A.Net != B.Net")
	(constraint clearance (min 0.2mm))
)
(rule "Board_7-Track width, outer layer (1oz copper)"
	(layer outer)
	(condition "A.Type == 'track'")
	(constraint track_width (min 0.127mm))
)

(rule "Board_7-Track spacing, outer layer (1oz copper)"
	(layer outer)
	(condition "A.Type == 'track' && B.Type == A.Type")
	(constraint clearance (min 0.127mm))
)

(rule "Board_7-Track width, inner layer"
	(layer inner)
	(condition "A.Type == 'track'")
	(constraint track_width (min 0.09mm))
)

(rule "Board_7-Track spacing, inner layer"
	(layer inner)
	(condition "A.Type == 'track' && B.Type == A.Type")
	(constraint clearance (min 0.09mm))
)

(rule "Board_7-Silkscreen text"
	(layer "?.Silkscreen")
	(condition "A.Type == 'Text' || A.Type == 'Text Box'")
	(constraint text_thickness (min 0.15mm))
	(constraint text_height (min 1mm))
)

(rule "Board_7-Pad to Silkscreen"
	(layer outer)
	(condition "A.Type == 'pad' && B.Layer == '?.Silkscreen'")
	(constraint silk_clearance (min 0.15mm))
)

(rule "Board_7-Edge (routed) to track clearance"
	(condition "A.Type == 'track'")
	(constraint edge_clearance (min 0.3mm))
)

#(rule "Edge (v-cut) to track clearance"
#	(condition "A.Type == 'track'")
#	(constraint edge_clearance (min 0.4mm))
#)

# JLCPCB restrictions ambiguous:
# Illustration: 0.2 mm, 1&2 layer: 0.3 mm, multilayer: "(0.15mm more costly)"
# This rule handles diameter minimum and maximum for ALL holes.
# Other specialized rules handle restrictions (e.g. Via, PTH, NPTH) 
(rule "Board_7-Hole diameter"
	(constraint hole_size (min 0.3mm) (max 6.3mm))
)

(rule "Board_7-Hole (NPTH) diameter"
	(layer outer)
	(condition "!A.isPlated()")
	(constraint hole_size (min 0.5mm))
)

# TODO: Hole to board edge ≥ 1 mm. Min. board size 10 × 10 mm
(rule "Board_7-Hole (castellated) diameter"
	(layer outer)
	(condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'")
	(constraint hole_size (min 0.6mm))
)

# JLCPCB: "Via diameter should be 0.1mm(0.15mm preferred) larger than Via hole size" (illustration shows diameters for both dimensions)
# JLCPCB: PTH: "The annular ring size will be enlarged to 0.15mm in production."
(rule "Board_7-Annular ring width (via and PTH)"
	(layer outer)
	(condition "A.isPlated()")
	(constraint annular_width (min 0.075mm))
)

(rule "Board_7-Clearance: hole to hole (perimeter), different nets"
	(layer outer)
	(condition "A.Net != B.Net && (A.Type != 'Via' || B.Type != 'Via')")
	(constraint hole_to_hole (min 0.5mm))
)

(rule "Board_7-Clearance: via to via (perimeter), different nets"
	(layer outer)
	(condition "A.Net != B.Net && A.Type == 'Via' && B.Type == 'Via'")
	(constraint hole_to_hole (min 0.2mm))
)

(rule "Board_7-Clearance: hole to hole (perimeter), same net"
	(layer outer)
	(condition "A.Net == B.Net")
	(constraint hole_to_hole (min 0.254mm))
)

(rule "Board_7-Clearance: track to NPTH hole (perimeter)"
#	(condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track' && A.Net != B.Net")
	(condition "!A.isPlated() && B.Type == 'track' && A.Net != B.Net")
	(constraint hole_clearance (min 0.254mm))
)

(rule "Board_7-Clearance: track to PTH hole perimeter"
	(condition "A.isPlated() && B.Type == 'track' && A.Net != B.Net")
	(constraint hole_clearance (min 0.33mm))
)

# TODO: try combining with rule "Clearance: PTH to track, different nets"
(rule "Board_7-Clearance: track to pad"
	(condition "A.Type == 'pad' && B.Type == 'track' &&  A.Net != B.Net")
	(constraint clearance (min 0.2mm))
)

(rule "Board_7-Clearance: pad/via to pad/via"
	(layer outer)
#	(condition "(A.Type == 'Pad' || A.Type == 'Via') && (B.Type == 'Pad' || B.Type == 'Via') && A.Net != B.Net")	
	(condition "A.isPlated() && B.isPlated() && A.Net != B.Net")
	(constraint clearance (min 0.2mm))
)
(rule "Board_8-Track width, outer layer (1oz copper)"
	(layer outer)
	(condition "A.Type == 'track'")
	(constraint track_width (min 0.127mm))
)

(rule "Board_8-Track spacing, outer layer (1oz copper)"
	(layer outer)
	(condition "A.Type == 'track' && B.Type == A.Type")
	(constraint clearance (min 0.127mm))
)

(rule "Board_8-Track width, inner layer"
	(layer inner)
	(condition "A.Type == 'track'")
	(constraint track_width (min 0.09mm))
)

(rule "Board_8-Track spacing, inner layer"
	(layer inner)
	(condition "A.Type == 'track' && B.Type == A.Type")
	(constraint clearance (min 0.09mm))
)

(rule "Board_8-Silkscreen text"
	(layer "?.Silkscreen")
	(condition "A.Type == 'Text' || A.Type == 'Text Box'")
	(constraint text_thickness (min 0.15mm))
	(constraint text_height (min 1mm))
)

(rule "Board_8-Pad to Silkscreen"
	(layer outer)
	(condition "A.Type == 'pad' && B.Layer == '?.Silkscreen'")
	(constraint silk_clearance (min 0.15mm))
)

(rule "Board_8-Edge (routed) to track clearance"
	(condition "A.Type == 'track'")
	(constraint edge_clearance (min 0.3mm))
)

#(rule "Edge (v-cut) to track clearance"
#	(condition "A.Type == 'track'")
#	(constraint edge_clearance (min 0.4mm))
#)

# JLCPCB restrictions ambiguous:
# Illustration: 0.2 mm, 1&2 layer: 0.3 mm, multilayer: "(0.15mm more costly)"
# This rule handles diameter minimum and maximum for ALL holes.
# Other specialized rules handle restrictions (e.g. Via, PTH, NPTH) 
(rule "Board_8-Hole diameter"
	(constraint hole_size (min 0.3mm) (max 6.3mm))
)

(rule "Board_8-Hole (NPTH) diameter"
	(layer outer)
	(condition "!A.isPlated()")
	(constraint hole_size (min 0.5mm))
)

# TODO: Hole to board edge ≥ 1 mm. Min. board size 10 × 10 mm
(rule "Board_8-Hole (castellated) diameter"
	(layer outer)
	(condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'")
	(constraint hole_size (min 0.6mm))
)

# JLCPCB: "Via diameter should be 0.1mm(0.15mm preferred) larger than Via hole size" (illustration shows diameters for both dimensions)
# JLCPCB: PTH: "The annular ring size will be enlarged to 0.15mm in production."
(rule "Board_8-Annular ring width (via and PTH)"
	(layer outer)
	(condition "A.isPlated()")
	(constraint annular_width (min 0.075mm))
)

(rule "Board_8-Clearance: hole to hole (perimeter), different nets"
	(layer outer)
	(condition "A.Net != B.Net && (A.Type != 'Via' || B.Type != 'Via')")
	(constraint hole_to_hole (min 0.5mm))
)

(rule "Board_8-Clearance: via to via (perimeter), different nets"
	(layer outer)
	(condition "A.Net != B.Net && A.Type == 'Via' && B.Type == 'Via'")
	(constraint hole_to_hole (min 0.2mm))
)

(rule "Board_8-Clearance: hole to hole (perimeter), same net"
	(layer outer)
	(condition "A.Net == B.Net")
	(constraint hole_to_hole (min 0.254mm))
)

(rule "Board_8-Clearance: track to NPTH hole (perimeter)"
#	(condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track' && A.Net != B.Net")
	(condition "!A.isPlated() && B.Type == 'track' && A.Net != B.Net")
	(constraint hole_clearance (min 0.254mm))
)

(rule "Board_8-Clearance: track to PTH hole perimeter"
	(condition "A.isPlated() && B.Type == 'track' && A.Net != B.Net")
	(constraint hole_clearance (min 0.33mm))
)

# TODO: try combining with rule "Clearance: PTH to track, different nets"
(rule "Board_8-Clearance: track to pad"
	(condition "A.Type == 'pad' && B.Type == 'track' &&  A.Net != B.Net")
	(constraint clearance (min 0.2mm))
)

(rule "Board_8-Clearance: pad/via to pad/via"
	(layer outer)
#	(condition "(A.Type == 'Pad' || A.Type == 'Via') && (B.Type == 'Pad' || B.Type == 'Via') && A.Net != B.Net")	
	(condition "A.isPlated() && B.isPlated() && A.Net != B.Net")
	(constraint clearance (min 0.2mm))
)
(rule "Board_9-Track width, outer layer (1oz copper)"
	(layer outer)
	(condition "A.Type == 'track'")
	(constraint track_width (min 0.127mm))
)

(rule "Board_9-Track spacing, outer layer (1oz copper)"
	(layer outer)
	(condition "A.Type == 'track' && B.Type == A.Type")
	(constraint clearance (min 0.127mm))
)

(rule "Board_9-Track width, inner layer"
	(layer inner)
	(condition "A.Type == 'track'")
	(constraint track_width (min 0.09mm))
)

(rule "Board_9-Track spacing, inner layer"
	(layer inner)
	(condition "A.Type == 'track' && B.Type == A.Type")
	(constraint clearance (min 0.09mm))
)

(rule "Board_9-Silkscreen text"
	(layer "?.Silkscreen")
	(condition "A.Type == 'Text' || A.Type == 'Text Box'")
	(constraint text_thickness (min 0.15mm))
	(constraint text_height (min 1mm))
)

(rule "Board_9-Pad to Silkscreen"
	(layer outer)
	(condition "A.Type == 'pad' && B.Layer == '?.Silkscreen'")
	(constraint silk_clearance (min 0.15mm))
)

(rule "Board_9-Edge (routed) to track clearance"
	(condition "A.Type == 'track'")
	(constraint edge_clearance (min 0.3mm))
)

#(rule "Edge (v-cut) to track clearance"
#	(condition "A.Type == 'track'")
#	(constraint edge_clearance (min 0.4mm))
#)

# JLCPCB restrictions ambiguous:
# Illustration: 0.2 mm, 1&2 layer: 0.3 mm, multilayer: "(0.15mm more costly)"
# This rule handles diameter minimum and maximum for ALL holes.
# Other specialized rules handle restrictions (e.g. Via, PTH, NPTH) 
(rule "Board_9-Hole diameter"
	(constraint hole_size (min 0.3mm) (max 6.3mm))
)

(rule "Board_9-Hole (NPTH) diameter"
	(layer outer)
	(condition "!A.isPlated()")
	(constraint hole_size (min 0.5mm))
)

# TODO: Hole to board edge ≥ 1 mm. Min. board size 10 × 10 mm
(rule "Board_9-Hole (castellated) diameter"
	(layer outer)
	(condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'")
	(constraint hole_size (min 0.6mm))
)

# JLCPCB: "Via diameter should be 0.1mm(0.15mm preferred) larger than Via hole size" (illustration shows diameters for both dimensions)
# JLCPCB: PTH: "The annular ring size will be enlarged to 0.15mm in production."
(rule "Board_9-Annular ring width (via and PTH)"
	(layer outer)
	(condition "A.isPlated()")
	(constraint annular_width (min 0.075mm))
)

(rule "Board_9-Clearance: hole to hole (perimeter), different nets"
	(layer outer)
	(condition "A.Net != B.Net && (A.Type != 'Via' || B.Type != 'Via')")
	(constraint hole_to_hole (min 0.5mm))
)

(rule "Board_9-Clearance: via to via (perimeter), different nets"
	(layer outer)
	(condition "A.Net != B.Net && A.Type == 'Via' && B.Type == 'Via'")
	(constraint hole_to_hole (min 0.2mm))
)

(rule "Board_9-Clearance: hole to hole (perimeter), same net"
	(layer outer)
	(condition "A.Net == B.Net")
	(constraint hole_to_hole (min 0.254mm))
)

(rule "Board_9-Clearance: track to NPTH hole (perimeter)"
#	(condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track' && A.Net != B.Net")
	(condition "!A.isPlated() && B.Type == 'track' && A.Net != B.Net")
	(constraint hole_clearance (min 0.254mm))
)

(rule "Board_9-Clearance: track to PTH hole perimeter"
	(condition "A.isPlated() && B.Type == 'track' && A.Net != B.Net")
	(constraint hole_clearance (min 0.33mm))
)

# TODO: try combining with rule "Clearance: PTH to track, different nets"
(rule "Board_9-Clearance: track to pad"
	(condition "A.Type == 'pad' && B.Type == 'track' &&  A.Net != B.Net")
	(constraint clearance (min 0.2mm))
)

(rule "Board_9-Clearance: pad/via to pad/via"
	(layer outer)
#	(condition "(A.Type == 'Pad' || A.Type == 'Via') && (B.Type == 'Pad' || B.Type == 'Via') && A.Net != B.Net")	
	(condition "A.isPlated() && B.isPlated() && A.Net != B.Net")
	(constraint clearance (min 0.2mm))
)
(rule "Board_10-Track width, outer layer (1oz copper)"
	(layer outer)
	(condition "A.Type == 'track'")
	(constraint track_width (min 0.127mm))
)

(rule "Board_10-Track spacing, outer layer (1oz copper)"
	(layer outer)
	(condition "A.Type == 'track' && B.Type == A.Type")
	(constraint clearance (min 0.127mm))
)

(rule "Board_10-Track width, inner layer"
	(layer inner)
	(condition "A.Type == 'track'")
	(constraint track_width (min 0.09mm))
)

(rule "Board_10-Track spacing, inner layer"
	(layer inner)
	(condition "A.Type == 'track' && B.Type == A.Type")
	(constraint clearance (min 0.09mm))
)

(rule "Board_10-Silkscreen text"
	(layer "?.Silkscreen")
	(condition "A.Type == 'Text' || A.Type == 'Text Box'")
	(constraint text_thickness (min 0.15mm))
	(constraint text_height (min 1mm))
)

(rule "Board_10-Pad to Silkscreen"
	(layer outer)
	(condition "A.Type == 'pad' && B.Layer == '?.Silkscreen'")
	(constraint silk_clearance (min 0.15mm))
)

(rule "Board_10-Edge (routed) to track clearance"
	(condition "A.Type == 'track'")
	(constraint edge_clearance (min 0.3mm))
)

#(rule "Edge (v-cut) to track clearance"
#	(condition "A.Type == 'track'")
#	(constraint edge_clearance (min 0.4mm))
#)

# JLCPCB restrictions ambiguous:
# Illustration: 0.2 mm, 1&2 layer: 0.3 mm, multilayer: "(0.15mm more costly)"
# This rule handles diameter minimum and maximum for ALL holes.
# Other specialized rules handle restrictions (e.g. Via, PTH, NPTH) 
(rule "Board_10-Hole diameter"
	(constraint hole_size (min 0.3mm) (max 6.3mm))
)

(rule "Board_10-Hole (NPTH) diameter"
	(layer outer)
	(condition "!A.isPlated()")
	(constraint hole_size (min 0.5mm))
)

# TODO: Hole to board edge ≥ 1 mm. Min. board size 10 × 10 mm
(rule "Board_10-Hole (castellated) diameter"
	(layer outer)
	(condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'")
	(constraint hole_size (min 0.6mm))
)

# JLCPCB: "Via diameter should be 0.1mm(0.15mm preferred) larger than Via hole size" (illustration shows diameters for both dimensions)
# JLCPCB: PTH: "The annular ring size will be enlarged to 0.15mm in production."
(rule "Board_10-Annular ring width (via and PTH)"
	(layer outer)
	(condition "A.isPlated()")
	(constraint annular_width (min 0.075mm))
)

(rule "Board_10-Clearance: hole to hole (perimeter), different nets"
	(layer outer)
	(condition "A.Net != B.Net && (A.Type != 'Via' || B.Type != 'Via')")
	(constraint hole_to_hole (min 0.5mm))
)

(rule "Board_10-Clearance: via to via (perimeter), different nets"
	(layer outer)
	(condition "A.Net != B.Net && A.Type == 'Via' && B.Type == 'Via'")
	(constraint hole_to_hole (min 0.2mm))
)

(rule "Board_10-Clearance: hole to hole (perimeter), same net"
	(layer outer)
	(condition "A.Net == B.Net")
	(constraint hole_to_hole (min 0.254mm))
)

(rule "Board_10-Clearance: track to NPTH hole (perimeter)"
#	(condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track' && A.Net != B.Net")
	(condition "!A.isPlated() && B.Type == 'track' && A.Net != B.Net")
	(constraint hole_clearance (min 0.254mm))
)

(rule "Board_10-Clearance: track to PTH hole perimeter"
	(condition "A.isPlated() && B.Type == 'track' && A.Net != B.Net")
	(constraint hole_clearance (min 0.33mm))
)

# TODO: try combining with rule "Clearance: PTH to track, different nets"
(rule "Board_10-Clearance: track to pad"
	(condition "A.Type == 'pad' && B.Type == 'track' &&  A.Net != B.Net")
	(constraint clearance (min 0.2mm))
)

(rule "Board_10-Clearance: pad/via to pad/via"
	(layer outer)
#	(condition "(A.Type == 'Pad' || A.Type == 'Via') && (B.Type == 'Pad' || B.Type == 'Via') && A.Net != B.Net")	
	(condition "A.isPlated() && B.isPlated() && A.Net != B.Net")
	(constraint clearance (min 0.2mm))
)
(rule "Board_11-Track width, outer layer (1oz copper)"
	(layer outer)
	(condition "A.Type == 'track'")
	(constraint track_width (min 0.127mm))
)

(rule "Board_11-Track spacing, outer layer (1oz copper)"
	(layer outer)
	(condition "A.Type == 'track' && B.Type == A.Type")
	(constraint clearance (min 0.127mm))
)

(rule "Board_11-Track width, inner layer"
	(layer inner)
	(condition "A.Type == 'track'")
	(constraint track_width (min 0.09mm))
)

(rule "Board_11-Track spacing, inner layer"
	(layer inner)
	(condition "A.Type == 'track' && B.Type == A.Type")
	(constraint clearance (min 0.09mm))
)

(rule "Board_11-Silkscreen text"
	(layer "?.Silkscreen")
	(condition "A.Type == 'Text' || A.Type == 'Text Box'")
	(constraint text_thickness (min 0.15mm))
	(constraint text_height (min 1mm))
)

(rule "Board_11-Pad to Silkscreen"
	(layer outer)
	(condition "A.Type == 'pad' && B.Layer == '?.Silkscreen'")
	(constraint silk_clearance (min 0.15mm))
)

(rule "Board_11-Edge (routed) to track clearance"
	(condition "A.Type == 'track'")
	(constraint edge_clearance (min 0.3mm))
)

#(rule "Edge (v-cut) to track clearance"
#	(condition "A.Type == 'track'")
#	(constraint edge_clearance (min 0.4mm))
#)

# JLCPCB restrictions ambiguous:
# Illustration: 0.2 mm, 1&2 layer: 0.3 mm, multilayer: "(0.15mm more costly)"
# This rule handles diameter minimum and maximum for ALL holes.
# Other specialized rules handle restrictions (e.g. Via, PTH, NPTH) 
(rule "Board_11-Hole diameter"
	(constraint hole_size (min 0.3mm) (max 6.3mm))
)

(rule "Board_11-Hole (NPTH) diameter"
	(layer outer)
	(condition "!A.isPlated()")
	(constraint hole_size (min 0.5mm))
)

# TODO: Hole to board edge ≥ 1 mm. Min. board size 10 × 10 mm
(rule "Board_11-Hole (castellated) diameter"
	(layer outer)
	(condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'")
	(constraint hole_size (min 0.6mm))
)

# JLCPCB: "Via diameter should be 0.1mm(0.15mm preferred) larger than Via hole size" (illustration shows diameters for both dimensions)
# JLCPCB: PTH: "The annular ring size will be enlarged to 0.15mm in production."
(rule "Board_11-Annular ring width (via and PTH)"
	(layer outer)
	(condition "A.isPlated()")
	(constraint annular_width (min 0.075mm))
)

(rule "Board_11-Clearance: hole to hole (perimeter), different nets"
	(layer outer)
	(condition "A.Net != B.Net && (A.Type != 'Via' || B.Type != 'Via')")
	(constraint hole_to_hole (min 0.5mm))
)

(rule "Board_11-Clearance: via to via (perimeter), different nets"
	(layer outer)
	(condition "A.Net != B.Net && A.Type == 'Via' && B.Type == 'Via'")
	(constraint hole_to_hole (min 0.2mm))
)

(rule "Board_11-Clearance: hole to hole (perimeter), same net"
	(layer outer)
	(condition "A.Net == B.Net")
	(constraint hole_to_hole (min 0.254mm))
)

(rule "Board_11-Clearance: track to NPTH hole (perimeter)"
#	(condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track' && A.Net != B.Net")
	(condition "!A.isPlated() && B.Type == 'track' && A.Net != B.Net")
	(constraint hole_clearance (min 0.254mm))
)

(rule "Board_11-Clearance: track to PTH hole perimeter"
	(condition "A.isPlated() && B.Type == 'track' && A.Net != B.Net")
	(constraint hole_clearance (min 0.33mm))
)

# TODO: try combining with rule "Clearance: PTH to track, different nets"
(rule "Board_11-Clearance: track to pad"
	(condition "A.Type == 'pad' && B.Type == 'track' &&  A.Net != B.Net")
	(constraint clearance (min 0.2mm))
)

(rule "Board_11-Clearance: pad/via to pad/via"
	(layer outer)
#	(condition "(A.Type == 'Pad' || A.Type == 'Via') && (B.Type == 'Pad' || B.Type == 'Via') && A.Net != B.Net")	
	(condition "A.isPlated() && B.isPlated() && A.Net != B.Net")
	(constraint clearance (min 0.2mm))
)