diff --git a/Makefile b/Makefile index af4a77a..feaf426 100755 --- a/Makefile +++ b/Makefile @@ -1,4 +1,4 @@ -COMMON_INFILES=src/toplevel.vhd src/sseg_ctrl.vhd +COMMON_INFILES=src/dcm_wrap.vhd src/sseg_ctrl.vhd src/toplevel.vhd SYN_INFILES= PSMFILES= CORES= @@ -34,7 +34,7 @@ $(addprefix -uc ,$(XCF))" NGDOPTS=-p $(PART) -aul -aut $(addprefix -uc ,$(UCF)) -sd coregen/ MAPOPTS=-p $(PART) -cm balanced -timing -ol high -logic_opt on -xe n PAROPTS=-ol high -xe n -BITGENOPTS= +BITGENOPTS=-g LCK_cycle:4 TRACEOPTS=-v -u 10 SIM_INFILES=src/sim_bmppack.vhd diff --git a/src/dcm_wrap.vhd b/src/dcm_wrap.vhd new file mode 100644 index 0000000..34694db --- /dev/null +++ b/src/dcm_wrap.vhd @@ -0,0 +1,61 @@ +------------------------------------------------------------------------------- +-- Title : dcm_wrap_ctrl +-- Project : +------------------------------------------------------------------------------- +-- File : dcm_wrap.vhd +-- Author : Matthias Blankertz +-- Company : +-- Created : 2013-03-11 +-- Last update: 2013-03-11 +-- Platform : +-- Standard : VHDL'93 +------------------------------------------------------------------------------- +-- Description: +------------------------------------------------------------------------------- +-- Copyright (c) 2013 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2013-03-11 1.0 matthias Created +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library UNISIM; +use UNISIM.vcomponents.all; + +entity dcm_wrap is + generic ( + dontcare : std_logic := '-' + ); + port ( + clkin : in std_logic; + + clk50 : out std_logic; + clk25 : out std_logic + ); +end dcm_wrap; + +architecture Mixed of dcm_wrap is +signal clk50_int : std_logic; +begin + + DCM_inst : DCM_SP + generic map ( + CLKIN_PERIOD => 20.0, + STARTUP_WAIT => true, + CLKDV_DIVIDE => 2.0) + port map ( + clkin => clkin, + clkfb => clk50_int, + + clk0 => clk50_int, + clkdv => clk25, + + psen => '0', + rst => '0'); + + clk50 <= clk50_int; + +end Mixed; diff --git a/src/sseg_ctrl.vhd b/src/sseg_ctrl.vhd index ef36086..cc2e6cd 100644 --- a/src/sseg_ctrl.vhd +++ b/src/sseg_ctrl.vhd @@ -34,8 +34,9 @@ entity sseg_ctrl is sseg_an : out std_logic_vector(3 downto 0); sseg_cat : out std_logic_vector(7 downto 0); - din : std_logic_vector(15 downto 0); - dp : std_logic_vector(3 downto 0) + din : in std_logic_vector(15 downto 0); + dp : in std_logic_vector(3 downto 0); + sync : out std_logic ); end sseg_ctrl; @@ -63,33 +64,35 @@ architecture Behavioral of sseg_ctrl is ); signal seg_ctr : integer range 0 to 3 := 0; - signal ctr_16ms : integer range 0 to 799999 := 0; - signal en_16ms : std_logic; + signal ctr_4ms : integer range 0 to 199999 := 0; + signal en_4ms : std_logic; signal an_decode : std_logic_vector(3 downto 0); signal crom_adr : std_logic_vector(3 downto 0); signal crom_data : std_logic_vector(6 downto 0); signal dp_int : std_logic; begin - gen_16ms : process(clk) + gen_4ms : process(clk) begin if rising_edge(clk) then - if ctr_16ms = 799999 then - en_16ms <= '1'; - ctr_16ms <= 0; + if ctr_4ms = 199999 then + en_4ms <= '1'; + ctr_4ms <= 0; else - en_16ms <= '0'; - ctr_16ms <= ctr_16ms + 1; + en_4ms <= '0'; + ctr_4ms <= ctr_4ms + 1; end if; end if; - end process gen_16ms; + end process gen_4ms; gen_seg_ctr : process(clk) begin if rising_edge(clk) then - if en_16ms = '1' then + sync <= '0'; + if en_4ms = '1' then if seg_ctr = 3 then seg_ctr <= 0; + sync <= '1'; else seg_ctr <= seg_ctr + 1; end if; @@ -97,10 +100,10 @@ begin end if; end process gen_seg_ctr; - an_decode <= "0001" when seg_ctr = 0 else - "0010" when seg_ctr = 1 else - "0100" when seg_ctr = 2 else - "1000" when seg_ctr = 3 else + an_decode <= "1110" when seg_ctr = 0 else + "1101" when seg_ctr = 1 else + "1011" when seg_ctr = 2 else + "0111" when seg_ctr = 3 else (others => dontcare); crom_adr <= din(3 downto 0) when seg_ctr = 0 else diff --git a/src/toplevel.vhd b/src/toplevel.vhd index 9f2e3c6..47292bb 100644 --- a/src/toplevel.vhd +++ b/src/toplevel.vhd @@ -39,6 +39,15 @@ entity toplevel is end toplevel; architecture Mixed of toplevel is + component dcm_wrap + generic ( + dontcare : std_logic); + port ( + clkin : in std_logic; + clk50 : out std_logic; + clk25 : out std_logic); + end component; + component sseg_ctrl generic ( dontcare : std_logic); @@ -46,9 +55,12 @@ architecture Mixed of toplevel is clk : in std_logic; sseg_an : out std_logic_vector(3 downto 0); sseg_cat : out std_logic_vector(7 downto 0); - din : std_logic_vector(15 downto 0); - dp : std_logic_vector(3 downto 0)); + din : in std_logic_vector(15 downto 0); + dp : in std_logic_vector(3 downto 0); + sync : out std_logic); end component; + + signal clk50, clk25 : std_logic; signal ctr_1Hz : integer range 0 to 49999999 := 0; signal en_1Hz : std_logic := '0'; @@ -58,9 +70,17 @@ architecture Mixed of toplevel is signal sseg_din : std_logic_vector(15 downto 0); begin - gen_1Hz : process(clkin) + dcm_wrap_inst: dcm_wrap + generic map ( + dontcare => dontcare) + port map ( + clkin => clkin, + clk50 => clk50, + clk25 => clk25); + + gen_1Hz : process(clk50) begin - if rising_edge(clkin) then + if rising_edge(clk50) then if ctr_1Hz = 49999999 then en_1Hz <= '1'; ctr_1Hz <= 0; @@ -71,9 +91,9 @@ begin end if; end process gen_1Hz; - gen_sr : process(clkin) + gen_sr : process(clk50) begin - if rising_edge(clkin) then + if rising_edge(clk50) then if en_1Hz = '1' then sr <= sr(6 downto 0) & sr(7); ctr_secs <= ctr_secs + 1; @@ -87,11 +107,12 @@ begin generic map ( dontcare => dontcare) port map ( - clk => clkin, + clk => clk50, sseg_an => sseg_an, sseg_cat => sseg_cat, din => sseg_din, - dp => "0000" --sseg_dp + dp => "0000", --sseg_dp + sync => open ); led <= sr;