From ebdb61260d4d687017328e2dcdf12e80694c94c8 Mon Sep 17 00:00:00 2001
From: Matthias Blankertz <matthias@blankertz.org>
Date: Mon, 18 Mar 2013 15:22:58 +0100
Subject: [PATCH] - Implemented BCD counter

---
 src/bcd_ctr.vhd | 67 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 67 insertions(+)
 create mode 100644 src/bcd_ctr.vhd

diff --git a/src/bcd_ctr.vhd b/src/bcd_ctr.vhd
new file mode 100644
index 0000000..7f50ce1
--- /dev/null
+++ b/src/bcd_ctr.vhd
@@ -0,0 +1,67 @@
+-------------------------------------------------------------------------------
+-- Title      : bcd_ctr
+-- Project    : 
+-------------------------------------------------------------------------------
+-- File       : bcd_ctr.vhd
+-- Author     : Matthias Blankertz  <matthias@blankertz.org>
+-- Company    : 
+-- Created    : 2013-03-18
+-- Last update: 2013-03-18
+-- Platform   : 
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: 
+-------------------------------------------------------------------------------
+-- Copyright (c) 2013 
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author  Description
+-- 2013-03-11  1.0      matthias	Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity bcd_ctr is
+  generic (
+    dontcare : std_logic := '-'
+  );
+  port (
+    clk  : in  std_logic;
+    en   : in  std_logic;
+    dout : out std_logic_vector(15 downto 0)
+  );
+end bcd_ctr;
+
+architecture Behavioral of bcd_ctr is
+  signal ctr : unsigned(15 downto 0) := to_unsigned(0, 16);
+begin
+
+  bcd_c : process(clk)
+    variable carry : unsigned(3 downto 0) := (others => '0');
+    variable dtmp : unsigned(3 downto 0);
+  begin
+    if rising_edge(clk) then
+      if en = '1' then
+        for i in 0 to 3 loop
+          if i = 0 then
+            dtmp := ctr(3 downto 0) + 1;
+          else
+            dtmp := ctr((i+1)*4-1 downto i*4) + ("000" & carry(i-1));
+          end if;
+          if dtmp = 10 then
+            carry(i) := '1';
+            ctr((i+1)*4-1 downto i*4) <= to_unsigned(0,4);
+          else
+            carry(i) := '0';
+            ctr((i+1)*4-1 downto i*4) <= dtmp(3 downto 0);
+          end if;
+        end loop;
+      end if;
+    end if;
+  end process bcd_c;
+
+  dout <= std_logic_vector(ctr);
+  
+end Behavioral;