151 lines
4.2 KiB
Makefile
Executable File
151 lines
4.2 KiB
Makefile
Executable File
COMMON_INFILES=src/dcm_wrap.vhd src/sseg_ctrl.vhd src/toplevel.vhd
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SYN_INFILES=
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PSMFILES=
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CORES=
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PRJNAME=willi_board
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NGCFILE=$(PRJNAME).ngc
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XSTFILE=$(PRJNAME).xst
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XCF=constr/$(PRJNAME).xcf
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UCF=constr/$(PRJNAME).ucf
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PCFFILE=$(PRJNAME).pcf
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NGDFILE=$(PRJNAME).ngd
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NCDFILE=$(PRJNAME).ncd
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NCDFILE_R=$(PRJNAME)_routed.ncd
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BITFILE=$(PRJNAME).bit
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TWRFILE=$(PRJNAME).twr
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TWXFILE=$(PRJNAME).twx
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PRJFILE=$(PRJNAME).prj
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PART=xc3s250e-cp132-4
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XSTOPTS="-ifn $(PRJFILE) \
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-ifmt mixed \
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-top toplevel \
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-ofn $(NGCFILE) \
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-ofmt NGC \
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-p $(PART) \
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-opt_mode Speed \
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-opt_level 1 \
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-fsm_encoding auto \
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-sd coregen/ \
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-read_cores yes \
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-rtlview no \
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-iob auto \
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-keep_hierarchy soft \
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$(addprefix -uc ,$(XCF))"
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NGDOPTS=-p $(PART) -aul -aut $(addprefix -uc ,$(UCF)) -sd coregen/
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MAPOPTS=-p $(PART) -cm balanced -timing -ol high -logic_opt on -xe n
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PAROPTS=-ol high -xe n
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BITGENOPTS=-g LCK_cycle:4
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TRACEOPTS=-v -u 10
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SIM_INFILES=
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SIM_INFILES_VLOG=
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VLOGCOMPOPTS=
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VHPCOMPOPTS=-L ieee_proposed=isim/ieee_proposed --incremental
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FUSEOPTS=-L ieee_proposed=isim/ieee_proposed
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SYNALLFILES=$(COMMON_INFILES) $(SYN_INFILES)
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SIMALLFILES=$(SIM_INFILES) $(COMMON_INFILES)
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SIMALLFILESXDB=isim/ieee_proposed/std_logic_1164_additions.vdb \
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$(addprefix isim/work/,$(notdir $(SIMALLFILES:.vhd=.vdb))) \
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$(addprefix isim/work/,$(notdir $(SIM_INFILES_VLOG:.v=.sdb)))
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CORESVDB=$(addprefix isim/work/,$(addsuffix .vdb,$(CORES)))
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CORESNGC=$(addprefix coregen/,$(addsuffix .ngc,$(CORES)))
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XILPATH=
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COREGEN=$(XILPATH)coregen
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XST=$(XILPATH)xst
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NGDBUILD=$(XILPATH)ngdbuild
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MAP=$(XILPATH)map
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PAR=$(XILPATH)par
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BITGEN=$(XILPATH)bitgen
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TRCE=$(XILPATH)trce
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VHPCOMP=$(XILPATH)vhpcomp
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VLOGCOMP=$(XILPATH)vlogcomp
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FUSE=$(XILPATH)fuse
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.SECONDARY:
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all: $(BITFILE) #firmware/fw.elf
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synth: $(NGCFILE)
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impl: $(NCDFILE_R)
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timing: $(TWRFILE)
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#firmware/fw.elf:
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# cd firmware && make fw.elf
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#%.vhd: %.psm
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# ../tools/picoasm/picoasm -t ../tools/picoasm/ROM_form.vhd -i $<
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#src/wb_interconnect.vhd: src/wishbone.defines
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# cd src && ../tools/wishbone.pl -nogui wishbone.defines
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#
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coregen/%.vhd coregen/%.ncd: coregen/%.xco coregen/coregen.cgp
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$(COREGEN) -p coregen/coregen.cgp -b $< -r
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$(PRJFILE): Makefile
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rm -f $(PRJFILE); for i in $(SYNALLFILES); do echo "vhdl work" $$i >> $(PRJFILE); done
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$(XSTFILE): Makefile
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rm -f $@; echo "run $(XSTOPTS)" > $@
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planahead_postsynth.tcl: Makefile
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rm -f $@; echo -e "create_project -force -part $(PART) postsynth planahead\n\
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set_property design_mode GateLvl [current_fileset]\n\
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import_files $(NGCFILE) $(CORESNGC)\n\
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import_files -fileset constrs_1 $(UCF)" > $@
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planahead_postimpl.tcl: Makefile
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rm -f $@; echo -e "create_project -force -part $(PART) postimpl planahead\n\
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set_property design_mode GateLvl [current_fileset]\n\
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add_files $(NGCFILE) $(CORESNGC)\n\
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import_files -fileset constrs_1 $(UCF)\n\
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import_as_run -run impl_1 -twx $(TWXFILE) $(NCDFILE_R)" > $@
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planahead_postsynth: planahead_postsynth.tcl $(NGCFILE) $(UCF) $(CORESNGC)
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planAhead -source planahead_postsynth.tcl
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planahead_postimpl: planahead_postimpl.tcl $(NCDFILE) $(UCF) $(NCDFILE_R) $(TWXFILE) $(CORESNGC)
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planAhead -source planahead_postimpl.tcl
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$(NGCFILE): $(SYNALLFILES) $(PRJFILE) $(XSTFILE) $(XCF) $(CORESNGC)
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$(XST) -ifn $(XSTFILE)
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$(NGDFILE): $(NGCFILE) $(UCF) $(CORESNGC)
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$(NGDBUILD) $(NGDOPTS) $(NGCFILE) $(NGDFILE)
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$(PCFFILE) $(NCDFILE): $(NGDFILE)
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$(MAP) $(MAPOPTS) -o $(NCDFILE) $(NGDFILE) $(PCFFILE)
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$(NCDFILE_R): $(PCFFILE) $(NCDFILE)
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$(PAR) -w $(PAROPTS) $(NCDFILE) $(NCDFILE_R) $(PCFFILE)
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$(BITFILE): $(NCDFILE_R) $(PCFFILE)
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$(BITGEN) -w $(BITGENOPTS) $(NCDFILE_R) $(BITFILE) $(PCFFILE)
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$(TWRFILE) $(TWXFILE): $(NCDFILE_R) $(PCFFILE)
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$(TRCE) $(TRACEOPTS) -o $(TWRFILE) $(NCDFILE_R) $(PCFFILE)
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isim/ieee_proposed/std_logic_1164_additions.vdb: tools/std_logic_1164_additions.vhdl
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$(VHPCOMP) --work ieee_proposed=isim/ieee_proposed $< $(VHPCOMPOPTS)
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isim/work/%.vdb: src/%.vhd
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$(VHPCOMP) $< $(VHPCOMPOPTS)
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isim/work/%.vdb: tb/%.vhd
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$(VHPCOMP) $< $(VHPCOMPOPTS)
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isim/work/%.vdb: coregen/%.vhd
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$(VHPCOMP) $< $(VHPCOMPOPTS)
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%.exe: $(SIMALLFILESXDB) $(CORESVDB) isim/work/%.vdb
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$(FUSE) work.$(@:.exe=) -o $@ $(FUSEOPTS)
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clean:
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rm -f $(NGCFILE) $(PCFFILE) $(NGDFILE) $(NCDFILE) $(NCDFILE_R) $(BITFILE) $(SIMALLFILESXDB) $(CORESVDB)
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.PSEUDO=all synth impl timing clean planahead_postsynth planahead_postimpl
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