89 lines
2.4 KiB
VHDL
89 lines
2.4 KiB
VHDL
-------------------------------------------------------------------------------
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-- Title : Testbench for design "toplevel"
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-- Project :
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-------------------------------------------------------------------------------
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-- File : toplevel_tb.vhd
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-- Author : Matthias Blankertz <matthias@matthias-tp>
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-- Company :
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-- Created : 2013-03-12
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-- Last update: 2013-03-12
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-- Platform :
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-- Standard : VHDL'87
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-------------------------------------------------------------------------------
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-- Description:
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-------------------------------------------------------------------------------
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-- Copyright (c) 2013
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Date Version Author Description
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-- 2013-03-12 1.0 matthias Created
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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-------------------------------------------------------------------------------
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entity toplevel_tb is
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end toplevel_tb;
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-------------------------------------------------------------------------------
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architecture testbench of toplevel_tb is
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component toplevel
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generic (
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dontcare : std_logic);
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port (
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clkin : in std_logic;
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led : out std_logic_vector(7 downto 0);
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sseg_an : out std_logic_vector(3 downto 0);
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sseg_cat : out std_logic_vector(7 downto 0));
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end component;
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-- component generics
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constant dontcare : std_logic := '0';
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-- component ports
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signal clkin : std_logic := '0';
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signal led : std_logic_vector(7 downto 0);
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signal sseg_an : std_logic_vector(3 downto 0);
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signal sseg_cat : std_logic_vector(7 downto 0);
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begin -- testbench
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-- component instantiation
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DUT: toplevel
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generic map (
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dontcare => dontcare)
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port map (
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clkin => clkin,
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led => led,
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sseg_an => sseg_an,
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sseg_cat => sseg_cat);
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-- clock generation
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clkin <= not clkin after 10 ns;
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-- waveform generation
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WaveGen_Proc: process
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begin
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-- insert signal assignments here
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wait;
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end process WaveGen_Proc;
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end testbench;
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-------------------------------------------------------------------------------
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configuration toplevel_tb_testbench_cfg of toplevel_tb is
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for testbench
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end for;
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end toplevel_tb_testbench_cfg;
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-------------------------------------------------------------------------------
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