a0d4fdcce0
Fixes automatic baudrate calculation results. Default clock source on this SoC is HSE not PCLK1. We could fix this by switching to PCLK1 instead, but two extra complications: - PCLK1 on this board is a 42.5MHz and the Pyboard CAN sample_point calculation requires an exact match, which is harder to hit with this source frequency. - Would be a breaking change for any existing Python code on this board, i.e. specifying brp, bs1, bs2 to initialise CAN. In the future it might be worth looking switching to the PLL source on this SoC instead, as this is a much higher frequency that would give higher quality BRS bitrate matches (probably too high without using the second divider going into the CAN peripheral though, so more code changes needed also). This work was funded through GitHub Sponsors. Signed-off-by: Angus Gratton <angus@redyak.com.au>
43 KiB
43 KiB