Matthias Blankertz
7f8282315e
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The python and C modules that are supposed to be built into the firmware image (i.e. those that are in manifest.py or in USER_C_MODULES) have been moved to the software/modules directory. The software/src directory should now only contain python scripts and other files that should be installed to the Picos flash filesystem. The idea is that these should be those scripts that implement the application behaviour, as these are the ones that a user who does not want to build the whole firmware themself wants to modify.
294 lines
12 KiB
C
294 lines
12 KiB
C
#include "hardware/pio.h"
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#include "sd_spi.h"
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#include "sd_util.h"
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#include "sd_spi_pio.pio.h"
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#include "hardware/dma.h"
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#include <hardware/gpio.h>
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#include <hardware/spi.h>
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#include <hardware/sync.h>
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#include <pico/time.h>
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#include <string.h>
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struct sd_dma_context {
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uint8_t *read_buf;
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size_t len;
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uint8_t crc_buf[2];
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uint8_t read_token_buf;
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uint8_t wrdata;
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_Atomic enum { DMA_READ_TOKEN, DMA_READ, DMA_IDLE } state;
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};
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struct sd_spi_context {
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struct sd_dma_context sd_dma_context;
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int spi_sm;
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unsigned spi_offset;
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int spi_dma_rd, spi_dma_wr, spi_dma_rd_crc;
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dma_channel_config spi_dma_rd_cfg, spi_dma_wr_cfg, spi_dma_rd_crc_cfg;
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int mosi, miso, sck, ss;
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bool initialized;
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};
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/* We only realistically need one context, so reduce overhead by statically allocating it here */
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static struct sd_spi_context sd_spi_context = {};
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static void __time_critical_func(sd_spi_write_blocking)(const uint8_t *data, size_t len)
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{
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if (len == 0)
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return;
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pio_sm_put(SD_PIO, sd_spi_context.spi_sm, data[0] << 24);
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for (size_t i = 1; i < len; ++i) {
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pio_sm_put(SD_PIO, sd_spi_context.spi_sm, data[i] << 24);
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pio_sm_get_blocking(SD_PIO, sd_spi_context.spi_sm);
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}
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pio_sm_get_blocking(SD_PIO, sd_spi_context.spi_sm);
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assert(pio_sm_is_tx_fifo_empty(SD_PIO, sd_spi_context.spi_sm));
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assert(pio_sm_is_rx_fifo_empty(SD_PIO, sd_spi_context.spi_sm));
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}
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static void __time_critical_func(sd_spi_read_blocking)(uint8_t wrdata, uint8_t *data, size_t len)
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{
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if (len == 0)
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return;
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pio_sm_put(SD_PIO, sd_spi_context.spi_sm, wrdata << 24);
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for (size_t i = 0; i < len - 1; ++i) {
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pio_sm_put(SD_PIO, sd_spi_context.spi_sm, wrdata << 24);
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data[i] = pio_sm_get_blocking(SD_PIO, sd_spi_context.spi_sm);
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}
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data[len - 1] = pio_sm_get_blocking(SD_PIO, sd_spi_context.spi_sm);
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assert(pio_sm_is_tx_fifo_empty(SD_PIO, sd_spi_context.spi_sm));
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assert(pio_sm_is_rx_fifo_empty(SD_PIO, sd_spi_context.spi_sm));
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}
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static void __time_critical_func(sd_spi_dma_isr)(void)
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{
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if (dma_channel_get_irq0_status(sd_spi_context.spi_dma_rd)) {
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dma_channel_acknowledge_irq0(sd_spi_context.spi_dma_rd);
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if (sd_spi_context.sd_dma_context.state == DMA_READ_TOKEN) {
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if (sd_spi_context.sd_dma_context.read_token_buf != 0xff) {
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if (sd_spi_context.sd_dma_context.read_token_buf == 0xfe) {
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channel_config_set_chain_to(&sd_spi_context.spi_dma_rd_cfg, sd_spi_context.spi_dma_rd_crc);
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channel_config_set_irq_quiet(&sd_spi_context.spi_dma_rd_cfg, true);
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dma_channel_configure(sd_spi_context.spi_dma_rd, &sd_spi_context.spi_dma_rd_cfg,
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sd_spi_context.sd_dma_context.read_buf, &SD_PIO->rxf[sd_spi_context.spi_sm],
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sd_spi_context.sd_dma_context.len, false);
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dma_channel_configure(sd_spi_context.spi_dma_wr, &sd_spi_context.spi_dma_wr_cfg,
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&SD_PIO->txf[sd_spi_context.spi_sm], &sd_spi_context.sd_dma_context.wrdata,
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sd_spi_context.sd_dma_context.len + 2, false);
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dma_channel_configure(sd_spi_context.spi_dma_rd_crc, &sd_spi_context.spi_dma_rd_crc_cfg,
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sd_spi_context.sd_dma_context.crc_buf, &SD_PIO->rxf[sd_spi_context.spi_sm], 2,
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false);
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dma_start_channel_mask((1 << sd_spi_context.spi_dma_rd) | (1 << sd_spi_context.spi_dma_wr));
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sd_spi_context.sd_dma_context.state = DMA_READ;
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} else {
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// Bad read token, abort transfer
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sd_spi_context.sd_dma_context.state = DMA_IDLE;
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}
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} else {
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// try again
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dma_channel_configure(sd_spi_context.spi_dma_rd, &sd_spi_context.spi_dma_rd_cfg,
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&sd_spi_context.sd_dma_context.read_token_buf,
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&SD_PIO->rxf[sd_spi_context.spi_sm], 1, false);
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dma_channel_configure(sd_spi_context.spi_dma_wr, &sd_spi_context.spi_dma_wr_cfg,
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&SD_PIO->txf[sd_spi_context.spi_sm], &sd_spi_context.sd_dma_context.wrdata, 1,
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false);
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dma_start_channel_mask((1 << sd_spi_context.spi_dma_rd) | (1 << sd_spi_context.spi_dma_wr));
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}
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}
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}
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if (dma_channel_get_irq0_status(sd_spi_context.spi_dma_rd_crc)) {
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dma_channel_acknowledge_irq0(sd_spi_context.spi_dma_rd_crc);
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assert(sd_spi_context.sd_dma_context.state == DMA_READ);
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sd_spi_context.sd_dma_context.state = DMA_IDLE;
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}
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}
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void sd_spi_wait_complete(void)
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{
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while (sd_spi_context.sd_dma_context.state != DMA_IDLE)
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__wfi();
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}
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bool sd_cmd_read_is_complete(void) { return sd_spi_context.sd_dma_context.state == DMA_IDLE; }
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static bool sd_spi_read_dma(uint8_t wrdata, uint8_t *data, size_t len)
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{
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if (sd_spi_context.sd_dma_context.state != DMA_IDLE)
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return false;
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channel_config_set_chain_to(&sd_spi_context.spi_dma_rd_cfg, sd_spi_context.spi_dma_rd);
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channel_config_set_irq_quiet(&sd_spi_context.spi_dma_rd_cfg, false);
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dma_channel_configure(sd_spi_context.spi_dma_rd, &sd_spi_context.spi_dma_rd_cfg,
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&sd_spi_context.sd_dma_context.read_token_buf, &SD_PIO->rxf[sd_spi_context.spi_sm], 1, false);
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dma_channel_configure(sd_spi_context.spi_dma_wr, &sd_spi_context.spi_dma_wr_cfg,
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&SD_PIO->txf[sd_spi_context.spi_sm], &sd_spi_context.sd_dma_context.wrdata, 1, false);
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sd_spi_context.sd_dma_context.state = DMA_READ_TOKEN;
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sd_spi_context.sd_dma_context.len = len;
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sd_spi_context.sd_dma_context.read_buf = data;
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sd_spi_context.sd_dma_context.wrdata = wrdata;
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dma_start_channel_mask((1 << sd_spi_context.spi_dma_rd) | (1 << sd_spi_context.spi_dma_wr));
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return true;
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}
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static void sd_spi_cmd_send(const uint8_t cmd, const uint32_t arg)
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{
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uint8_t buf[6] = {0x40 | cmd, arg >> 24, arg >> 16, arg >> 8, arg, 0};
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buf[5] = sd_crc7(5, buf) << 1 | 1;
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gpio_put(sd_spi_context.ss, false);
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// Write command, argument and CRC
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sd_spi_write_blocking(buf, 6);
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}
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bool sd_cmd(const uint8_t cmd, const uint32_t arg, unsigned resplen, uint8_t resp[static resplen])
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{
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sd_spi_cmd_send(cmd, arg);
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resp[0] = 0;
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// Read up to 8 garbage bytes (0xff), followed by R1 (MSB is zero)
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bool got_r1 = false;
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for (int timeout = 0; timeout < 8; ++timeout) {
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sd_spi_read_blocking(0xff, resp, 1);
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if (!(resp[0] & 0x80)) {
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got_r1 = true;
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break;
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}
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}
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if (got_r1 && (resp[0] & 0x7e) == 0) {
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// read rest of response if R1 does not indicate an error
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sd_spi_read_blocking(0xff, resp + 1, resplen - 1);
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}
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gpio_put(sd_spi_context.ss, true);
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const uint8_t buf = 0xff;
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// Ensure 8 SPI clock cycles after CS deasserted
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sd_spi_write_blocking(&buf, 1);
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return got_r1 && (resp[0] & 0x7e) == 0;
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}
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bool sd_cmd_read(uint8_t cmd, uint32_t arg, unsigned datalen, uint8_t data[static datalen])
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{
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if (!sd_cmd_read_start(cmd, arg, datalen, data))
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return false;
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return sd_cmd_read_complete();
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}
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bool sd_cmd_read_start(uint8_t cmd, uint32_t arg, unsigned datalen, uint8_t data[static datalen])
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{
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uint8_t buf[2];
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sd_spi_cmd_send(cmd, arg);
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// Read up to 8 garbage bytes (0xff), followed by R1 (MSB is zero)
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bool got_r1 = false;
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for (int timeout = 0; timeout < 8; ++timeout) {
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sd_spi_read_blocking(0xff, buf, 1);
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if (!(buf[0] & 0x80)) {
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got_r1 = true;
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break;
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}
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}
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if (!got_r1 || buf[0] != 0x00)
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goto abort;
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if (!sd_spi_read_dma(0xff, data, datalen))
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goto abort;
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return true;
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abort:
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gpio_put(sd_spi_context.ss, true);
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sd_spi_read_blocking(0xff, buf, 1);
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return false;
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}
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bool sd_cmd_read_complete(void)
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{
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uint8_t buf;
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sd_spi_wait_complete();
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gpio_put(sd_spi_context.ss, true);
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sd_spi_read_blocking(0xff, &buf, 1);
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return (sd_spi_context.sd_dma_context.read_token_buf == 0xfe);
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}
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bool sd_spi_init(int mosi, int miso, int sck, int ss)
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{
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if (sd_spi_context.initialized)
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return false;
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if (!pio_can_add_program(SD_PIO, &sd_spi_pio_program))
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return false;
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sd_spi_context.spi_sm = pio_claim_unused_sm(SD_PIO, false);
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if (sd_spi_context.spi_sm == -1)
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return false;
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sd_spi_context.spi_offset = pio_add_program(SD_PIO, &sd_spi_pio_program);
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sd_spi_context.mosi = mosi;
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sd_spi_context.miso = miso;
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sd_spi_context.sck = sck;
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sd_spi_context.ss = ss;
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sd_spi_pio_program_init(SD_PIO, sd_spi_context.spi_sm, sd_spi_context.spi_offset, sd_spi_context.mosi,
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sd_spi_context.miso, sd_spi_context.sck, SD_INIT_BITRATE);
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pio_sm_set_enabled(SD_PIO, sd_spi_context.spi_sm, true);
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gpio_init(sd_spi_context.ss);
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gpio_set_dir(sd_spi_context.ss, true);
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sd_spi_context.spi_dma_rd = dma_claim_unused_channel(false);
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sd_spi_context.spi_dma_rd_crc = dma_claim_unused_channel(false);
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sd_spi_context.spi_dma_wr = dma_claim_unused_channel(false);
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if (sd_spi_context.spi_dma_rd == -1 || sd_spi_context.spi_dma_rd_crc == -1 || sd_spi_context.spi_dma_wr == -1)
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return false;
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sd_spi_context.spi_dma_rd_cfg = dma_channel_get_default_config(sd_spi_context.spi_dma_rd);
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channel_config_set_read_increment(&sd_spi_context.spi_dma_rd_cfg, false);
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channel_config_set_write_increment(&sd_spi_context.spi_dma_rd_cfg, true);
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channel_config_set_dreq(&sd_spi_context.spi_dma_rd_cfg, pio_get_dreq(SD_PIO, sd_spi_context.spi_sm, false));
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channel_config_set_transfer_data_size(&sd_spi_context.spi_dma_rd_cfg, DMA_SIZE_8);
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sd_spi_context.spi_dma_rd_crc_cfg = dma_channel_get_default_config(sd_spi_context.spi_dma_rd_crc);
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channel_config_set_read_increment(&sd_spi_context.spi_dma_rd_crc_cfg, false);
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channel_config_set_dreq(&sd_spi_context.spi_dma_rd_crc_cfg, pio_get_dreq(SD_PIO, sd_spi_context.spi_sm, false));
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channel_config_set_transfer_data_size(&sd_spi_context.spi_dma_rd_crc_cfg, DMA_SIZE_8);
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sd_spi_context.spi_dma_wr_cfg = dma_channel_get_default_config(sd_spi_context.spi_dma_wr);
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channel_config_set_read_increment(&sd_spi_context.spi_dma_wr_cfg, false);
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channel_config_set_dreq(&sd_spi_context.spi_dma_wr_cfg, pio_get_dreq(SD_PIO, sd_spi_context.spi_sm, true));
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channel_config_set_transfer_data_size(&sd_spi_context.spi_dma_wr_cfg, DMA_SIZE_8);
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sd_spi_context.sd_dma_context.state = DMA_IDLE;
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irq_add_shared_handler(DMA_IRQ_0, &sd_spi_dma_isr, PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY);
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dma_channel_set_irq0_enabled(sd_spi_context.spi_dma_rd, true);
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dma_channel_set_irq0_enabled(sd_spi_context.spi_dma_rd_crc, true);
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irq_set_enabled(DMA_IRQ_0, true);
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gpio_put(sd_spi_context.ss, true);
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uint8_t buf[16];
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memset(buf, 0xff, 16);
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// Ensure at least 74 SPI clock cycles without CS asserted
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sd_spi_write_blocking(buf, 10);
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sd_spi_context.initialized = true;
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return true;
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}
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bool sd_spi_deinit(void)
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{
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if (!sd_spi_context.initialized)
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return false;
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if (sd_spi_context.sd_dma_context.state != DMA_IDLE)
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return false;
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dma_channel_set_irq0_enabled(sd_spi_context.spi_dma_rd, false);
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dma_channel_set_irq0_enabled(sd_spi_context.spi_dma_rd_crc, false);
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irq_remove_handler(DMA_IRQ_0, &sd_spi_dma_isr);
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dma_channel_unclaim(sd_spi_context.spi_dma_rd);
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dma_channel_unclaim(sd_spi_context.spi_dma_rd_crc);
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dma_channel_unclaim(sd_spi_context.spi_dma_wr);
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pio_remove_program(SD_PIO, &sd_spi_pio_program, sd_spi_context.spi_offset);
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pio_sm_unclaim(SD_PIO, sd_spi_context.spi_sm);
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sd_spi_context.initialized = false;
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return true;
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}
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void sd_spi_set_bitrate(const int rate)
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{
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pio_sm_set_enabled(SD_PIO, sd_spi_context.spi_sm, false);
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sd_spi_pio_program_init(SD_PIO, sd_spi_context.spi_sm, sd_spi_context.spi_offset, sd_spi_context.mosi,
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sd_spi_context.miso, sd_spi_context.sck, rate);
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pio_sm_set_enabled(SD_PIO, sd_spi_context.spi_sm, true);
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}
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