matthias/2d_display_engine-new
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- System integration & debugging

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This commit is contained in:
Matthias Blankertz
2013-03-09 14:14:22 +01:00
parent 861cd1e00d
commit 077bef75d3
14 changed files with 1026 additions and 355 deletions
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6
Makefile
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@@ -26,7 +26,7 @@ ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_s3_dm_iob.vhd \
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_s3_dqs_iob.vhd \ ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_s3_dqs_iob.vhd \
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_s3_dq_iob.vhd \ ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_s3_dq_iob.vhd \
src/wb_interconnect.vhd \ src/wb_interconnect.vhd \
src/wb_rom.vhd src/wb_ram.vhd \ src/wb_rom.vhd src/wb_ram.vhd src/cpu.vhd \
src/clk_reset.vhd src/wb_ddr_ctrl.vhd src/wb_ddr_ctrl_ddrwrap.vhd \ src/clk_reset.vhd src/wb_ddr_ctrl.vhd src/wb_ddr_ctrl_ddrwrap.vhd \
src/wb_ddr_ctrl_wb.vhd src/wb_ddr_ctrl_wb_dc_fsm.vhd src/wb_ddr_ctrl_wb_dc.vhd \ src/wb_ddr_ctrl_wb.vhd src/wb_ddr_ctrl_wb_dc_fsm.vhd src/wb_ddr_ctrl_wb_dc.vhd \
src/wb_ddr_ctrl_wb_sc_fe_ram.vhd src/wb_ddr_ctrl_wb_sc_fe_fsm.vhd src/wb_ddr_ctrl_wb_sc_fe.vhd \ src/wb_ddr_ctrl_wb_sc_fe_ram.vhd src/wb_ddr_ctrl_wb_sc_fe_fsm.vhd src/wb_ddr_ctrl_wb_sc_fe.vhd \
@@ -52,8 +52,8 @@ TWRFILE=$(PRJNAME).twr
PRJFILE=$(PRJNAME).prj PRJFILE=$(PRJNAME).prj
PART=xc3s700an-fgg484-4 PART=xc3s700an-fgg484-4
NGDOPTS=-p $(PART) -aul -aut $(addprefix -uc ,$(UCF)) -sd coregen/ NGDOPTS=-p $(PART) -aul -aut $(addprefix -uc ,$(UCF)) -sd coregen/
MAPOPTS=-p $(PART) -cm balanced -timing -ol high -logic_opt on MAPOPTS=-p $(PART) -cm balanced -timing -ol high -logic_opt on -xe n
PAROPTS=-ol high PAROPTS=-ol high -xe n
BITGENOPTS= BITGENOPTS=
TRACEOPTS=-v -u 100 TRACEOPTS=-v -u 100

38
constr/2d_display_engine.ucf
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@@ -1,27 +1,33 @@
# Timing constraints # Timing constraints
NET "CLKIN_50MHZ" PERIOD = 20.0ns HIGH 40%; NET "CLKIN_50MHZ" TNM_NET = "CLK_50";
NET "CLKIN_133MHZ" PERIOD = 7.51ns HIGH 40%; TIMESPEC "TS_CLK_50" = PERIOD "CLK_50" 20.0 ns HIGH 50 %;
# NET "CLKIN_133MHZ" PERIOD = 7.51ns HIGH 40%;
TIMEGRP "vga" OFFSET = OUT 10ns AFTER "CLKIN_50MHZ" RISING;
# Location and I/O defs # Location and I/O defs
# Clocks # Clocks
NET "CLKIN_50MHZ" LOC = "E12"| IOSTANDARD = LVCMOS33 ; NET "CLKIN_50MHZ" LOC = "E12"| IOSTANDARD = LVCMOS33 ;
NET "CLKIN_133MHZ" LOC = "V12"| IOSTANDARD = LVCMOS33 ; NET "CLKIN_133MHZ" LOC = "V12"| IOSTANDARD = LVCMOS33 ;
# Reset (on BTN_EAST)
NET "RESET" LOC = "T16" | IOSTANDARD = LVCMOS33 | PULLDOWN ;
# VGA output # VGA output
NET "VGA_R<3>" LOC = "C8" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; NET "VGA_R<3>" LOC = "C8" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | TNM_NET = "VGA" ;
NET "VGA_R<2>" LOC = "B8" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; NET "VGA_R<2>" LOC = "B8" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | TNM_NET = "VGA" ;
NET "VGA_R<1>" LOC = "B3" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; NET "VGA_R<1>" LOC = "B3" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | TNM_NET = "VGA" ;
NET "VGA_R<0>" LOC = "A3" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; NET "VGA_R<0>" LOC = "A3" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | TNM_NET = "VGA" ;
NET "VGA_G<3>" LOC = "D6" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; NET "VGA_G<3>" LOC = "D6" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | TNM_NET = "VGA" ;
NET "VGA_G<2>" LOC = "C6" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; NET "VGA_G<2>" LOC = "C6" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | TNM_NET = "VGA" ;
NET "VGA_G<1>" LOC = "D5" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; NET "VGA_G<1>" LOC = "D5" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | TNM_NET = "VGA" ;
NET "VGA_G<0>" LOC = "C5" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; NET "VGA_G<0>" LOC = "C5" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | TNM_NET = "VGA" ;
NET "VGA_B<3>" LOC = "C9" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; NET "VGA_B<3>" LOC = "C9" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | TNM_NET = "VGA" ;
NET "VGA_B<2>" LOC = "B9" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; NET "VGA_B<2>" LOC = "B9" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | TNM_NET = "VGA" ;
NET "VGA_B<1>" LOC = "D7" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; NET "VGA_B<1>" LOC = "D7" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | TNM_NET = "VGA" ;
NET "VGA_B<0>" LOC = "C7" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; NET "VGA_B<0>" LOC = "C7" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | TNM_NET = "VGA" ;
NET "VGA_HSYNC" LOC = "C11" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; NET "VGA_HSYNC" LOC = "C11" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | TNM_NET = "VGA" ;
NET "VGA_VSYNC" LOC = "B11" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; NET "VGA_VSYNC" LOC = "B11" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | TNM_NET = "VGA" ;
# SPI flash # SPI flash
NET "DATAFLASH_MISO" LOC = "AB20" | IOSTANDARD = LVCMOS33 ; NET "DATAFLASH_MISO" LOC = "AB20" | IOSTANDARD = LVCMOS33 ;

12
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_clk_dcm.vhd
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@@ -64,6 +64,7 @@ entity vhdl_bl4_clk_dcm is
rst : in std_logic; rst : in std_logic;
clk : out std_logic; clk : out std_logic;
clk90 : out std_logic; clk90 : out std_logic;
clk180 : out std_logic;
dcm_lock : out std_logic dcm_lock : out std_logic
); );
end vhdl_bl4_clk_dcm; end vhdl_bl4_clk_dcm;
@@ -72,8 +73,10 @@ architecture arc of vhdl_bl4_clk_dcm is
signal clk0dcm : std_logic; signal clk0dcm : std_logic;
signal clk90dcm : std_logic; signal clk90dcm : std_logic;
signal clk180dcm : std_logic;
signal clk0_buf : std_logic; signal clk0_buf : std_logic;
signal clk90_buf : std_logic; signal clk90_buf : std_logic;
signal clk180_buf : std_logic;
signal gnd : std_logic; signal gnd : std_logic;
signal dcm1_lock : std_logic; signal dcm1_lock : std_logic;
@@ -82,6 +85,7 @@ begin
gnd <= '0'; gnd <= '0';
clk <= clk0_buf; clk <= clk0_buf;
clk90 <= clk90_buf; clk90 <= clk90_buf;
clk180 <= clk180_buf;
DCM_INST1 : DCM DCM_INST1 : DCM
generic map( generic map(
@@ -98,7 +102,7 @@ begin
RST => rst, RST => rst,
CLK0 => clk0dcm, CLK0 => clk0dcm,
CLK90 => clk90dcm, CLK90 => clk90dcm,
CLK180 => open, CLK180 => clk180dcm,
CLK270 => open, CLK270 => open,
CLK2X => open, CLK2X => open,
CLK2X180 => open, CLK2X180 => open,
@@ -122,6 +126,12 @@ begin
I => clk90dcm I => clk90dcm
); );
BUFG_CLK180 : BUFG
port map (
O => clk180_buf,
I => clk180dcm
);
dcm_lock <= dcm1_lock; dcm_lock <= dcm1_lock;
end arc; end arc;

5
ddr2_sdram/vhdl_bl4/example_design/rtl/vhdl_bl4_infrastructure_top.vhd
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@@ -70,6 +70,7 @@ entity vhdl_bl4_infrastructure_top is
sys_rst90_val : out std_logic; sys_rst90_val : out std_logic;
clk_int_val : out std_logic; clk_int_val : out std_logic;
clk90_int_val : out std_logic; clk90_int_val : out std_logic;
clk180_int_val : out std_logic;
sys_rst180_val : out std_logic; sys_rst180_val : out std_logic;
wait_200us : out std_logic; wait_200us : out std_logic;
-- debug signals -- debug signals
@@ -90,6 +91,7 @@ architecture arc of vhdl_bl4_infrastructure_top is
rst : in std_logic; rst : in std_logic;
clk : out std_logic; clk : out std_logic;
clk90 : out std_logic; clk90 : out std_logic;
clk180 : out std_logic;
dcm_lock : out std_logic dcm_lock : out std_logic
); );
end component; end component;
@@ -112,6 +114,7 @@ architecture arc of vhdl_bl4_infrastructure_top is
signal user_cal_rst : std_logic; signal user_cal_rst : std_logic;
signal clk_int : std_logic; signal clk_int : std_logic;
signal clk90_int : std_logic; signal clk90_int : std_logic;
signal clk180_int : std_logic;
signal dcm_lock : std_logic; signal dcm_lock : std_logic;
signal sys_rst_o : std_logic; signal sys_rst_o : std_logic;
signal sys_rst_1 : std_logic := '1'; signal sys_rst_1 : std_logic := '1';
@@ -157,6 +160,7 @@ begin
clk_int_val <= clk_int; clk_int_val <= clk_int;
clk90_int_val <= clk90_int; clk90_int_val <= clk90_int;
clk180_int_val <= clk180_int;
sys_rst_val <= sys_rst; sys_rst_val <= sys_rst;
sys_rst90_val <= sys_rst90; sys_rst90_val <= sys_rst90;
sys_rst180_val <= sys_rst180; sys_rst180_val <= sys_rst180;
@@ -274,6 +278,7 @@ begin
rst => user_rst, rst => user_rst,
clk => clk_int, clk => clk_int,
clk90 => clk90_int, clk90 => clk90_int,
clk180 => clk180_int,
dcm_lock => dcm_lock dcm_lock => dcm_lock
); );

146
src/cpu.vhd
View File

@@ -42,106 +42,108 @@ entity cpu is
burst_length : integer := 16 burst_length : integer := 16
); );
port ( port (
clk : in std_logic; clk_i : in std_logic;
rst : in std_logic; rst_i : in std_logic;
enable_vga : out std_logic; wbm_i : in cpu_wbm_i_type;
wbm_o : out cpu_wbm_o_type
cpu_wbm_i : in cpu_wbm_i_type;
cpu_wbm_o : out cpu_wbm_o_type
); );
end cpu; end cpu;
architecture Behavioral of cpu is architecture Behavioral of cpu is
type states is (S_INIT, S_WRITE, S_DONE); type states is (S_WRITE1, S_WRITE2, S_FLUSH1, S_FLUSH2, S_DONE);
signal state : states := S_INIT; signal state : states := S_WRITE1;
signal enable_vga_i : std_logic := '0';
signal x : integer range 0 to 639 := 0; signal x : integer range 0 to 639 := 0;
signal y : integer range 0 to 480 := 0; signal y : integer range 0 to 479 := 0;
signal adr : integer range 0 to 153600 := 0; signal adr : integer range 0 to 153599 := 0;
constant base_adr : integer := 67108864;
signal burst_ctr : integer range 0 to burst_length := 0; constant cc_adr : integer := 134217728;
begin begin
fill_fb : process(clk) fill_fb : process(clk_i)
begin begin
if rising_edge(clk) then if rising_edge(clk_i) then
if rst = '1' then if rst_i = '1' then
enable_vga_i <= '0';
x <= 0; x <= 0;
y <= 0; y <= 0;
adr <= 0; adr <= 0;
cpu_wbm_o.stb_o <= '0'; wbm_o.stb_o <= '0';
cpu_wbm_o.cyc_o <= '0'; wbm_o.cyc_o <= '0';
state <= S_INIT; state <= S_WRITE1;
else else
case state is case state is
when S_INIT => when S_WRITE1 =>
cpu_wbm_o.stb_o <= '1'; wbm_o.stb_o <= '1';
cpu_wbm_o.cyc_o <= '1'; wbm_o.cyc_o <= '1';
cpu_wbm_o.cti_o <= "010"; -- wbm_o.cti_o <= "000";
cpu_wbm_o.bte_o <= "00"; -- wbm_o.bte_o <= "00";
cpu_wbm_o.we_o <= '1'; wbm_o.we_o <= '1';
cpu_wbm_o.sel_o <= (others => '1'); wbm_o.sel_o <= (others => '1');
cpu_wbm_o.adr_o <= std_logic_vector(to_unsigned(adr*4,cpu_wbm_o.adr_o'length)); wbm_o.adr_o <= std_logic_vector(to_unsigned(base_adr+adr*4,wbm_o.adr_o'length));
-- draw a 1px white border around a black screen -- draw a 1px white border around a black screen
if y = 0 or y = 479 then if y = 0 or y = 479 then
cpu_wbm_o.dat_o <= x"ffffffff"; wbm_o.dat_o <= x"0fff0fff";
elsif x = 0 then elsif x = 0 then
cpu_wbm_o.dat_o <= x"ffff0000"; wbm_o.dat_o <= x"00000fff";
elsif x = 639 then elsif x = 638 then
cpu_wbm_o.dat_o <= x"0000ffff"; wbm_o.dat_o <= x"0fff0000";
else else
cpu_wbm_o.dat_o <= x"00000000"; wbm_o.dat_o <= x"00000000";
end if; end if;
burst_ctr <= 0;
adr <= adr + 1; state <= S_WRITE2;
x <= x + 1; when S_WRITE2 =>
state <= S_WRITE; wbm_o.stb_o <= '1';
when S_WRITE => wbm_o.cyc_o <= '1';
if cpu_wbm_i.ack_i = '1' then
if burst_ctr = burst_length-2 then if wbm_i.ack_i = '1' then
cpu_wbm_o.cti_o <= "111"; wbm_o.stb_o <= '0';
end if; wbm_o.cyc_o <= '0';
if burst_ctr = burst_length-1 then if adr < 153599 then
cpu_wbm_o.stb_o <= '0';
cpu_wbm_o.cyc_o <= '0';
if adr = 153600 then
state <= S_DONE;
else
state <= S_INIT;
end if;
else
cpu_wbm_o.adr_o <= std_logic_vector(to_unsigned(adr*4,cpu_wbm_o.adr_o'length));
-- draw a 1px white border around a black screen
if y = 0 or y = 479 then
cpu_wbm_o.dat_o <= x"ffffffff";
elsif x = 0 then
cpu_wbm_o.dat_o <= x"ffff0000";
elsif x = 639 then
cpu_wbm_o.dat_o <= x"0000ffff";
else
cpu_wbm_o.dat_o <= x"00000000";
end if;
adr <= adr + 1; adr <= adr + 1;
if x = 639 then if x < 638 then
y <= y + 1; x <= x + 2;
x <= 0;
else else
x <= x + 1; x <= 0;
y <= y + 1;
end if; end if;
burst_ctr <= burst_ctr + 1; state <= S_WRITE1;
else
adr <= 0;
state <= S_FLUSH1;
end if;
end if;
when S_FLUSH1 =>
wbm_o.stb_o <= '1';
wbm_o.cyc_o <= '1';
-- wbm_o.cti_o <= "000";
-- wbm_o.bte_o <= "00";
wbm_o.we_o <= '1';
wbm_o.sel_o <= (others => '1');
wbm_o.adr_o <= std_logic_vector(to_unsigned(cc_adr,wbm_o.adr_o'length));
wbm_o.dat_o <= std_logic_vector(to_unsigned(adr*4,32));
state <= S_FLUSH2;
when S_FLUSH2 =>
wbm_o.stb_o <= '1';
wbm_o.cyc_o <= '1';
if wbm_i.ack_i = '1' then
wbm_o.stb_o <= '0';
wbm_o.cyc_o <= '0';
if adr < 153583 then
adr <= adr + 16;
state <= S_FLUSH1;
else
state <= S_DONE;
end if; end if;
end if; end if;
when S_DONE => when S_DONE =>
enable_vga_i <= '1'; null;
end case; end case;
end if; end if;
end if; end if;
end process fill_fb; end process fill_fb;
enable_vga <= enable_vga_i;
end Behavioral; end Behavioral;

26
src/toplevel.vhd
View File

@@ -52,7 +52,7 @@ entity toplevel is
dataflash_miso : IN std_ulogic; dataflash_miso : IN std_ulogic;
-- LEDs -- LEDs
led : OUT std_ulogic_vector(7 downto 0); -- led : OUT std_ulogic_vector(7 downto 0);
-- DDR2 SDRAM -- DDR2 SDRAM
ddr2_dq : inout std_logic_vector(15 downto 0); ddr2_dq : inout std_logic_vector(15 downto 0);
@@ -86,6 +86,9 @@ architecture Mixed of toplevel is
sysRst50 : out STD_LOGIC); sysRst50 : out STD_LOGIC);
end component; end component;
component wb_ddr_ctrl is component wb_ddr_ctrl is
generic (
dontcare : std_logic := '-'
);
Port ( Port (
-- DDR2 control -- DDR2 control
ddr2_clock : in std_ulogic; ddr2_clock : in std_ulogic;
@@ -159,7 +162,7 @@ architecture Mixed of toplevel is
hsync : out std_logic); hsync : out std_logic);
end component; end component;
component cpu_system component cpu
port ( port (
rst_i : in std_logic; rst_i : in std_logic;
clk_i : in std_logic; clk_i : in std_logic;
@@ -218,23 +221,28 @@ signal vga_mem_adr : std_logic_vector(19 downto 0);
signal vga_mem_ack : std_logic; signal vga_mem_ack : std_logic;
signal vga_mem_dat_i : std_logic_vector(63 downto 0); signal vga_mem_dat_i : std_logic_vector(63 downto 0);
signal enable_vga : std_logic; signal reset_int : std_logic;
begin begin
reset_int <= reset;
sys_clk_rst : clk_reset sys_clk_rst : clk_reset
port map ( port map (
clkIn50 => clkin_50MHz, clkIn50 => clkin_50MHz,
rstIn => reset, rstIn => reset_int,
sysClk50 => sysClk, sysClk50 => sysClk,
sysClk25 => vgaClk, sysClk25 => vgaClk,
sysRst50 => sysRst sysRst50 => sysRst
); );
ddr_ctrl0 : wb_ddr_ctrl ddr_ctrl0 : wb_ddr_ctrl
generic map (
dontcare => dontcare
)
port map ( port map (
-- DDR2 control -- DDR2 control
ddr2_clock => clkin_133MHz, ddr2_clock => clkin_133MHz,
ddr2_reset => reset, ddr2_reset => reset_int,
-- DDR2 SDRAM -- DDR2 SDRAM
ddr2_dq => ddr2_dq, ddr2_dq => ddr2_dq,
@@ -314,7 +322,7 @@ wb_rom_inst: wb_rom
wbs_i => rom_wbs_i, wbs_i => rom_wbs_i,
wbs_o => rom_wbs_o); wbs_o => rom_wbs_o);
cpu_system_inst: cpu_system cpu_system_inst: cpu
port map ( port map (
rst_i => sysRst, rst_i => sysRst,
clk_i => sysClk, clk_i => sysClk,
@@ -338,4 +346,10 @@ intercon_1: intercon
clk => sysClk, clk => sysClk,
reset => sysRst); reset => sysRst);
dataflash_mosi <= 'Z';
dataflash_sck <= 'Z';
dataflash_ss <= 'Z';
dataflash_wp <= 'Z';
dataflash_rst <= 'Z';
end Mixed; end Mixed;

87
src/wb_ddr_ctrl.vhd
View File

@@ -36,43 +36,46 @@ use IEEE.STD_LOGIC_1164.ALL;
use work.intercon_package.all; use work.intercon_package.all;
entity wb_ddr_ctrl is entity wb_ddr_ctrl is
Port ( generic (
-- DDR2 control dontcare : std_logic := '-'
ddr2_clock : in std_ulogic; );
ddr2_reset : in std_ulogic; Port (
-- DDR2 control
-- DDR2 SDRAM ddr2_clock : in std_ulogic;
ddr2_dq : inout std_logic_vector(15 downto 0); ddr2_reset : in std_ulogic;
ddr2_a : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(1 downto 0); -- DDR2 SDRAM
ddr2_cke : out std_logic; ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_cs_n : out std_logic; ddr2_a : out std_logic_vector(12 downto 0);
ddr2_ras_n : out std_logic; ddr2_ba : out std_logic_vector(1 downto 0);
ddr2_cas_n : out std_logic; ddr2_cke : out std_logic;
ddr2_we_n : out std_logic; ddr2_cs_n : out std_logic;
ddr2_odt : out std_logic; ddr2_ras_n : out std_logic;
ddr2_dm : out std_logic_vector(1 downto 0); ddr2_cas_n : out std_logic;
rst_dqs_div_in : in std_logic; ddr2_we_n : out std_logic;
rst_dqs_div_out : out std_logic; ddr2_odt : out std_logic;
ddr2_dqs : inout std_logic_vector(1 downto 0); ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0); rst_dqs_div_in : in std_logic;
ddr2_ck : out std_logic_vector(0 downto 0); rst_dqs_div_out : out std_logic;
ddr2_ck_n : out std_logic_vector(0 downto 0); ddr2_dqs : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
-- Wishbone slave ddr2_ck : out std_logic_vector(0 downto 0);
clk_i : in std_ulogic; ddr2_ck_n : out std_logic_vector(0 downto 0);
rst_i : in std_ulogic;
wbs_i : in sdram_ctrl_wbs_i_type; -- Wishbone slave
wbs_o : out sdram_ctrl_wbs_o_type; clk_i : in std_ulogic;
wbs_cc_i : in sdram_ctrl_cc_wbs_i_type; rst_i : in std_ulogic;
wbs_cc_o : out sdram_ctrl_cc_wbs_o_type; wbs_i : in sdram_ctrl_wbs_i_type;
wbs_o : out sdram_ctrl_wbs_o_type;
wbs_cc_i : in sdram_ctrl_cc_wbs_i_type;
wbs_cc_o : out sdram_ctrl_cc_wbs_o_type;
-- Direct memctrl access for VGA -- Direct memctrl access for VGA
vga_mem_rdrq : in std_logic; vga_mem_rdrq : in std_logic;
vga_mem_adr : in std_logic_vector(19 downto 0); vga_mem_adr : in std_logic_vector(19 downto 0);
vga_mem_ack : out std_logic; vga_mem_ack : out std_logic;
vga_mem_dat_i : out std_logic_vector(63 downto 0) vga_mem_dat_i : out std_logic_vector(63 downto 0)
); );
end wb_ddr_ctrl; end wb_ddr_ctrl;
architecture Behavioral of wb_ddr_ctrl is architecture Behavioral of wb_ddr_ctrl is
@@ -116,16 +119,21 @@ component wb_ddr_ctrl_ddrwrap is
-- Clock out -- Clock out
ddr2_clk0 : out std_ulogic; ddr2_clk0 : out std_ulogic;
ddr2_clk90 : out std_ulogic; ddr2_clk90 : out std_ulogic;
ddr2_clk180 : out std_logic;
ddr2_rst0 : out std_ulogic ddr2_rst0 : out std_ulogic
); );
end component; end component;
component wb_ddr_ctrl_wb is component wb_ddr_ctrl_wb is
generic (
dontcare : std_logic := '-'
);
Port ( Port (
-- Control signals -- Control signals
ddr2_clk0 : in std_ulogic; ddr2_clk0 : in std_ulogic;
ddr2_clk90 : in std_ulogic; ddr2_clk90 : in std_ulogic;
ddr2_clk180 : in std_logic;
ddr2_reset : in std_ulogic; ddr2_reset : in std_ulogic;
-- to DDR2 controller -- to DDR2 controller
@@ -157,7 +165,7 @@ component wb_ddr_ctrl_wb is
); );
end component; end component;
signal ddr2_clk0, ddr2_clk90 : std_ulogic; signal ddr2_clk0, ddr2_clk90, ddr2_clk180 : std_ulogic;
signal ddr2_rst0 : std_ulogic; signal ddr2_rst0 : std_ulogic;
signal ctrl_input_data : std_logic_vector(31 downto 0); signal ctrl_input_data : std_logic_vector(31 downto 0);
signal ctrl_data_mask : std_logic_vector(3 downto 0); signal ctrl_data_mask : std_logic_vector(3 downto 0);
@@ -192,6 +200,7 @@ ddr_0 : wb_ddr_ctrl_ddrwrap
ddr2_clk0 => ddr2_clk0, ddr2_clk0 => ddr2_clk0,
ddr2_clk90 => ddr2_clk90, ddr2_clk90 => ddr2_clk90,
ddr2_clk180 => ddr2_clk180,
ddr2_rst0 => ddr2_rst0, ddr2_rst0 => ddr2_rst0,
@@ -209,12 +218,16 @@ ddr_0 : wb_ddr_ctrl_ddrwrap
); );
wb_0 : wb_ddr_ctrl_wb wb_0 : wb_ddr_ctrl_wb
generic map (
dontcare => dontcare
)
port map ( port map (
clk_i => clk_i, clk_i => clk_i,
rst_i => rst_i, rst_i => rst_i,
ddr2_clk0 => ddr2_clk0, ddr2_clk0 => ddr2_clk0,
ddr2_clk90 => ddr2_clk90, ddr2_clk90 => ddr2_clk90,
ddr2_clk180 => ddr2_clk180,
ddr2_reset => ddr2_rst0, ddr2_reset => ddr2_rst0,
ctrl_input_data => ctrl_input_data, ctrl_input_data => ctrl_input_data,

6
src/wb_ddr_ctrl_ddrwrap.vhd
View File

@@ -73,6 +73,7 @@ entity wb_ddr_ctrl_ddrwrap is
-- Clock out -- Clock out
ddr2_clk0 : out std_ulogic; ddr2_clk0 : out std_ulogic;
ddr2_clk90 : out std_ulogic; ddr2_clk90 : out std_ulogic;
ddr2_clk180 : out std_logic;
ddr2_rst0 : out std_ulogic ddr2_rst0 : out std_ulogic
); );
end wb_ddr_ctrl_ddrwrap; end wb_ddr_ctrl_ddrwrap;
@@ -89,6 +90,7 @@ component vhdl_bl4_infrastructure_top is
sys_rst90_val : out std_logic; sys_rst90_val : out std_logic;
clk_int_val : out std_logic; clk_int_val : out std_logic;
clk90_int_val : out std_logic; clk90_int_val : out std_logic;
clk180_int_val : out std_logic;
sys_rst180_val : out std_logic; sys_rst180_val : out std_logic;
wait_200us : out std_logic; wait_200us : out std_logic;
-- debug signals -- debug signals
@@ -156,7 +158,7 @@ component vhdl_bl4_top_0 is
end component; end component;
signal ddr2_rst0_int, ddr2_rst90, ddr2_rst180 : std_logic; signal ddr2_rst0_int, ddr2_rst90, ddr2_rst180 : std_logic;
signal ddr2_clk0_int, ddr2_clk90_int : std_logic; signal ddr2_clk0_int, ddr2_clk90_int, ddr2_clk180_int : std_logic;
signal wait_200us : std_logic; signal wait_200us : std_logic;
signal delay_sel : std_logic_vector(4 downto 0); signal delay_sel : std_logic_vector(4 downto 0);
begin begin
@@ -173,6 +175,7 @@ infrastructure_0 : vhdl_bl4_infrastructure_top
sys_rst180_val => ddr2_rst180, sys_rst180_val => ddr2_rst180,
clk_int_val => ddr2_clk0_int, clk_int_val => ddr2_clk0_int,
clk90_int_val => ddr2_clk90_int, clk90_int_val => ddr2_clk90_int,
clk180_int_val => ddr2_clk180_int,
wait_200us => wait_200us, wait_200us => wait_200us,
-- debug signals -- debug signals
dbg_phase_cnt => open, dbg_phase_cnt => open,
@@ -233,6 +236,7 @@ top_0 : vhdl_bl4_top_0
ddr2_clk0 <= ddr2_clk0_int; ddr2_clk0 <= ddr2_clk0_int;
ddr2_clk90 <= ddr2_clk90_int; ddr2_clk90 <= ddr2_clk90_int;
ddr2_clk180 <= ddr2_clk180_int;
ddr2_rst0 <= ddr2_rst0_int; ddr2_rst0 <= ddr2_rst0_int;

180
src/wb_ddr_ctrl_wb.vhd
View File

@@ -34,39 +34,43 @@ use IEEE.STD_LOGIC_1164.ALL;
use work.intercon_package.all; use work.intercon_package.all;
entity wb_ddr_ctrl_wb is entity wb_ddr_ctrl_wb is
Port ( generic (
-- Control signals dontcare : std_logic := '-'
ddr2_clk0 : in std_ulogic; );
ddr2_clk90 : in std_ulogic; Port (
ddr2_reset : in std_ulogic; -- Control signals
ddr2_clk0 : in std_ulogic;
-- to DDR2 controller ddr2_clk90 : in std_ulogic;
ctrl_input_data : out std_logic_vector(31 downto 0); ddr2_clk180 : in std_logic;
ctrl_data_mask : out std_logic_vector(3 downto 0); ddr2_reset : in std_ulogic;
ctrl_output_data : in std_logic_vector(31 downto 0) := (others => 'Z');
ctrl_data_valid : in std_logic; -- to DDR2 controller
ctrl_input_address : out std_logic_vector(((13 + 10 + 2)-1) downto 0); ctrl_input_data : out std_logic_vector(31 downto 0);
ctrl_command_register : out std_logic_vector(2 downto 0); ctrl_data_mask : out std_logic_vector(3 downto 0);
ctrl_burst_done : out std_logic; ctrl_output_data : in std_logic_vector(31 downto 0) := (others => 'Z');
ctrl_auto_ref_req : in std_logic; ctrl_data_valid : in std_logic;
ctrl_cmd_ack : in std_logic; ctrl_input_address : out std_logic_vector(((13 + 10 + 2)-1) downto 0);
ctrl_init_done : in std_logic; ctrl_command_register : out std_logic_vector(2 downto 0);
ctrl_ar_done : in std_logic; ctrl_burst_done : out std_logic;
ctrl_auto_ref_req : in std_logic;
-- Wishbone slave ctrl_cmd_ack : in std_logic;
clk_i : in std_ulogic; ctrl_init_done : in std_logic;
rst_i : in std_ulogic; ctrl_ar_done : in std_logic;
wbs_i : in sdram_ctrl_wbs_i_type;
wbs_o : out sdram_ctrl_wbs_o_type; -- Wishbone slave
wbs_cc_i : in sdram_ctrl_cc_wbs_i_type; clk_i : in std_ulogic;
wbs_cc_o : out sdram_ctrl_cc_wbs_o_type; rst_i : in std_ulogic;
wbs_i : in sdram_ctrl_wbs_i_type;
wbs_o : out sdram_ctrl_wbs_o_type;
wbs_cc_i : in sdram_ctrl_cc_wbs_i_type;
wbs_cc_o : out sdram_ctrl_cc_wbs_o_type;
-- Direct memctrl access for VGA -- Direct memctrl access for VGA
vga_mem_rdrq : in std_logic; vga_mem_rdrq : in std_logic;
vga_mem_adr : in std_logic_vector(19 downto 0); vga_mem_adr : in std_logic_vector(19 downto 0);
vga_mem_ack : out std_logic; vga_mem_ack : out std_logic;
vga_mem_dat_i : out std_logic_vector(63 downto 0) vga_mem_dat_i : out std_logic_vector(63 downto 0)
); );
end wb_ddr_ctrl_wb; end wb_ddr_ctrl_wb;
architecture Behavioral of wb_ddr_ctrl_wb is architecture Behavioral of wb_ddr_ctrl_wb is
@@ -97,33 +101,36 @@ component wb_ddr_ctrl_wb_to_ddr IS
); );
END component; END component;
component wb_ddr_ctrl_wb_sc is component wb_ddr_ctrl_wb_sc is
Port ( generic (
-- Wishbone slave dontcare : std_logic := '-'
clk_i : in std_ulogic; );
rst_i : in std_ulogic; Port (
wbs_i : in sdram_ctrl_wbs_i_type; -- Wishbone slave
wbs_o : out sdram_ctrl_wbs_o_type; clk_i : in std_ulogic;
wbs_cc_i : in sdram_ctrl_cc_wbs_i_type; rst_i : in std_ulogic;
wbs_cc_o : out sdram_ctrl_cc_wbs_o_type; wbs_i : in sdram_ctrl_wbs_i_type;
wbs_o : out sdram_ctrl_wbs_o_type;
wbs_cc_i : in sdram_ctrl_cc_wbs_i_type;
wbs_cc_o : out sdram_ctrl_cc_wbs_o_type;
-- Direct memctrl access for VGA -- Direct memctrl access for VGA
vga_mem_rdrq : in std_logic; vga_mem_rdrq : in std_logic;
vga_mem_adr : in std_logic_vector(19 downto 0); vga_mem_adr : in std_logic_vector(19 downto 0);
vga_mem_ack : out std_logic; vga_mem_ack : out std_logic;
vga_mem_dat_i : out std_logic_vector(63 downto 0); vga_mem_dat_i : out std_logic_vector(63 downto 0);
-- To/from ddr clock domain -- To/from ddr clock domain
ddr_din : out std_logic_vector(63 downto 0); ddr_din : out std_logic_vector(63 downto 0);
ddr_dout : in std_logic_vector(63 downto 0); ddr_dout : in std_logic_vector(63 downto 0);
ddr_adr : out std_logic_vector(22 downto 0); ddr_adr : out std_logic_vector(22 downto 0);
ddr_we : out std_ulogic; ddr_we : out std_ulogic;
ddr_be : out std_logic_vector(7 downto 0); ddr_be : out std_logic_vector(7 downto 0);
fifo_to_ddr_write : out std_ulogic; fifo_to_ddr_write : out std_ulogic;
fifo_from_ddr_read : out std_ulogic; fifo_from_ddr_read : out std_ulogic;
fifo_to_ddr_full : in std_ulogic; fifo_to_ddr_full : in std_ulogic;
fifo_from_ddr_empty : in std_ulogic fifo_from_ddr_empty : in std_ulogic
); );
end component; end component;
component wb_ddr_ctrl_wb_dc is component wb_ddr_ctrl_wb_dc is
Port ( Port (
@@ -170,39 +177,38 @@ signal d2s_fifo_din : std_ulogic_vector(63 downto 0);
signal s2d_fifo_dout : std_logic_vector(95 downto 0); signal s2d_fifo_dout : std_logic_vector(95 downto 0);
signal d2s_fifo_dout : std_logic_vector(63 downto 0); signal d2s_fifo_dout : std_logic_vector(63 downto 0);
signal ddr2_clk180 : std_ulogic;
begin begin
ddr2_clk180 <= not ddr2_clk0;
system_cd_inst : wb_ddr_ctrl_wb_sc system_cd_inst : wb_ddr_ctrl_wb_sc
port map ( generic map (
-- Wishbone slave dontcare => dontcare
clk_i => clk_i, )
rst_i => rst_i, port map (
wbs_i => wbs_i, -- Wishbone slave
wbs_o => wbs_o, clk_i => clk_i,
wbs_cc_i => wbs_cc_i, rst_i => rst_i,
wbs_cc_o => wbs_cc_o, wbs_i => wbs_i,
wbs_o => wbs_o,
wbs_cc_i => wbs_cc_i,
wbs_cc_o => wbs_cc_o,
vga_mem_rdrq => vga_mem_rdrq, vga_mem_rdrq => vga_mem_rdrq,
vga_mem_adr => vga_mem_adr, vga_mem_adr => vga_mem_adr,
vga_mem_ack => vga_mem_ack, vga_mem_ack => vga_mem_ack,
vga_mem_dat_i => vga_mem_dat_i, vga_mem_dat_i => vga_mem_dat_i,
-- To/from ddr clock domain -- To/from ddr clock domain
ddr_din => s2d_fifo_din(63 downto 0), ddr_din => s2d_fifo_din(63 downto 0),
ddr_dout => d2s_fifo_dout, ddr_dout => d2s_fifo_dout,
ddr_adr => s2d_fifo_din(86 downto 64), ddr_adr => s2d_fifo_din(86 downto 64),
ddr_we => s2d_fifo_din(87), ddr_we => s2d_fifo_din(87),
ddr_be => s2d_fifo_din(95 downto 88), ddr_be => s2d_fifo_din(95 downto 88),
fifo_to_ddr_write => s2d_fifo_wr, fifo_to_ddr_write => s2d_fifo_wr,
fifo_from_ddr_read => d2s_fifo_rd, fifo_from_ddr_read => d2s_fifo_rd,
fifo_to_ddr_full => s2d_fifo_full, fifo_to_ddr_full => s2d_fifo_full,
fifo_from_ddr_empty => d2s_fifo_empty fifo_from_ddr_empty => d2s_fifo_empty
); );
s2d_fifo : wb_ddr_ctrl_wb_to_ddr s2d_fifo : wb_ddr_ctrl_wb_to_ddr
port map ( port map (

1
src/wb_ddr_ctrl_wb_dc_fsm.vhd
View File

@@ -115,6 +115,7 @@ ctrl_fsm_state : process(ddr2_clk180)
when S_IDLE => when S_IDLE =>
if ctrl_auto_ref_req = '1' then -- DDR controller requests refresh if ctrl_auto_ref_req = '1' then -- DDR controller requests refresh
ctrl_state <= S_REFRESH; ctrl_state <= S_REFRESH;
fifo_pending <= fifo_from_sys_valid;
elsif fifo_from_sys_valid = '1' then -- A request from the system is pending elsif fifo_from_sys_valid = '1' then -- A request from the system is pending
ctrl_state <= S_REQUEST_INIT; ctrl_state <= S_REQUEST_INIT;
end if; -- else do nothing end if; -- else do nothing

9
src/wb_ddr_ctrl_wb_sc.vhd
View File

@@ -77,7 +77,8 @@ architecture Behavioral of wb_ddr_ctrl_wb_sc is
line_size_ln2 : integer; line_size_ln2 : integer;
lines_ln2 : integer; lines_ln2 : integer;
assoc_ln2 : integer; assoc_ln2 : integer;
addr_width : integer); addr_width : integer;
dontcare : std_logic);
port ( port (
clk_i : in std_logic; clk_i : in std_logic;
rst_i : in std_logic; rst_i : in std_logic;
@@ -139,7 +140,8 @@ begin
line_size_ln2 => burst_length_ln2, line_size_ln2 => burst_length_ln2,
lines_ln2 => 6, lines_ln2 => 6,
assoc_ln2 => 1, assoc_ln2 => 1,
addr_width => 23 addr_width => 23,
dontcare => dontcare
) )
port map ( port map (
clk_i => clk_i, clk_i => clk_i,
@@ -165,7 +167,7 @@ begin
fifo_from_ddr_read <= not fifo_from_ddr_empty; fifo_from_ddr_read <= not fifo_from_ddr_empty;
ddr_be <= (others => '1'); ddr_be <= (others => '0');
ddr_din <= cfe_mem_dat_o; ddr_din <= cfe_mem_dat_o;
ddr_adr_int(22 downto 3) <= vga_adr_reg when bus_owner = B_VGA else ddr_adr_int(22 downto 3) <= vga_adr_reg when bus_owner = B_VGA else
cfe_adr_reg when bus_owner = B_CFE else cfe_adr_reg when bus_owner = B_CFE else
@@ -208,6 +210,7 @@ begin
end if; end if;
else else
fifo_to_ddr_write_dly <= (others => '0'); fifo_to_ddr_write_dly <= (others => '0');
out_complete_dly <= (others => '0');
end if; end if;
end if; end if;
end process write_dly; end process write_dly;

31
src/wb_ddr_ctrl_wb_sc_fe.vhd
View File

@@ -51,7 +51,8 @@ entity wb_ddr_ctrl_wb_sc_fe is
line_size_ln2 : integer := 3; line_size_ln2 : integer := 3;
lines_ln2 : integer := 6; lines_ln2 : integer := 6;
assoc_ln2 : integer := 1; assoc_ln2 : integer := 1;
addr_width : integer := 23 addr_width : integer := 23;
dontcare : std_logic := '-'
); );
port ( port (
-- Wishbone slave -- Wishbone slave
@@ -144,20 +145,20 @@ architecture Behavioral of wb_ddr_ctrl_wb_sc_fe is
type cc_lru_a is array(lines/assoc-1 downto 0) of lru_t; type cc_lru_a is array(lines/assoc-1 downto 0) of lru_t;
type cc_valid_a is array(lines/assoc-1 downto 0) of std_logic_vector(assoc-1 downto 0); type cc_valid_a is array(lines/assoc-1 downto 0) of std_logic_vector(assoc-1 downto 0);
type cc_dirty_a is array(lines/assoc-1 downto 0) of std_logic_vector(assoc-1 downto 0); type cc_dirty_a is array(lines/assoc-1 downto 0) of std_logic_vector(assoc-1 downto 0);
signal cc_tag : cc_tag_a := (others => (others => '-')); signal cc_tag : cc_tag_a := (others => (others => dontcare));
signal cc_lru : cc_lru_a := (others => (others => '-')); signal cc_lru : cc_lru_a := (others => (others => dontcare));
signal cc_valid : cc_valid_a := (others => (others => '0')); signal cc_valid : cc_valid_a := (others => (others => '0'));
signal cc_dirty : cc_dirty_a := (others => (others => '-')); signal cc_dirty : cc_dirty_a := (others => (others => dontcare));
attribute ram_style of cc_tag : signal is "block"; attribute ram_style of cc_tag : signal is "block";
attribute ram_style of cc_lru : signal is "auto"; attribute ram_style of cc_lru : signal is "auto";
attribute ram_style of cc_valid : signal is "auto"; attribute ram_style of cc_valid : signal is "auto";
attribute ram_style of cc_dirty : signal is "auto"; attribute ram_style of cc_dirty : signal is "auto";
signal cc_we : std_logic := '0'; signal cc_we : std_logic := '0';
signal cc_wr_addr, cc_rd_addr : unsigned(lines_ln2-assoc_ln2-1 downto 0) := (others => '-'); signal cc_wr_addr, cc_rd_addr : unsigned(lines_ln2-assoc_ln2-1 downto 0) := (others => dontcare);
signal cc_tag_wr_data, cc_tag_rd_data : tag_t := (others => '-'); signal cc_tag_wr_data, cc_tag_rd_data : tag_t := (others => dontcare);
signal cc_lru_wr_data, cc_lru_rd_data : lru_t := (others => '-'); signal cc_lru_wr_data, cc_lru_rd_data : lru_t := (others => dontcare);
signal cc_valid_wr_data, cc_valid_rd_data : std_logic_vector(assoc-1 downto 0) := (others => '0'); signal cc_valid_wr_data, cc_valid_rd_data : std_logic_vector(assoc-1 downto 0) := (others => '0');
signal cc_dirty_wr_data, cc_dirty_rd_data : std_logic_vector(assoc-1 downto 0) := (others => '-'); signal cc_dirty_wr_data, cc_dirty_rd_data : std_logic_vector(assoc-1 downto 0) := (others => dontcare);
-- Convenience variable for cc_tag_rd_data -- Convenience variable for cc_tag_rd_data
type tag_a is array(assoc-1 downto 0) of std_logic_vector(tag_width-1 downto 0); type tag_a is array(assoc-1 downto 0) of std_logic_vector(tag_width-1 downto 0);
@@ -166,8 +167,8 @@ architecture Behavioral of wb_ddr_ctrl_wb_sc_fe is
-- Cache data signals / memory -- Cache data signals / memory
-- signal cache_we : std_logic := '0'; -- signal cache_we : std_logic := '0';
signal cache_wr_addr, cache_rd_addr : unsigned(lines_ln2+line_size_ln2-1 downto 0) := (others => '0'); signal cache_wr_addr, cache_rd_addr : unsigned(lines_ln2+line_size_ln2-1 downto 0) := (others => '0');
signal cache_wr_data, cache_rd_data : std_logic_vector(63 downto 0) := (others => '-'); signal cache_wr_data, cache_rd_data : std_logic_vector(63 downto 0) := (others => dontcare);
signal cache_bwe : std_logic_vector(7 downto 0) := (others => '-'); signal cache_bwe : std_logic_vector(7 downto 0) := (others => dontcare);
-- Convenience variables for adr_i -- Convenience variables for adr_i
@@ -201,7 +202,7 @@ begin
adr_index & eject_num & mem_offset; adr_index & eject_num & mem_offset;
cache_wr_data <= wbs_i.dat_i & wbs_i.dat_i when cache_write = '1' else cache_wr_data <= wbs_i.dat_i & wbs_i.dat_i when cache_write = '1' else
mem_dat_i when cache_from_mem = '1' else mem_dat_i when cache_from_mem = '1' else
(others => '-'); (others => dontcare);
cache_bwe <= "0000" & wbs_i.sel_i when cache_write = '1' and wbs_i.adr_i(2) = '0' else cache_bwe <= "0000" & wbs_i.sel_i when cache_write = '1' and wbs_i.adr_i(2) = '0' else
wbs_i.sel_i & "0000" when cache_write = '1' and wbs_i.adr_i(2) = '1' else wbs_i.sel_i & "0000" when cache_write = '1' and wbs_i.adr_i(2) = '1' else
"11111111" when cache_from_mem = '1' and mem_ack = '1' else "11111111" when cache_from_mem = '1' and mem_ack = '1' else
@@ -227,7 +228,7 @@ begin
mem_adr <= adr_tag & std_logic_vector(adr_index) when cache_from_mem = '1' else mem_adr <= adr_tag & std_logic_vector(adr_index) when cache_from_mem = '1' else
tags(to_integer(eject_num)) & std_logic_vector(adr_index) when cache_to_mem = '1' else tags(to_integer(eject_num)) & std_logic_vector(adr_index) when cache_to_mem = '1' else
(others => '-'); (others => dontcare);
cc_wr_data_gen : for i in 0 to assoc-1 generate cc_wr_data_gen : for i in 0 to assoc-1 generate
cc_tag_wr_data((i+1)*tag_width-1 downto i*tag_width) <= cc_tag_wr_data((i+1)*tag_width-1 downto i*tag_width) <=
@@ -252,7 +253,7 @@ begin
end generate; end generate;
cc_wr_addr <= adr_index when update_lru = '1' or set_dirty = '1' or set_valid = '1' or set_invalid = '1' else cc_wr_addr <= adr_index when update_lru = '1' or set_dirty = '1' or set_valid = '1' or set_invalid = '1' else
(others => '-'); (others => dontcare);
cc_we <= update_lru or set_dirty or set_valid or set_invalid; cc_we <= update_lru or set_dirty or set_valid or set_invalid;
-- Memory for cache control -- Memory for cache control
@@ -307,7 +308,7 @@ begin
pe_assoc_2 : if assoc = 2 generate pe_assoc_2 : if assoc = 2 generate
adr_tag_eq_num <= to_unsigned(0,1) when adr_tag_eq(0) = '1' else adr_tag_eq_num <= to_unsigned(0,1) when adr_tag_eq(0) = '1' else
to_unsigned(1,1) when adr_tag_eq(1) = '1' else to_unsigned(1,1) when adr_tag_eq(1) = '1' else
(others => '-'); (others => dontcare);
eject_num <= adr_tag_eq_num when user_cc = '1' else eject_num <= adr_tag_eq_num when user_cc = '1' else
to_unsigned(0,1) when lru_eq0(0) = '1' else to_unsigned(0,1) when lru_eq0(0) = '1' else
to_unsigned(1,1) when lru_eq0(1) = '1' else to_unsigned(1,1) when lru_eq0(1) = '1' else
@@ -318,7 +319,7 @@ begin
to_unsigned(1,2) when adr_tag_eq(1) = '1' else to_unsigned(1,2) when adr_tag_eq(1) = '1' else
to_unsigned(2,2) when adr_tag_eq(2) = '1' else to_unsigned(2,2) when adr_tag_eq(2) = '1' else
to_unsigned(3,2) when adr_tag_eq(3) = '1' else to_unsigned(3,2) when adr_tag_eq(3) = '1' else
(others => '-'); (others => dontcare);
eject_num <= adr_tag_eq_num when user_cc = '1' else eject_num <= adr_tag_eq_num when user_cc = '1' else
to_unsigned(0,2) when lru_eq0(0) = '1' else to_unsigned(0,2) when lru_eq0(0) = '1' else
to_unsigned(1,2) when lru_eq0(1) = '1' else to_unsigned(1,2) when lru_eq0(1) = '1' else

9
tb/toplevel_tb.vhd
View File

@@ -6,7 +6,7 @@
-- Author : <Matthias@MATTHIAS-PC> -- Author : <Matthias@MATTHIAS-PC>
-- Company : -- Company :
-- Created : 2013-03-02 -- Created : 2013-03-02
-- Last update: 2013-03-08 -- Last update: 2013-03-09
-- Platform : -- Platform :
-- Standard : VHDL'87 -- Standard : VHDL'87
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
@@ -34,6 +34,9 @@ end toplevel_tb;
architecture testbench of toplevel_tb is architecture testbench of toplevel_tb is
component toplevel component toplevel
generic (
dontcare : std_logic
);
port ( port (
clkin_50MHz : IN std_ulogic; clkin_50MHz : IN std_ulogic;
clkin_133MHz : IN std_ulogic; clkin_133MHz : IN std_ulogic;
@@ -81,6 +84,7 @@ architecture testbench of toplevel_tb is
); );
end component; end component;
constant dontcare : std_logic := '0';
-- component ports -- component ports
signal clkin_50MHz : std_ulogic := '0'; signal clkin_50MHz : std_ulogic := '0';
@@ -114,6 +118,9 @@ begin -- testbench
-- component instantiation -- component instantiation
DUT: toplevel DUT: toplevel
generic map (
dontcare => dontcare
)
port map ( port map (
clkin_50MHz => clkin_50MHz, clkin_50MHz => clkin_50MHz,
clkin_133MHz => clkin_133MHz, clkin_133MHz => clkin_133MHz,

825
toplevel_tb.wcfg
View File

@@ -7,6 +7,7 @@
<top_modules> <top_modules>
<top_module name="intercon_package" /> <top_module name="intercon_package" />
<top_module name="numeric_std" /> <top_module name="numeric_std" />
<top_module name="sim_bmppack" />
<top_module name="std_logic_1164" /> <top_module name="std_logic_1164" />
<top_module name="std_logic_arith" /> <top_module name="std_logic_arith" />
<top_module name="std_logic_unsigned" /> <top_module name="std_logic_unsigned" />
@@ -21,7 +22,7 @@
</top_modules> </top_modules>
</db_ref> </db_ref>
</db_ref_list> </db_ref_list>
<WVObjectSize size="40" /> <WVObjectSize size="45" />
<wvobject fp_name="/toplevel_tb/DUT/clkin_50mhz" type="logic" db_ref_id="1"> <wvobject fp_name="/toplevel_tb/DUT/clkin_50mhz" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clkin_50mhz</obj_property> <obj_property name="ElementShortName">clkin_50mhz</obj_property>
<obj_property name="ObjectShortName">clkin_50mhz</obj_property> <obj_property name="ObjectShortName">clkin_50mhz</obj_property>
@@ -158,47 +159,23 @@
<obj_property name="ElementShortName">sysrst</obj_property> <obj_property name="ElementShortName">sysrst</obj_property>
<obj_property name="ObjectShortName">sysrst</obj_property> <obj_property name="ObjectShortName">sysrst</obj_property>
</wvobject> </wvobject>
<wvobject fp_name="/toplevel_tb/DUT/vga_wbm_i" type="array" db_ref_id="1"> <wvobject fp_name="/toplevel_tb/DUT/vga_mem_rdrq" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">vga_wbm_i</obj_property> <obj_property name="ElementShortName">vga_mem_rdrq</obj_property>
<obj_property name="ObjectShortName">vga_wbm_i</obj_property> <obj_property name="ObjectShortName">vga_mem_rdrq</obj_property>
<wvobject fp_name="/toplevel_tb/DUT/vga_wbm_i.dat_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">.dat_i</obj_property>
<obj_property name="ObjectShortName">vga_wbm_i.dat_i</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/vga_wbm_i.ack_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">.ack_i</obj_property>
<obj_property name="ObjectShortName">vga_wbm_i.ack_i</obj_property>
</wvobject>
</wvobject> </wvobject>
<wvobject fp_name="/toplevel_tb/DUT/vga_wbm_o" type="array" db_ref_id="1"> <wvobject fp_name="/toplevel_tb/DUT/vga_mem_adr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">vga_wbm_o</obj_property> <obj_property name="ElementShortName">vga_mem_adr[19:0]</obj_property>
<obj_property name="ObjectShortName">vga_wbm_o</obj_property> <obj_property name="ObjectShortName">vga_mem_adr[19:0]</obj_property>
<wvobject fp_name="/toplevel_tb/DUT/vga_wbm_o.sel_o" type="array" db_ref_id="1"> <obj_property name="Radix">HEXRADIX</obj_property>
<obj_property name="ElementShortName">.sel_o</obj_property> </wvobject>
<obj_property name="ObjectShortName">vga_wbm_o.sel_o</obj_property> <wvobject fp_name="/toplevel_tb/DUT/vga_mem_ack" type="logic" db_ref_id="1">
</wvobject> <obj_property name="ElementShortName">vga_mem_ack</obj_property>
<wvobject fp_name="/toplevel_tb/DUT/vga_wbm_o.adr_o" type="array" db_ref_id="1"> <obj_property name="ObjectShortName">vga_mem_ack</obj_property>
<obj_property name="ElementShortName">.adr_o</obj_property> </wvobject>
<obj_property name="ObjectShortName">vga_wbm_o.adr_o</obj_property> <wvobject fp_name="/toplevel_tb/DUT/vga_mem_dat_i" type="array" db_ref_id="1">
<obj_property name="Radix">HEXRADIX</obj_property> <obj_property name="ElementShortName">vga_mem_dat_i[63:0]</obj_property>
</wvobject> <obj_property name="ObjectShortName">vga_mem_dat_i[63:0]</obj_property>
<wvobject fp_name="/toplevel_tb/DUT/vga_wbm_o.bte_o" type="array" db_ref_id="1"> <obj_property name="Radix">HEXRADIX</obj_property>
<obj_property name="ElementShortName">.bte_o</obj_property>
<obj_property name="ObjectShortName">vga_wbm_o.bte_o</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/vga_wbm_o.cti_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">.cti_o</obj_property>
<obj_property name="ObjectShortName">vga_wbm_o.cti_o</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/vga_wbm_o.cyc_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">.cyc_o</obj_property>
<obj_property name="ObjectShortName">vga_wbm_o.cyc_o</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/vga_wbm_o.stb_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">.stb_o</obj_property>
<obj_property name="ObjectShortName">vga_wbm_o.stb_o</obj_property>
</wvobject>
</wvobject> </wvobject>
<wvobject fp_name="/toplevel_tb/DUT/cpu_wbm_o" type="array" db_ref_id="1"> <wvobject fp_name="/toplevel_tb/DUT/cpu_wbm_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cpu_wbm_o</obj_property> <obj_property name="ElementShortName">cpu_wbm_o</obj_property>
@@ -258,121 +235,743 @@
<wvobject fp_name="group68" type="group"> <wvobject fp_name="group68" type="group">
<obj_property name="label">cpu_1</obj_property> <obj_property name="label">cpu_1</obj_property>
<obj_property name="DisplayName">label</obj_property> <obj_property name="DisplayName">label</obj_property>
<wvobject fp_name="/toplevel_tb/DUT/cpu_1/enable_vga" type="logic" db_ref_id="1"> <wvobject fp_name="/toplevel_tb/DUT/cpu_system_inst/clk_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">enable_vga</obj_property> <obj_property name="ElementShortName">clk_i</obj_property>
<obj_property name="ObjectShortName">enable_vga</obj_property> <obj_property name="ObjectShortName">clk_i</obj_property>
</wvobject> </wvobject>
<wvobject fp_name="/toplevel_tb/DUT/cpu_1/cpu_wbm_i" type="array" db_ref_id="1"> <wvobject fp_name="/toplevel_tb/DUT/cpu_system_inst/rst_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">cpu_wbm_i</obj_property> <obj_property name="ElementShortName">rst_i</obj_property>
<obj_property name="ObjectShortName">cpu_wbm_i</obj_property> <obj_property name="ObjectShortName">rst_i</obj_property>
</wvobject> </wvobject>
<wvobject fp_name="/toplevel_tb/DUT/cpu_1/cpu_wbm_o" type="array" db_ref_id="1"> <wvobject fp_name="/toplevel_tb/DUT/cpu_system_inst/wbm_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cpu_wbm_o</obj_property> <obj_property name="ElementShortName">wbm_i</obj_property>
<obj_property name="ObjectShortName">cpu_wbm_o</obj_property> <obj_property name="ObjectShortName">wbm_i</obj_property>
<wvobject fp_name="/toplevel_tb/DUT/cpu_1/cpu_wbm_o.dat_o" type="array" db_ref_id="1"> <wvobject fp_name="/toplevel_tb/DUT/cpu_system_inst/wbm_i.dat_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">.dat_i</obj_property>
<obj_property name="ObjectShortName">wbm_i.dat_i</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/cpu_system_inst/wbm_i.ack_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">.ack_i</obj_property>
<obj_property name="ObjectShortName">wbm_i.ack_i</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/cpu_system_inst/wbm_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">wbm_o</obj_property>
<obj_property name="ObjectShortName">wbm_o</obj_property>
<wvobject fp_name="/toplevel_tb/DUT/cpu_system_inst/wbm_o.dat_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">.dat_o</obj_property> <obj_property name="ElementShortName">.dat_o</obj_property>
<obj_property name="ObjectShortName">cpu_wbm_o.dat_o</obj_property> <obj_property name="ObjectShortName">wbm_o.dat_o</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property> <obj_property name="Radix">HEXRADIX</obj_property>
</wvobject> </wvobject>
<wvobject fp_name="/toplevel_tb/DUT/cpu_1/cpu_wbm_o.we_o" type="logic" db_ref_id="1"> <wvobject fp_name="/toplevel_tb/DUT/cpu_system_inst/wbm_o.we_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">.we_o</obj_property> <obj_property name="ElementShortName">.we_o</obj_property>
<obj_property name="ObjectShortName">cpu_wbm_o.we_o</obj_property> <obj_property name="ObjectShortName">wbm_o.we_o</obj_property>
</wvobject> </wvobject>
<wvobject fp_name="/toplevel_tb/DUT/cpu_1/cpu_wbm_o.sel_o" type="array" db_ref_id="1"> <wvobject fp_name="/toplevel_tb/DUT/cpu_system_inst/wbm_o.sel_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">.sel_o</obj_property> <obj_property name="ElementShortName">.sel_o</obj_property>
<obj_property name="ObjectShortName">cpu_wbm_o.sel_o</obj_property> <obj_property name="ObjectShortName">wbm_o.sel_o</obj_property>
</wvobject> </wvobject>
<wvobject fp_name="/toplevel_tb/DUT/cpu_1/cpu_wbm_o.adr_o" type="array" db_ref_id="1"> <wvobject fp_name="/toplevel_tb/DUT/cpu_system_inst/wbm_o.adr_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">.adr_o</obj_property> <obj_property name="ElementShortName">.adr_o</obj_property>
<obj_property name="ObjectShortName">cpu_wbm_o.adr_o</obj_property> <obj_property name="ObjectShortName">wbm_o.adr_o</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property> <obj_property name="Radix">HEXRADIX</obj_property>
</wvobject> </wvobject>
<wvobject fp_name="/toplevel_tb/DUT/cpu_1/cpu_wbm_o.bte_o" type="array" db_ref_id="1"> <wvobject fp_name="/toplevel_tb/DUT/cpu_system_inst/wbm_o.cyc_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">.bte_o</obj_property>
<obj_property name="ObjectShortName">cpu_wbm_o.bte_o</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/cpu_1/cpu_wbm_o.cti_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">.cti_o</obj_property>
<obj_property name="ObjectShortName">cpu_wbm_o.cti_o</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/cpu_1/cpu_wbm_o.cyc_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">.cyc_o</obj_property> <obj_property name="ElementShortName">.cyc_o</obj_property>
<obj_property name="ObjectShortName">cpu_wbm_o.cyc_o</obj_property> <obj_property name="ObjectShortName">wbm_o.cyc_o</obj_property>
</wvobject> </wvobject>
<wvobject fp_name="/toplevel_tb/DUT/cpu_1/cpu_wbm_o.stb_o" type="logic" db_ref_id="1"> <wvobject fp_name="/toplevel_tb/DUT/cpu_system_inst/wbm_o.stb_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">.stb_o</obj_property> <obj_property name="ElementShortName">.stb_o</obj_property>
<obj_property name="ObjectShortName">cpu_wbm_o.stb_o</obj_property> <obj_property name="ObjectShortName">wbm_o.stb_o</obj_property>
</wvobject> </wvobject>
</wvobject> </wvobject>
<wvobject fp_name="/toplevel_tb/DUT/cpu_1/state" type="other" db_ref_id="1"> <wvobject fp_name="/toplevel_tb/DUT/cpu_system_inst/state" type="other" db_ref_id="1">
<obj_property name="ElementShortName">state</obj_property> <obj_property name="ElementShortName">state</obj_property>
<obj_property name="ObjectShortName">state</obj_property> <obj_property name="ObjectShortName">state</obj_property>
</wvobject> </wvobject>
<wvobject fp_name="/toplevel_tb/DUT/cpu_1/enable_vga_i" type="logic" db_ref_id="1"> <wvobject fp_name="/toplevel_tb/DUT/cpu_system_inst/x" type="other" db_ref_id="1">
<obj_property name="ElementShortName">enable_vga_i</obj_property>
<obj_property name="ObjectShortName">enable_vga_i</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/cpu_1/x" type="other" db_ref_id="1">
<obj_property name="ElementShortName">x</obj_property> <obj_property name="ElementShortName">x</obj_property>
<obj_property name="ObjectShortName">x</obj_property> <obj_property name="ObjectShortName">x</obj_property>
</wvobject> </wvobject>
<wvobject fp_name="/toplevel_tb/DUT/cpu_1/y" type="other" db_ref_id="1"> <wvobject fp_name="/toplevel_tb/DUT/cpu_system_inst/y" type="other" db_ref_id="1">
<obj_property name="ElementShortName">y</obj_property> <obj_property name="ElementShortName">y</obj_property>
<obj_property name="ObjectShortName">y</obj_property> <obj_property name="ObjectShortName">y</obj_property>
</wvobject> </wvobject>
<wvobject fp_name="/toplevel_tb/DUT/cpu_1/adr" type="other" db_ref_id="1"> <wvobject fp_name="/toplevel_tb/DUT/cpu_system_inst/adr" type="other" db_ref_id="1">
<obj_property name="ElementShortName">adr</obj_property> <obj_property name="ElementShortName">adr</obj_property>
<obj_property name="ObjectShortName">adr</obj_property> <obj_property name="ObjectShortName">adr</obj_property>
</wvobject> </wvobject>
<wvobject fp_name="/toplevel_tb/DUT/cpu_1/burst_ctr" type="other" db_ref_id="1">
<obj_property name="ElementShortName">burst_ctr</obj_property>
<obj_property name="ObjectShortName">burst_ctr</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/cpu_1/burst_length" type="other" db_ref_id="1">
<obj_property name="ElementShortName">burst_length</obj_property>
<obj_property name="ObjectShortName">burst_length</obj_property>
</wvobject>
</wvobject> </wvobject>
<wvobject fp_name="group86" type="group"> <wvobject fp_name="group86" type="group">
<obj_property name="label">vga_pixelgen_1</obj_property> <obj_property name="label">vga_pixelgen_1</obj_property>
<obj_property name="DisplayName">label</obj_property> <obj_property name="DisplayName">label</obj_property>
<wvobject fp_name="/toplevel_tb/DUT/vga_inst/vga_pixelgen_inst/clk" type="logic" db_ref_id="1"> <wvobject fp_name="/toplevel_tb/DUT/vga_1/vga_pixelreader_inst/clk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk</obj_property> <obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property> <obj_property name="ObjectShortName">clk</obj_property>
</wvobject> </wvobject>
<wvobject fp_name="/toplevel_tb/DUT/vga_inst/vga_pixelgen_inst/row" type="array" db_ref_id="1"> <wvobject fp_name="/toplevel_tb/DUT/vga_1/vga_pixelreader_inst/rst" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">row[9:0]</obj_property> <obj_property name="ElementShortName">rst</obj_property>
<obj_property name="ObjectShortName">row[9:0]</obj_property> <obj_property name="ObjectShortName">rst</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject> </wvobject>
<wvobject fp_name="/toplevel_tb/DUT/vga_inst/vga_pixelgen_inst/column" type="array" db_ref_id="1"> <wvobject fp_name="/toplevel_tb/DUT/vga_1/vga_pixelreader_inst/pixeldata" type="array" db_ref_id="1">
<obj_property name="ElementShortName">column[9:0]</obj_property> <obj_property name="ElementShortName">pixeldata[63:0]</obj_property>
<obj_property name="ObjectShortName">column[9:0]</obj_property> <obj_property name="ObjectShortName">pixeldata[63:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject> </wvobject>
<wvobject fp_name="/toplevel_tb/DUT/vga_inst/vga_pixelgen_inst/pixeldata" type="array" db_ref_id="1"> <wvobject fp_name="/toplevel_tb/DUT/vga_1/vga_pixelreader_inst/fifo_write" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">pixeldata[15:0]</obj_property> <obj_property name="ElementShortName">fifo_write</obj_property>
<obj_property name="ObjectShortName">pixeldata[15:0]</obj_property> <obj_property name="ObjectShortName">fifo_write</obj_property>
</wvobject> </wvobject>
<wvobject fp_name="/toplevel_tb/DUT/vga_inst/vga_pixelgen_inst/fifo_read" type="logic" db_ref_id="1"> <wvobject fp_name="/toplevel_tb/DUT/vga_1/vga_pixelreader_inst/fifo_full16" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_read</obj_property> <obj_property name="ElementShortName">fifo_full16</obj_property>
<obj_property name="ObjectShortName">fifo_read</obj_property> <obj_property name="ObjectShortName">fifo_full16</obj_property>
</wvobject> </wvobject>
<wvobject fp_name="/toplevel_tb/DUT/vga_inst/vga_pixelgen_inst/fifo_empty" type="logic" db_ref_id="1"> <wvobject fp_name="/toplevel_tb/DUT/vga_1/vga_pixelreader_inst/fifo_rst" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_empty</obj_property> <obj_property name="ElementShortName">fifo_rst</obj_property>
<obj_property name="ObjectShortName">fifo_empty</obj_property> <obj_property name="ObjectShortName">fifo_rst</obj_property>
</wvobject> </wvobject>
<wvobject fp_name="/toplevel_tb/DUT/vga_inst/vga_pixelgen_inst/red" type="array" db_ref_id="1"> <wvobject fp_name="/toplevel_tb/DUT/vga_1/vga_pixelreader_inst/vsync" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">red[3:0]</obj_property> <obj_property name="ElementShortName">vsync</obj_property>
<obj_property name="ObjectShortName">red[3:0]</obj_property> <obj_property name="ObjectShortName">vsync</obj_property>
</wvobject> </wvobject>
<wvobject fp_name="/toplevel_tb/DUT/vga_inst/vga_pixelgen_inst/green" type="array" db_ref_id="1"> <wvobject fp_name="/toplevel_tb/DUT/vga_1/vga_pixelreader_inst/mem_rdrq" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">green[3:0]</obj_property> <obj_property name="ElementShortName">mem_rdrq</obj_property>
<obj_property name="ObjectShortName">green[3:0]</obj_property> <obj_property name="ObjectShortName">mem_rdrq</obj_property>
</wvobject> </wvobject>
<wvobject fp_name="/toplevel_tb/DUT/vga_inst/vga_pixelgen_inst/blue" type="array" db_ref_id="1"> <wvobject fp_name="/toplevel_tb/DUT/vga_1/vga_pixelreader_inst/mem_adr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">blue[3:0]</obj_property> <obj_property name="ElementShortName">mem_adr[19:0]</obj_property>
<obj_property name="ObjectShortName">blue[3:0]</obj_property> <obj_property name="ObjectShortName">mem_adr[19:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/vga_1/vga_pixelreader_inst/mem_ack" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">mem_ack</obj_property>
<obj_property name="ObjectShortName">mem_ack</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/vga_1/vga_pixelreader_inst/mem_dat_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">mem_dat_i[63:0]</obj_property>
<obj_property name="ObjectShortName">mem_dat_i[63:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/vga_1/vga_pixelreader_inst/state" type="other" db_ref_id="1">
<obj_property name="ElementShortName">state</obj_property>
<obj_property name="ObjectShortName">state</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/vga_1/vga_pixelreader_inst/addr_ctr" type="other" db_ref_id="1">
<obj_property name="ElementShortName">addr_ctr</obj_property>
<obj_property name="ObjectShortName">addr_ctr</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/vga_1/vga_pixelreader_inst/burst_ctr" type="other" db_ref_id="1">
<obj_property name="ElementShortName">burst_ctr</obj_property>
<obj_property name="ObjectShortName">burst_ctr</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="group156" type="group">
<obj_property name="label">ddr_ctrl_sc</obj_property>
<obj_property name="DisplayName">label</obj_property>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/clk_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk_i</obj_property>
<obj_property name="ObjectShortName">clk_i</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/rst_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rst_i</obj_property>
<obj_property name="ObjectShortName">rst_i</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wbs_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">wbs_i</obj_property>
<obj_property name="ObjectShortName">wbs_i</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wbs_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">wbs_o</obj_property>
<obj_property name="ObjectShortName">wbs_o</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wbs_cc_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">wbs_cc_i</obj_property>
<obj_property name="ObjectShortName">wbs_cc_i</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wbs_cc_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">wbs_cc_o</obj_property>
<obj_property name="ObjectShortName">wbs_cc_o</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/vga_mem_rdrq" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">vga_mem_rdrq</obj_property>
<obj_property name="ObjectShortName">vga_mem_rdrq</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/vga_mem_adr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">vga_mem_adr[19:0]</obj_property>
<obj_property name="ObjectShortName">vga_mem_adr[19:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/vga_mem_ack" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">vga_mem_ack</obj_property>
<obj_property name="ObjectShortName">vga_mem_ack</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/vga_mem_dat_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">vga_mem_dat_i[63:0]</obj_property>
<obj_property name="ObjectShortName">vga_mem_dat_i[63:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/ddr_din" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr_din[63:0]</obj_property>
<obj_property name="ObjectShortName">ddr_din[63:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/ddr_dout" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr_dout[63:0]</obj_property>
<obj_property name="ObjectShortName">ddr_dout[63:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/ddr_adr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr_adr[22:0]</obj_property>
<obj_property name="ObjectShortName">ddr_adr[22:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/ddr_we" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr_we</obj_property>
<obj_property name="ObjectShortName">ddr_we</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/ddr_be" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr_be[7:0]</obj_property>
<obj_property name="ObjectShortName">ddr_be[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/fifo_to_ddr_write" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_to_ddr_write</obj_property>
<obj_property name="ObjectShortName">fifo_to_ddr_write</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/fifo_from_ddr_read" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_from_ddr_read</obj_property>
<obj_property name="ObjectShortName">fifo_from_ddr_read</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/fifo_to_ddr_full" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_to_ddr_full</obj_property>
<obj_property name="ObjectShortName">fifo_to_ddr_full</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/fifo_from_ddr_empty" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_from_ddr_empty</obj_property>
<obj_property name="ObjectShortName">fifo_from_ddr_empty</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/cfe_mem_adr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cfe_mem_adr[19:0]</obj_property>
<obj_property name="ObjectShortName">cfe_mem_adr[19:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/cfe_mem_rdrq" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">cfe_mem_rdrq</obj_property>
<obj_property name="ObjectShortName">cfe_mem_rdrq</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/cfe_mem_wrrq" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">cfe_mem_wrrq</obj_property>
<obj_property name="ObjectShortName">cfe_mem_wrrq</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/cfe_mem_dat_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cfe_mem_dat_o[63:0]</obj_property>
<obj_property name="ObjectShortName">cfe_mem_dat_o[63:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/cfe_mem_ack" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">cfe_mem_ack</obj_property>
<obj_property name="ObjectShortName">cfe_mem_ack</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/cfe_mem_dat_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cfe_mem_dat_i[63:0]</obj_property>
<obj_property name="ObjectShortName">cfe_mem_dat_i[63:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/vga_rdrq_reg" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">vga_rdrq_reg</obj_property>
<obj_property name="ObjectShortName">vga_rdrq_reg</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/vga_adr_reg" type="array" db_ref_id="1">
<obj_property name="ElementShortName">vga_adr_reg[19:0]</obj_property>
<obj_property name="ObjectShortName">vga_adr_reg[19:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/vga_rq_complete" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">vga_rq_complete</obj_property>
<obj_property name="ObjectShortName">vga_rq_complete</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/cfe_rdrq_reg" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">cfe_rdrq_reg</obj_property>
<obj_property name="ObjectShortName">cfe_rdrq_reg</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/cfe_wrrq_reg" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">cfe_wrrq_reg</obj_property>
<obj_property name="ObjectShortName">cfe_wrrq_reg</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/cfe_adr_reg" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cfe_adr_reg[19:0]</obj_property>
<obj_property name="ObjectShortName">cfe_adr_reg[19:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/cfe_rq_complete" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">cfe_rq_complete</obj_property>
<obj_property name="ObjectShortName">cfe_rq_complete</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/dout_data_valid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">dout_data_valid</obj_property>
<obj_property name="ObjectShortName">dout_data_valid</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/bus_owner" type="other" db_ref_id="1">
<obj_property name="ElementShortName">bus_owner</obj_property>
<obj_property name="ObjectShortName">bus_owner</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/bus_owner_reg" type="other" db_ref_id="1">
<obj_property name="ElementShortName">bus_owner_reg</obj_property>
<obj_property name="ObjectShortName">bus_owner_reg</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/out_ctr" type="other" db_ref_id="1">
<obj_property name="ElementShortName">out_ctr</obj_property>
<obj_property name="ObjectShortName">out_ctr</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/in_ctr" type="other" db_ref_id="1">
<obj_property name="ElementShortName">in_ctr</obj_property>
<obj_property name="ObjectShortName">in_ctr</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/out_complete" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">out_complete</obj_property>
<obj_property name="ObjectShortName">out_complete</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/in_complete" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">in_complete</obj_property>
<obj_property name="ObjectShortName">in_complete</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/in_read" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">in_read</obj_property>
<obj_property name="ObjectShortName">in_read</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/in_write" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">in_write</obj_property>
<obj_property name="ObjectShortName">in_write</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/ddr_adr_int" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr_adr_int[22:0]</obj_property>
<obj_property name="ObjectShortName">ddr_adr_int[22:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/ddr_adr_dly" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr_adr_dly[1:0]</obj_property>
<obj_property name="ObjectShortName">ddr_adr_dly[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/ddr_we_int" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr_we_int</obj_property>
<obj_property name="ObjectShortName">ddr_we_int</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/ddr_we_dly" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr_we_dly[1:0]</obj_property>
<obj_property name="ObjectShortName">ddr_we_dly[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/fifo_to_ddr_write_int" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_to_ddr_write_int</obj_property>
<obj_property name="ObjectShortName">fifo_to_ddr_write_int</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/fifo_to_ddr_write_dly" type="array" db_ref_id="1">
<obj_property name="ElementShortName">fifo_to_ddr_write_dly[1:0]</obj_property>
<obj_property name="ObjectShortName">fifo_to_ddr_write_dly[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/out_complete_dly" type="array" db_ref_id="1">
<obj_property name="ElementShortName">out_complete_dly[1:0]</obj_property>
<obj_property name="ObjectShortName">out_complete_dly[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/fifo_to_ddr_full_last" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_to_ddr_full_last</obj_property>
<obj_property name="ObjectShortName">fifo_to_ddr_full_last</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="group214" type="group">
<obj_property name="label">cfe</obj_property>
<obj_property name="DisplayName">label</obj_property>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/clk_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk_i</obj_property>
<obj_property name="ObjectShortName">clk_i</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/rst_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rst_i</obj_property>
<obj_property name="ObjectShortName">rst_i</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/wbs_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">wbs_i</obj_property>
<obj_property name="ObjectShortName">wbs_i</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/wbs_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">wbs_o</obj_property>
<obj_property name="ObjectShortName">wbs_o</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/wbs_cc_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">wbs_cc_i</obj_property>
<obj_property name="ObjectShortName">wbs_cc_i</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/wbs_cc_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">wbs_cc_o</obj_property>
<obj_property name="ObjectShortName">wbs_cc_o</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/mem_adr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">mem_adr[19:0]</obj_property>
<obj_property name="ObjectShortName">mem_adr[19:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/mem_rdrq" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">mem_rdrq</obj_property>
<obj_property name="ObjectShortName">mem_rdrq</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/mem_wrrq" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">mem_wrrq</obj_property>
<obj_property name="ObjectShortName">mem_wrrq</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/mem_dat_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">mem_dat_o[63:0]</obj_property>
<obj_property name="ObjectShortName">mem_dat_o[63:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/mem_ack" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">mem_ack</obj_property>
<obj_property name="ObjectShortName">mem_ack</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/mem_dat_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">mem_dat_i[63:0]</obj_property>
<obj_property name="ObjectShortName">mem_dat_i[63:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/cc_tag" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cc_tag[31:0]</obj_property>
<obj_property name="ObjectShortName">cc_tag[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/cc_lru" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cc_lru[31:0]</obj_property>
<obj_property name="ObjectShortName">cc_lru[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/cc_valid" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cc_valid[31:0]</obj_property>
<obj_property name="ObjectShortName">cc_valid[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/cc_dirty" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cc_dirty[31:0]</obj_property>
<obj_property name="ObjectShortName">cc_dirty[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/cc_we" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">cc_we</obj_property>
<obj_property name="ObjectShortName">cc_we</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/cc_wr_addr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cc_wr_addr[4:0]</obj_property>
<obj_property name="ObjectShortName">cc_wr_addr[4:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/cc_rd_addr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cc_rd_addr[4:0]</obj_property>
<obj_property name="ObjectShortName">cc_rd_addr[4:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/cc_tag_wr_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cc_tag_wr_data[29:0]</obj_property>
<obj_property name="ObjectShortName">cc_tag_wr_data[29:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/cc_tag_rd_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cc_tag_rd_data[29:0]</obj_property>
<obj_property name="ObjectShortName">cc_tag_rd_data[29:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/cc_lru_wr_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cc_lru_wr_data[1:0]</obj_property>
<obj_property name="ObjectShortName">cc_lru_wr_data[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/cc_lru_rd_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cc_lru_rd_data[1:0]</obj_property>
<obj_property name="ObjectShortName">cc_lru_rd_data[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/cc_valid_wr_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cc_valid_wr_data[1:0]</obj_property>
<obj_property name="ObjectShortName">cc_valid_wr_data[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/cc_valid_rd_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cc_valid_rd_data[1:0]</obj_property>
<obj_property name="ObjectShortName">cc_valid_rd_data[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/cc_dirty_wr_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cc_dirty_wr_data[1:0]</obj_property>
<obj_property name="ObjectShortName">cc_dirty_wr_data[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/cc_dirty_rd_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cc_dirty_rd_data[1:0]</obj_property>
<obj_property name="ObjectShortName">cc_dirty_rd_data[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/tags" type="array" db_ref_id="1">
<obj_property name="ElementShortName">tags[1:0]</obj_property>
<obj_property name="ObjectShortName">tags[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/cache_wr_addr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cache_wr_addr[8:0]</obj_property>
<obj_property name="ObjectShortName">cache_wr_addr[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/cache_rd_addr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cache_rd_addr[8:0]</obj_property>
<obj_property name="ObjectShortName">cache_rd_addr[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/cache_wr_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cache_wr_data[63:0]</obj_property>
<obj_property name="ObjectShortName">cache_wr_data[63:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/cache_rd_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cache_rd_data[63:0]</obj_property>
<obj_property name="ObjectShortName">cache_rd_data[63:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/cache_bwe" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cache_bwe[7:0]</obj_property>
<obj_property name="ObjectShortName">cache_bwe[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/adr_index" type="array" db_ref_id="1">
<obj_property name="ElementShortName">adr_index[4:0]</obj_property>
<obj_property name="ObjectShortName">adr_index[4:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/adr_offset" type="array" db_ref_id="1">
<obj_property name="ElementShortName">adr_offset[2:0]</obj_property>
<obj_property name="ObjectShortName">adr_offset[2:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/adr_tag" type="array" db_ref_id="1">
<obj_property name="ElementShortName">adr_tag[14:0]</obj_property>
<obj_property name="ObjectShortName">adr_tag[14:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/adr_tag_eq" type="array" db_ref_id="1">
<obj_property name="ElementShortName">adr_tag_eq[1:0]</obj_property>
<obj_property name="ObjectShortName">adr_tag_eq[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/lru_eq0" type="array" db_ref_id="1">
<obj_property name="ElementShortName">lru_eq0[1:0]</obj_property>
<obj_property name="ObjectShortName">lru_eq0[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/adr_tag_eq_num" type="array" db_ref_id="1">
<obj_property name="ElementShortName">adr_tag_eq_num[0:0]</obj_property>
<obj_property name="ObjectShortName">adr_tag_eq_num[0:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/eject_num" type="array" db_ref_id="1">
<obj_property name="ElementShortName">eject_num[0:0]</obj_property>
<obj_property name="ObjectShortName">eject_num[0:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/update_lru" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">update_lru</obj_property>
<obj_property name="ObjectShortName">update_lru</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/set_dirty" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">set_dirty</obj_property>
<obj_property name="ObjectShortName">set_dirty</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/set_valid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">set_valid</obj_property>
<obj_property name="ObjectShortName">set_valid</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/cache_write" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">cache_write</obj_property>
<obj_property name="ObjectShortName">cache_write</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/cache_from_mem" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">cache_from_mem</obj_property>
<obj_property name="ObjectShortName">cache_from_mem</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/eject_dirty" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">eject_dirty</obj_property>
<obj_property name="ObjectShortName">eject_dirty</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/set_invalid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">set_invalid</obj_property>
<obj_property name="ObjectShortName">set_invalid</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/cache_to_mem" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">cache_to_mem</obj_property>
<obj_property name="ObjectShortName">cache_to_mem</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/user_cc" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">user_cc</obj_property>
<obj_property name="ObjectShortName">user_cc</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/adr_tag_eq_num_dirty" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">adr_tag_eq_num_dirty</obj_property>
<obj_property name="ObjectShortName">adr_tag_eq_num_dirty</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/mem_offset" type="array" db_ref_id="1">
<obj_property name="ElementShortName">mem_offset[2:0]</obj_property>
<obj_property name="ObjectShortName">mem_offset[2:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/mem_offset_dly" type="array" db_ref_id="1">
<obj_property name="ElementShortName">mem_offset_dly[2:0]</obj_property>
<obj_property name="ObjectShortName">mem_offset_dly[2:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/mem_rdrq_int" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">mem_rdrq_int</obj_property>
<obj_property name="ObjectShortName">mem_rdrq_int</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/mem_wrrq_int" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">mem_wrrq_int</obj_property>
<obj_property name="ObjectShortName">mem_wrrq_int</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/user_cc_req_flush" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">user_cc_req_flush</obj_property>
<obj_property name="ObjectShortName">user_cc_req_flush</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/user_cc_req_inval" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">user_cc_req_inval</obj_property>
<obj_property name="ObjectShortName">user_cc_req_inval</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/user_cc_read" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">user_cc_read</obj_property>
<obj_property name="ObjectShortName">user_cc_read</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/system_cd_inst/wb_ddr_ctrl_wb_sc_fe_1/wb_ddr_ctrl_wb_sc_fe_fsm_inst/state" type="other" db_ref_id="1">
<obj_property name="ElementShortName">state</obj_property>
<obj_property name="ObjectShortName">state</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="group221" type="group">
<obj_property name="label">ddr_ctrl_dc</obj_property>
<obj_property name="DisplayName">label</obj_property>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/ddr2_clk0" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_clk0</obj_property>
<obj_property name="ObjectShortName">ddr2_clk0</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/ddr2_clk180" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_clk180</obj_property>
<obj_property name="ObjectShortName">ddr2_clk180</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/ddr2_clk90" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_clk90</obj_property>
<obj_property name="ObjectShortName">ddr2_clk90</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/ddr2_reset" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_reset</obj_property>
<obj_property name="ObjectShortName">ddr2_reset</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/ctrl_input_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_input_data[31:0]</obj_property>
<obj_property name="ObjectShortName">ctrl_input_data[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/ctrl_data_mask" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_data_mask[3:0]</obj_property>
<obj_property name="ObjectShortName">ctrl_data_mask[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/ctrl_output_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_output_data[31:0]</obj_property>
<obj_property name="ObjectShortName">ctrl_output_data[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/ctrl_data_valid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_data_valid</obj_property>
<obj_property name="ObjectShortName">ctrl_data_valid</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/ctrl_input_address" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_input_address[24:0]</obj_property>
<obj_property name="ObjectShortName">ctrl_input_address[24:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/ctrl_command_register" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_command_register[2:0]</obj_property>
<obj_property name="ObjectShortName">ctrl_command_register[2:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/ctrl_burst_done" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_burst_done</obj_property>
<obj_property name="ObjectShortName">ctrl_burst_done</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/ctrl_auto_ref_req" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_auto_ref_req</obj_property>
<obj_property name="ObjectShortName">ctrl_auto_ref_req</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/ctrl_cmd_ack" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_cmd_ack</obj_property>
<obj_property name="ObjectShortName">ctrl_cmd_ack</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/ctrl_init_done" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_init_done</obj_property>
<obj_property name="ObjectShortName">ctrl_init_done</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/ctrl_ar_done" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_ar_done</obj_property>
<obj_property name="ObjectShortName">ctrl_ar_done</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/din" type="array" db_ref_id="1">
<obj_property name="ElementShortName">din[63:0]</obj_property>
<obj_property name="ObjectShortName">din[63:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/dout" type="array" db_ref_id="1">
<obj_property name="ElementShortName">dout[63:0]</obj_property>
<obj_property name="ObjectShortName">dout[63:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/adr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">adr[22:0]</obj_property>
<obj_property name="ObjectShortName">adr[22:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/we" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">we</obj_property>
<obj_property name="ObjectShortName">we</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/be" type="array" db_ref_id="1">
<obj_property name="ElementShortName">be[7:0]</obj_property>
<obj_property name="ObjectShortName">be[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/fifo_to_sys_write" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_to_sys_write</obj_property>
<obj_property name="ObjectShortName">fifo_to_sys_write</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/fifo_from_sys_read" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_from_sys_read</obj_property>
<obj_property name="ObjectShortName">fifo_from_sys_read</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/fifo_to_sys_full" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_to_sys_full</obj_property>
<obj_property name="ObjectShortName">fifo_to_sys_full</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/fifo_from_sys_empty" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_from_sys_empty</obj_property>
<obj_property name="ObjectShortName">fifo_from_sys_empty</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/ddr_address" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr_address[22:0]</obj_property>
<obj_property name="ObjectShortName">ddr_address[22:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/ddr_address_en" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr_address_en</obj_property>
<obj_property name="ObjectShortName">ddr_address_en</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/ddr_dout" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr_dout[31:0]</obj_property>
<obj_property name="ObjectShortName">ddr_dout[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/ddr_dout_en" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr_dout_en</obj_property>
<obj_property name="ObjectShortName">ddr_dout_en</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/ddr_dout_high" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr_dout_high</obj_property>
<obj_property name="ObjectShortName">ddr_dout_high</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/ddr_dmask" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr_dmask[3:0]</obj_property>
<obj_property name="ObjectShortName">ddr_dmask[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/ddr_dmask_rst" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr_dmask_rst</obj_property>
<obj_property name="ObjectShortName">ddr_dmask_rst</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/ddr_dmask_en" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr_dmask_en</obj_property>
<obj_property name="ObjectShortName">ddr_dmask_en</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/ctrl_command_register_d" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_command_register_d[2:0]</obj_property>
<obj_property name="ObjectShortName">ctrl_command_register_d[2:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/ctrl_burst_done_d" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_burst_done_d</obj_property>
<obj_property name="ObjectShortName">ctrl_burst_done_d</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/dout_low" type="array" db_ref_id="1">
<obj_property name="ElementShortName">dout_low[31:0]</obj_property>
<obj_property name="ObjectShortName">dout_low[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/dout_low_en" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">dout_low_en</obj_property>
<obj_property name="ObjectShortName">dout_low_en</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/ctrl_data_valid_toggle" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_data_valid_toggle</obj_property>
<obj_property name="ObjectShortName">ctrl_data_valid_toggle</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/wb_ddr_ctrl_wb_dc_fsm_inst/ctrl_state" type="other" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_state</obj_property>
<obj_property name="ObjectShortName">ctrl_state</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/wb_ddr_ctrl_wb_dc_fsm_inst/burst_start_adr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">burst_start_adr[12:0]</obj_property>
<obj_property name="ObjectShortName">burst_start_adr[12:0]</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/wb_ddr_ctrl_wb_dc_fsm_inst/fifo_pending" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_pending</obj_property>
<obj_property name="ObjectShortName">fifo_pending</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/wb_ddr_ctrl_wb_dc_fsm_inst/fifo_from_sys_read_int" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_from_sys_read_int</obj_property>
<obj_property name="ObjectShortName">fifo_from_sys_read_int</obj_property>
</wvobject>
<wvobject fp_name="/toplevel_tb/DUT/ddr_ctrl0/wb_0/ddr_cd_inst/wb_ddr_ctrl_wb_dc_fsm_inst/fifo_from_sys_valid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_from_sys_valid</obj_property>
<obj_property name="ObjectShortName">fifo_from_sys_valid</obj_property>
</wvobject> </wvobject>
</wvobject> </wvobject>
</wave_config> </wave_config>