Matthias Blankertz 077bef75d3 - System integration & debugging

2013-03-09 14:14:22 +01:00

constr

- System integration & debugging

2013-03-09 14:14:22 +01:00

coregen

- Reworked VGA

2013-03-07 20:55:58 +01:00

ddr2_sdram/vhdl_bl4/example_design

- System integration & debugging

2013-03-09 14:14:22 +01:00

src

- System integration & debugging

2013-03-09 14:14:22 +01:00

tb

- System integration & debugging

2013-03-09 14:14:22 +01:00

tools

- Debugging

2013-03-05 22:49:30 +01:00

zy2000

- Added synthesis contraints

2013-03-04 12:55:59 +01:00

.gitignore

- Reworked VGA

2013-03-07 20:55:58 +01:00

2d_display_engine.xst

- Added synthesis contraints

2013-03-04 12:55:59 +01:00

Makefile

- System integration & debugging

2013-03-09 14:14:22 +01:00

planahead_postsynth.tcl

- Added synthesis contraints

2013-03-04 12:55:59 +01:00

toplevel_tb.wcfg

- System integration & debugging

2013-03-09 14:14:22 +01:00

vga_tb.wcfg

- Reworked VGA

2013-03-07 20:55:58 +01:00

vga.bmp

- Added synthesis contraints

2013-03-04 12:55:59 +01:00

wb_ddr_ctrl_tb.wcfg

- Added synthesis contraints

2013-03-04 12:55:59 +01:00

wb_ddr_ctrl_wb_sc_fe_tb.wcfg

- Debugging

2013-03-05 22:49:30 +01:00

wb_ddr_ctrl_wb_sc_tb.wcfg

- Integrated DDR controller with VGA and cache controller

2013-03-08 21:43:43 +01:00

Description

No description provided

372 KiB

Languages

VHDL 69.1%

Verilog 10.1%

SystemVerilog 8%

Raku 7.9%

C++ 2.6%

Other 2.2%