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077bef75d3
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- System integration & debugging
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2013-03-09 14:14:22 +01:00 |
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861cd1e00d
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- Integrated DDR controller with VGA and cache controller
- Debugged the above
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2013-03-08 21:43:43 +01:00 |
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90631f89bd
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- Reworked VGA
- Started changing DDR controller interface to 64 bit bus width
- Debugging
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2013-03-07 20:55:58 +01:00 |
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17835c4f7f
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- Debugging
- Added manual flush/invalidate to cache
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2013-03-05 22:49:30 +01:00 |
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321ea30ed8
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- Added synthesis contraints
- Added ZPU processor
- Optimized wb_ddr_ctrl_wb_dc* to meet timing
- Added cache frontend
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2013-03-04 12:55:59 +01:00 |
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34bec7d6c7
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- Begun implementing VGA out
- Integrated wishbone interconnect generator
- Debugging
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2013-03-02 21:27:54 +01:00 |
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f65882554d
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- Debugged write burst
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2013-03-02 12:29:47 +01:00 |
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cac9a8a60f
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- Corrected write timing
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2013-03-02 12:29:07 +01:00 |
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c04775d4a7
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- Made build rule for testbenches generic
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2013-03-02 12:26:58 +01:00 |
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95aa43b2d5
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- Debugging wb_ddr_ctrl
- Changed wb_ddr_ctrl_wb FIFO to 64 bit data width
- Added write burst support to wb_ddr_ctrl_wb_sc
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2013-02-28 21:10:44 +01:00 |
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56930a80c3
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- Seperated control and data path in wb_ddr_ctrl_wb_dc
- Debugging wb_ddr_ctrl
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2013-02-28 15:54:48 +01:00 |
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70aaa51615
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- Fixed DDR reset polarity
- Added planAhead script
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2013-02-27 12:13:26 +01:00 |
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dd2c99b93f
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- Import project
- Clean up
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2013-02-26 23:54:37 +01:00 |
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