matthias/2d_display_engine-new
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

- Debugging wb_ddr_ctrl

Browse Source 
- Changed wb_ddr_ctrl_wb FIFO to 64 bit data width
- Added write burst support to wb_ddr_ctrl_wb_sc
This commit is contained in:
Matthias Blankertz
2013-02-28 21:10:44 +01:00
parent 56930a80c3
commit 95aa43b2d5
9 changed files with 2994 additions and 2802 deletions
Download Patch File Download Diff File Expand all files Collapse all files

851
Default.wcfg
View File

@@ -1,419 +1,432 @@
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="./isim.wdb" id="1" type="auto">
<top_modules>
<top_module name="numeric_std" />
<top_module name="std_logic_1164" />
<top_module name="std_logic_arith" />
<top_module name="std_logic_unsigned" />
<top_module name="textio" />
<top_module name="vcomponents" />
<top_module name="vhdl_bl4_parameters_0" />
<top_module name="vital_primitives" />
<top_module name="vital_timing" />
<top_module name="vl_types" />
<top_module name="vpkg" />
<top_module name="wb_ddr_ctrl_tb" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="3" />
<wvobject fp_name="group31" type="group">
<obj_property name="label">toplevel</obj_property>
<obj_property name="DisplayName">label</obj_property>
<wvobject fp_name="/wb_ddr_ctrl_tb/ddr2_clock" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_clock</obj_property>
<obj_property name="ObjectShortName">ddr2_clock</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/ddr2_reset" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_reset</obj_property>
<obj_property name="ObjectShortName">ddr2_reset</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/ddr2_dq" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_dq[15:0]</obj_property>
<obj_property name="ObjectShortName">ddr2_dq[15:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/ddr2_a" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_a[12:0]</obj_property>
<obj_property name="ObjectShortName">ddr2_a[12:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/ddr2_ba" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_ba[1:0]</obj_property>
<obj_property name="ObjectShortName">ddr2_ba[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/ddr2_cke" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_cke</obj_property>
<obj_property name="ObjectShortName">ddr2_cke</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/ddr2_cs_n" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_cs_n</obj_property>
<obj_property name="ObjectShortName">ddr2_cs_n</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/ddr2_ras_n" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_ras_n</obj_property>
<obj_property name="ObjectShortName">ddr2_ras_n</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/ddr2_cas_n" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_cas_n</obj_property>
<obj_property name="ObjectShortName">ddr2_cas_n</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/ddr2_we_n" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_we_n</obj_property>
<obj_property name="ObjectShortName">ddr2_we_n</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/ddr2_odt" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_odt</obj_property>
<obj_property name="ObjectShortName">ddr2_odt</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/ddr2_dm" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_dm[1:0]</obj_property>
<obj_property name="ObjectShortName">ddr2_dm[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/rst_dqs_div_in" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rst_dqs_div_in</obj_property>
<obj_property name="ObjectShortName">rst_dqs_div_in</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/rst_dqs_div_out" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rst_dqs_div_out</obj_property>
<obj_property name="ObjectShortName">rst_dqs_div_out</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/ddr2_dqs" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_dqs[1:0]</obj_property>
<obj_property name="ObjectShortName">ddr2_dqs[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/ddr2_dqs_n" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_dqs_n[1:0]</obj_property>
<obj_property name="ObjectShortName">ddr2_dqs_n[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/ddr2_ck" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_ck[0:0]</obj_property>
<obj_property name="ObjectShortName">ddr2_ck[0:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/ddr2_ck_n" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_ck_n[0:0]</obj_property>
<obj_property name="ObjectShortName">ddr2_ck_n[0:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/clk_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk_i</obj_property>
<obj_property name="ObjectShortName">clk_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/rst_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rst_i</obj_property>
<obj_property name="ObjectShortName">rst_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/dat_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">dat_i[31:0]</obj_property>
<obj_property name="ObjectShortName">dat_i[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/dat_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">dat_o[31:0]</obj_property>
<obj_property name="ObjectShortName">dat_o[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/ack_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ack_o</obj_property>
<obj_property name="ObjectShortName">ack_o</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/adr_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">adr_i[25:2]</obj_property>
<obj_property name="ObjectShortName">adr_i[25:2]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/cyc_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">cyc_i</obj_property>
<obj_property name="ObjectShortName">cyc_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/sel_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">sel_i[3:0]</obj_property>
<obj_property name="ObjectShortName">sel_i[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/stb_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">stb_i</obj_property>
<obj_property name="ObjectShortName">stb_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/we_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">we_i</obj_property>
<obj_property name="ObjectShortName">we_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/cti_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cti_i[2:0]</obj_property>
<obj_property name="ObjectShortName">cti_i[2:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/bte_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">bte_i[1:0]</obj_property>
<obj_property name="ObjectShortName">bte_i[1:0]</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="group32" type="group">
<obj_property name="label">ddr_cd_inst</obj_property>
<obj_property name="DisplayName">label</obj_property>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ddr2_clk0" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_clk0</obj_property>
<obj_property name="ObjectShortName">ddr2_clk0</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ddr2_clk180" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_clk180</obj_property>
<obj_property name="ObjectShortName">ddr2_clk180</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ddr2_clk90" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_clk90</obj_property>
<obj_property name="ObjectShortName">ddr2_clk90</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ddr2_reset" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_reset</obj_property>
<obj_property name="ObjectShortName">ddr2_reset</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ctrl_input_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_input_data[31:0]</obj_property>
<obj_property name="ObjectShortName">ctrl_input_data[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ctrl_data_mask" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_data_mask[3:0]</obj_property>
<obj_property name="ObjectShortName">ctrl_data_mask[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ctrl_output_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_output_data[31:0]</obj_property>
<obj_property name="ObjectShortName">ctrl_output_data[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ctrl_data_valid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_data_valid</obj_property>
<obj_property name="ObjectShortName">ctrl_data_valid</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ctrl_input_address" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_input_address[24:0]</obj_property>
<obj_property name="ObjectShortName">ctrl_input_address[24:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ctrl_command_register" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_command_register[2:0]</obj_property>
<obj_property name="ObjectShortName">ctrl_command_register[2:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ctrl_burst_done" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_burst_done</obj_property>
<obj_property name="ObjectShortName">ctrl_burst_done</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ctrl_auto_ref_req" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_auto_ref_req</obj_property>
<obj_property name="ObjectShortName">ctrl_auto_ref_req</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ctrl_cmd_ack" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_cmd_ack</obj_property>
<obj_property name="ObjectShortName">ctrl_cmd_ack</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ctrl_init_done" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_init_done</obj_property>
<obj_property name="ObjectShortName">ctrl_init_done</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ctrl_ar_done" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_ar_done</obj_property>
<obj_property name="ObjectShortName">ctrl_ar_done</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/din" type="array" db_ref_id="1">
<obj_property name="ElementShortName">din[31:0]</obj_property>
<obj_property name="ObjectShortName">din[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/dout" type="array" db_ref_id="1">
<obj_property name="ElementShortName">dout[31:0]</obj_property>
<obj_property name="ObjectShortName">dout[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/adr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">adr[23:0]</obj_property>
<obj_property name="ObjectShortName">adr[23:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/we" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">we</obj_property>
<obj_property name="ObjectShortName">we</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/be" type="array" db_ref_id="1">
<obj_property name="ElementShortName">be[3:0]</obj_property>
<obj_property name="ObjectShortName">be[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/fifo_to_sys_write" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_to_sys_write</obj_property>
<obj_property name="ObjectShortName">fifo_to_sys_write</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/fifo_from_sys_read" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_from_sys_read</obj_property>
<obj_property name="ObjectShortName">fifo_from_sys_read</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/fifo_to_sys_full" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_to_sys_full</obj_property>
<obj_property name="ObjectShortName">fifo_to_sys_full</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/fifo_from_sys_empty" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_from_sys_empty</obj_property>
<obj_property name="ObjectShortName">fifo_from_sys_empty</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ddr_address" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr_address[23:0]</obj_property>
<obj_property name="ObjectShortName">ddr_address[23:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ddr_address_en" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr_address_en</obj_property>
<obj_property name="ObjectShortName">ddr_address_en</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ddr_dout" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr_dout[31:0]</obj_property>
<obj_property name="ObjectShortName">ddr_dout[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ddr_dout_en" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr_dout_en</obj_property>
<obj_property name="ObjectShortName">ddr_dout_en</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ddr_dmask" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr_dmask[3:0]</obj_property>
<obj_property name="ObjectShortName">ddr_dmask[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ddr_dmask_rst" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr_dmask_rst</obj_property>
<obj_property name="ObjectShortName">ddr_dmask_rst</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ddr_dmask_en" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr_dmask_en</obj_property>
<obj_property name="ObjectShortName">ddr_dmask_en</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ctrl_command_register_d" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_command_register_d[2:0]</obj_property>
<obj_property name="ObjectShortName">ctrl_command_register_d[2:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ctrl_burst_done_d" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_burst_done_d</obj_property>
<obj_property name="ObjectShortName">ctrl_burst_done_d</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/wb_ddr_ctrl_wb_dc_fsm_inst/ctrl_state" type="other" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_state</obj_property>
<obj_property name="ObjectShortName">ctrl_state</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/wb_ddr_ctrl_wb_dc_fsm_inst/burst_start_adr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">burst_start_adr[12:0]</obj_property>
<obj_property name="ObjectShortName">burst_start_adr[12:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/wb_ddr_ctrl_wb_dc_fsm_inst/fifo_pending" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_pending</obj_property>
<obj_property name="ObjectShortName">fifo_pending</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/wb_ddr_ctrl_wb_dc_fsm_inst/fifo_from_sys_read_int" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_from_sys_read_int</obj_property>
<obj_property name="ObjectShortName">fifo_from_sys_read_int</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/wb_ddr_ctrl_wb_dc_fsm_inst/fifo_from_sys_valid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_from_sys_valid</obj_property>
<obj_property name="ObjectShortName">fifo_from_sys_valid</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="group33" type="group">
<obj_property name="label">system_cd_inst</obj_property>
<obj_property name="DisplayName">label</obj_property>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/clk_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk_i</obj_property>
<obj_property name="ObjectShortName">clk_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/rst_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rst_i</obj_property>
<obj_property name="ObjectShortName">rst_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/dat_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">dat_i[31:0]</obj_property>
<obj_property name="ObjectShortName">dat_i[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/dat_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">dat_o[31:0]</obj_property>
<obj_property name="ObjectShortName">dat_o[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/ack_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ack_o</obj_property>
<obj_property name="ObjectShortName">ack_o</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/adr_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">adr_i[25:2]</obj_property>
<obj_property name="ObjectShortName">adr_i[25:2]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/cyc_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">cyc_i</obj_property>
<obj_property name="ObjectShortName">cyc_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/sel_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">sel_i[3:0]</obj_property>
<obj_property name="ObjectShortName">sel_i[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/stb_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">stb_i</obj_property>
<obj_property name="ObjectShortName">stb_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/we_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">we_i</obj_property>
<obj_property name="ObjectShortName">we_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/cti_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cti_i[2:0]</obj_property>
<obj_property name="ObjectShortName">cti_i[2:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/bte_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">bte_i[1:0]</obj_property>
<obj_property name="ObjectShortName">bte_i[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/ddr_din" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr_din[31:0]</obj_property>
<obj_property name="ObjectShortName">ddr_din[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/ddr_dout" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr_dout[31:0]</obj_property>
<obj_property name="ObjectShortName">ddr_dout[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/ddr_adr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr_adr[23:0]</obj_property>
<obj_property name="ObjectShortName">ddr_adr[23:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/ddr_we" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr_we</obj_property>
<obj_property name="ObjectShortName">ddr_we</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/ddr_be" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr_be[3:0]</obj_property>
<obj_property name="ObjectShortName">ddr_be[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/fifo_to_ddr_write" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_to_ddr_write</obj_property>
<obj_property name="ObjectShortName">fifo_to_ddr_write</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/fifo_from_ddr_read" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_from_ddr_read</obj_property>
<obj_property name="ObjectShortName">fifo_from_ddr_read</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/fifo_to_ddr_full" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_to_ddr_full</obj_property>
<obj_property name="ObjectShortName">fifo_to_ddr_full</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/fifo_from_ddr_empty" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_from_ddr_empty</obj_property>
<obj_property name="ObjectShortName">fifo_from_ddr_empty</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/state" type="other" db_ref_id="1">
<obj_property name="ElementShortName">state</obj_property>
<obj_property name="ObjectShortName">state</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/fifo_from_ddr_read_int" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_from_ddr_read_int</obj_property>
<obj_property name="ObjectShortName">fifo_from_ddr_read_int</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/fifo_from_ddr_valid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_from_ddr_valid</obj_property>
<obj_property name="ObjectShortName">fifo_from_ddr_valid</obj_property>
</wvobject>
</wvobject>
</wave_config>
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="./isim.wdb" id="1" type="auto">
<top_modules>
<top_module name="numeric_std" />
<top_module name="std_logic_1164" />
<top_module name="std_logic_arith" />
<top_module name="std_logic_unsigned" />
<top_module name="textio" />
<top_module name="vcomponents" />
<top_module name="vhdl_bl4_parameters_0" />
<top_module name="vital_primitives" />
<top_module name="vital_timing" />
<top_module name="vl_types" />
<top_module name="vpkg" />
<top_module name="wb_ddr_ctrl_tb" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="3" />
<wvobject fp_name="group31" type="group">
<obj_property name="label">toplevel</obj_property>
<obj_property name="DisplayName">label</obj_property>
<wvobject fp_name="/wb_ddr_ctrl_tb/ddr2_clock" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_clock</obj_property>
<obj_property name="ObjectShortName">ddr2_clock</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/ddr2_reset" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_reset</obj_property>
<obj_property name="ObjectShortName">ddr2_reset</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/ddr2_dq" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_dq[15:0]</obj_property>
<obj_property name="ObjectShortName">ddr2_dq[15:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/ddr2_a" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_a[12:0]</obj_property>
<obj_property name="ObjectShortName">ddr2_a[12:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/ddr2_ba" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_ba[1:0]</obj_property>
<obj_property name="ObjectShortName">ddr2_ba[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/ddr2_cke" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_cke</obj_property>
<obj_property name="ObjectShortName">ddr2_cke</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/ddr2_cs_n" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_cs_n</obj_property>
<obj_property name="ObjectShortName">ddr2_cs_n</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/ddr2_ras_n" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_ras_n</obj_property>
<obj_property name="ObjectShortName">ddr2_ras_n</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/ddr2_cas_n" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_cas_n</obj_property>
<obj_property name="ObjectShortName">ddr2_cas_n</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/ddr2_we_n" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_we_n</obj_property>
<obj_property name="ObjectShortName">ddr2_we_n</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/ddr2_odt" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_odt</obj_property>
<obj_property name="ObjectShortName">ddr2_odt</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/ddr2_dm" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_dm[1:0]</obj_property>
<obj_property name="ObjectShortName">ddr2_dm[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/rst_dqs_div_in" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rst_dqs_div_in</obj_property>
<obj_property name="ObjectShortName">rst_dqs_div_in</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/rst_dqs_div_out" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rst_dqs_div_out</obj_property>
<obj_property name="ObjectShortName">rst_dqs_div_out</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/ddr2_dqs" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_dqs[1:0]</obj_property>
<obj_property name="ObjectShortName">ddr2_dqs[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/ddr2_dqs_n" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_dqs_n[1:0]</obj_property>
<obj_property name="ObjectShortName">ddr2_dqs_n[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/ddr2_ck" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_ck[0:0]</obj_property>
<obj_property name="ObjectShortName">ddr2_ck[0:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/ddr2_ck_n" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_ck_n[0:0]</obj_property>
<obj_property name="ObjectShortName">ddr2_ck_n[0:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/clk_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk_i</obj_property>
<obj_property name="ObjectShortName">clk_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/rst_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rst_i</obj_property>
<obj_property name="ObjectShortName">rst_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/dat_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">dat_i[31:0]</obj_property>
<obj_property name="ObjectShortName">dat_i[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/dat_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">dat_o[31:0]</obj_property>
<obj_property name="ObjectShortName">dat_o[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/ack_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ack_o</obj_property>
<obj_property name="ObjectShortName">ack_o</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/adr_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">adr_i[25:2]</obj_property>
<obj_property name="ObjectShortName">adr_i[25:2]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/cyc_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">cyc_i</obj_property>
<obj_property name="ObjectShortName">cyc_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/sel_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">sel_i[3:0]</obj_property>
<obj_property name="ObjectShortName">sel_i[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/stb_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">stb_i</obj_property>
<obj_property name="ObjectShortName">stb_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/we_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">we_i</obj_property>
<obj_property name="ObjectShortName">we_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/cti_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cti_i[2:0]</obj_property>
<obj_property name="ObjectShortName">cti_i[2:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/bte_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">bte_i[1:0]</obj_property>
<obj_property name="ObjectShortName">bte_i[1:0]</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="group32" type="group">
<obj_property name="label">ddr_cd_inst</obj_property>
<obj_property name="DisplayName">label</obj_property>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ddr2_clk0" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_clk0</obj_property>
<obj_property name="ObjectShortName">ddr2_clk0</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ddr2_clk180" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_clk180</obj_property>
<obj_property name="ObjectShortName">ddr2_clk180</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ddr2_clk90" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_clk90</obj_property>
<obj_property name="ObjectShortName">ddr2_clk90</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ddr2_reset" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr2_reset</obj_property>
<obj_property name="ObjectShortName">ddr2_reset</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ctrl_input_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_input_data[31:0]</obj_property>
<obj_property name="ObjectShortName">ctrl_input_data[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ctrl_data_mask" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_data_mask[3:0]</obj_property>
<obj_property name="ObjectShortName">ctrl_data_mask[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ctrl_output_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_output_data[31:0]</obj_property>
<obj_property name="ObjectShortName">ctrl_output_data[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ctrl_data_valid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_data_valid</obj_property>
<obj_property name="ObjectShortName">ctrl_data_valid</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ctrl_input_address" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_input_address[24:0]</obj_property>
<obj_property name="ObjectShortName">ctrl_input_address[24:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ctrl_command_register" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_command_register[2:0]</obj_property>
<obj_property name="ObjectShortName">ctrl_command_register[2:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ctrl_burst_done" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_burst_done</obj_property>
<obj_property name="ObjectShortName">ctrl_burst_done</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ctrl_auto_ref_req" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_auto_ref_req</obj_property>
<obj_property name="ObjectShortName">ctrl_auto_ref_req</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ctrl_cmd_ack" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_cmd_ack</obj_property>
<obj_property name="ObjectShortName">ctrl_cmd_ack</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ctrl_init_done" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_init_done</obj_property>
<obj_property name="ObjectShortName">ctrl_init_done</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ctrl_ar_done" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_ar_done</obj_property>
<obj_property name="ObjectShortName">ctrl_ar_done</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/din" type="array" db_ref_id="1">
<obj_property name="ElementShortName">din[63:0]</obj_property>
<obj_property name="ObjectShortName">din[63:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/dout" type="array" db_ref_id="1">
<obj_property name="ElementShortName">dout[63:0]</obj_property>
<obj_property name="ObjectShortName">dout[63:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/adr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">adr[22:0]</obj_property>
<obj_property name="ObjectShortName">adr[22:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/we" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">we</obj_property>
<obj_property name="ObjectShortName">we</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/be" type="array" db_ref_id="1">
<obj_property name="ElementShortName">be[7:0]</obj_property>
<obj_property name="ObjectShortName">be[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/fifo_to_sys_write" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_to_sys_write</obj_property>
<obj_property name="ObjectShortName">fifo_to_sys_write</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/fifo_from_sys_read" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_from_sys_read</obj_property>
<obj_property name="ObjectShortName">fifo_from_sys_read</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/fifo_to_sys_full" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_to_sys_full</obj_property>
<obj_property name="ObjectShortName">fifo_to_sys_full</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/fifo_from_sys_empty" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_from_sys_empty</obj_property>
<obj_property name="ObjectShortName">fifo_from_sys_empty</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ddr_address" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr_address[22:0]</obj_property>
<obj_property name="ObjectShortName">ddr_address[22:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ddr_address_en" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr_address_en</obj_property>
<obj_property name="ObjectShortName">ddr_address_en</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ddr_dout" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr_dout[31:0]</obj_property>
<obj_property name="ObjectShortName">ddr_dout[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ddr_dout_en" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr_dout_en</obj_property>
<obj_property name="ObjectShortName">ddr_dout_en</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ddr_dout_high" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr_dout_high</obj_property>
<obj_property name="ObjectShortName">ddr_dout_high</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/dout_low" type="array" db_ref_id="1">
<obj_property name="ElementShortName">dout_low[31:0]</obj_property>
<obj_property name="ObjectShortName">dout_low[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/dout_low_en" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">dout_low_en</obj_property>
<obj_property name="ObjectShortName">dout_low_en</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ddr_dmask" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr_dmask[3:0]</obj_property>
<obj_property name="ObjectShortName">ddr_dmask[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ddr_dmask_rst" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr_dmask_rst</obj_property>
<obj_property name="ObjectShortName">ddr_dmask_rst</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ddr_dmask_en" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr_dmask_en</obj_property>
<obj_property name="ObjectShortName">ddr_dmask_en</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ctrl_command_register_d" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_command_register_d[2:0]</obj_property>
<obj_property name="ObjectShortName">ctrl_command_register_d[2:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/ctrl_burst_done_d" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_burst_done_d</obj_property>
<obj_property name="ObjectShortName">ctrl_burst_done_d</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/wb_ddr_ctrl_wb_dc_fsm_inst/ctrl_state" type="other" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_state</obj_property>
<obj_property name="ObjectShortName">ctrl_state</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/wb_ddr_ctrl_wb_dc_fsm_inst/burst_start_adr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">burst_start_adr[12:0]</obj_property>
<obj_property name="ObjectShortName">burst_start_adr[12:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/wb_ddr_ctrl_wb_dc_fsm_inst/fifo_pending" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_pending</obj_property>
<obj_property name="ObjectShortName">fifo_pending</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/wb_ddr_ctrl_wb_dc_fsm_inst/fifo_from_sys_read_int" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_from_sys_read_int</obj_property>
<obj_property name="ObjectShortName">fifo_from_sys_read_int</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/ddr_cd_inst/wb_ddr_ctrl_wb_dc_fsm_inst/fifo_from_sys_valid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_from_sys_valid</obj_property>
<obj_property name="ObjectShortName">fifo_from_sys_valid</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="group33" type="group">
<obj_property name="label">system_cd_inst</obj_property>
<obj_property name="DisplayName">label</obj_property>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/clk_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk_i</obj_property>
<obj_property name="ObjectShortName">clk_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/rst_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rst_i</obj_property>
<obj_property name="ObjectShortName">rst_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/dat_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">dat_i[31:0]</obj_property>
<obj_property name="ObjectShortName">dat_i[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/dat_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">dat_o[31:0]</obj_property>
<obj_property name="ObjectShortName">dat_o[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/ack_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ack_o</obj_property>
<obj_property name="ObjectShortName">ack_o</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/adr_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">adr_i[25:2]</obj_property>
<obj_property name="ObjectShortName">adr_i[25:2]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/cyc_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">cyc_i</obj_property>
<obj_property name="ObjectShortName">cyc_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/sel_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">sel_i[3:0]</obj_property>
<obj_property name="ObjectShortName">sel_i[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/stb_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">stb_i</obj_property>
<obj_property name="ObjectShortName">stb_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/we_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">we_i</obj_property>
<obj_property name="ObjectShortName">we_i</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/cti_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cti_i[2:0]</obj_property>
<obj_property name="ObjectShortName">cti_i[2:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/bte_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">bte_i[1:0]</obj_property>
<obj_property name="ObjectShortName">bte_i[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/ddr_din" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr_din[63:0]</obj_property>
<obj_property name="ObjectShortName">ddr_din[63:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/ddr_dout" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr_dout[63:0]</obj_property>
<obj_property name="ObjectShortName">ddr_dout[63:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/ddr_adr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr_adr[22:0]</obj_property>
<obj_property name="ObjectShortName">ddr_adr[22:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/ddr_we" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ddr_we</obj_property>
<obj_property name="ObjectShortName">ddr_we</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/ddr_be" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ddr_be[7:0]</obj_property>
<obj_property name="ObjectShortName">ddr_be[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/fifo_to_ddr_write" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_to_ddr_write</obj_property>
<obj_property name="ObjectShortName">fifo_to_ddr_write</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/fifo_from_ddr_read" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_from_ddr_read</obj_property>
<obj_property name="ObjectShortName">fifo_from_ddr_read</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/fifo_to_ddr_full" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_to_ddr_full</obj_property>
<obj_property name="ObjectShortName">fifo_to_ddr_full</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/fifo_from_ddr_empty" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_from_ddr_empty</obj_property>
<obj_property name="ObjectShortName">fifo_from_ddr_empty</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/state" type="other" db_ref_id="1">
<obj_property name="ElementShortName">state</obj_property>
<obj_property name="ObjectShortName">state</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/fifo_from_ddr_read_int" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_from_ddr_read_int</obj_property>
<obj_property name="ObjectShortName">fifo_from_ddr_read_int</obj_property>
</wvobject>
<wvobject fp_name="/wb_ddr_ctrl_tb/DUT/wb_0/system_cd_inst/fifo_from_ddr_valid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">fifo_from_ddr_valid</obj_property>
<obj_property name="ObjectShortName">fifo_from_ddr_valid</obj_property>
</wvobject>
</wvobject>
</wave_config>

3714
coregen/coregen.cgc Executable file → Normal file
View File

File diff suppressed because it is too large Load Diff

426
coregen/wb_ddr_ctrl_wb_from_ddr.xco Executable file → Normal file
View File

@@ -1,213 +1,213 @@
##############################################################
#
# Xilinx Core Generator version 14.4
# Date: Tue Feb 26 21:32:50 2013
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:fifo_generator:9.3
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc3s700an
SET devicefamily = spartan3a
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -4
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3
# END Select
# BEGIN Parameters
CSET add_ngc_constraint_axi=false
CSET almost_empty_flag=false
CSET almost_full_flag=false
CSET aruser_width=1
CSET awuser_width=1
CSET axi_address_width=32
CSET axi_data_width=64
CSET axi_type=AXI4_Stream
CSET axis_type=FIFO
CSET buser_width=1
CSET clock_enable_type=Slave_Interface_Clock_Enable
CSET clock_type_axi=Common_Clock
CSET component_name=wb_ddr_ctrl_wb_from_ddr
CSET data_count=false
CSET data_count_width=4
CSET disable_timing_violations=true
CSET disable_timing_violations_axi=false
CSET dout_reset_value=0
CSET empty_threshold_assert_value=2
CSET empty_threshold_assert_value_axis=1022
CSET empty_threshold_assert_value_rach=1022
CSET empty_threshold_assert_value_rdch=1022
CSET empty_threshold_assert_value_wach=1022
CSET empty_threshold_assert_value_wdch=1022
CSET empty_threshold_assert_value_wrch=1022
CSET empty_threshold_negate_value=3
CSET enable_aruser=false
CSET enable_awuser=false
CSET enable_buser=false
CSET enable_common_overflow=false
CSET enable_common_underflow=false
CSET enable_data_counts_axis=false
CSET enable_data_counts_rach=false
CSET enable_data_counts_rdch=false
CSET enable_data_counts_wach=false
CSET enable_data_counts_wdch=false
CSET enable_data_counts_wrch=false
CSET enable_ecc=false
CSET enable_ecc_axis=false
CSET enable_ecc_rach=false
CSET enable_ecc_rdch=false
CSET enable_ecc_wach=false
CSET enable_ecc_wdch=false
CSET enable_ecc_wrch=false
CSET enable_read_channel=false
CSET enable_read_pointer_increment_by2=false
CSET enable_reset_synchronization=true
CSET enable_ruser=false
CSET enable_tdata=false
CSET enable_tdest=false
CSET enable_tid=false
CSET enable_tkeep=false
CSET enable_tlast=false
CSET enable_tready=true
CSET enable_tstrobe=false
CSET enable_tuser=false
CSET enable_write_channel=false
CSET enable_wuser=false
CSET fifo_application_type_axis=Data_FIFO
CSET fifo_application_type_rach=Data_FIFO
CSET fifo_application_type_rdch=Data_FIFO
CSET fifo_application_type_wach=Data_FIFO
CSET fifo_application_type_wdch=Data_FIFO
CSET fifo_application_type_wrch=Data_FIFO
CSET fifo_implementation=Independent_Clocks_Distributed_RAM
CSET fifo_implementation_axis=Common_Clock_Block_RAM
CSET fifo_implementation_rach=Common_Clock_Block_RAM
CSET fifo_implementation_rdch=Common_Clock_Block_RAM
CSET fifo_implementation_wach=Common_Clock_Block_RAM
CSET fifo_implementation_wdch=Common_Clock_Block_RAM
CSET fifo_implementation_wrch=Common_Clock_Block_RAM
CSET full_flags_reset_value=1
CSET full_threshold_assert_value=13
CSET full_threshold_assert_value_axis=1023
CSET full_threshold_assert_value_rach=1023
CSET full_threshold_assert_value_rdch=1023
CSET full_threshold_assert_value_wach=1023
CSET full_threshold_assert_value_wdch=1023
CSET full_threshold_assert_value_wrch=1023
CSET full_threshold_negate_value=12
CSET id_width=4
CSET inject_dbit_error=false
CSET inject_dbit_error_axis=false
CSET inject_dbit_error_rach=false
CSET inject_dbit_error_rdch=false
CSET inject_dbit_error_wach=false
CSET inject_dbit_error_wdch=false
CSET inject_dbit_error_wrch=false
CSET inject_sbit_error=false
CSET inject_sbit_error_axis=false
CSET inject_sbit_error_rach=false
CSET inject_sbit_error_rdch=false
CSET inject_sbit_error_wach=false
CSET inject_sbit_error_wdch=false
CSET inject_sbit_error_wrch=false
CSET input_data_width=32
CSET input_depth=16
CSET input_depth_axis=1024
CSET input_depth_rach=16
CSET input_depth_rdch=1024
CSET input_depth_wach=16
CSET input_depth_wdch=1024
CSET input_depth_wrch=16
CSET interface_type=Native
CSET output_data_width=32
CSET output_depth=16
CSET overflow_flag=false
CSET overflow_flag_axi=false
CSET overflow_sense=Active_High
CSET overflow_sense_axi=Active_High
CSET performance_options=Standard_FIFO
CSET programmable_empty_type=No_Programmable_Empty_Threshold
CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold
CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold
CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold
CSET programmable_full_type=No_Programmable_Full_Threshold
CSET programmable_full_type_axis=No_Programmable_Full_Threshold
CSET programmable_full_type_rach=No_Programmable_Full_Threshold
CSET programmable_full_type_rdch=No_Programmable_Full_Threshold
CSET programmable_full_type_wach=No_Programmable_Full_Threshold
CSET programmable_full_type_wdch=No_Programmable_Full_Threshold
CSET programmable_full_type_wrch=No_Programmable_Full_Threshold
CSET rach_type=FIFO
CSET rdch_type=FIFO
CSET read_clock_frequency=1
CSET read_data_count=false
CSET read_data_count_width=4
CSET register_slice_mode_axis=Fully_Registered
CSET register_slice_mode_rach=Fully_Registered
CSET register_slice_mode_rdch=Fully_Registered
CSET register_slice_mode_wach=Fully_Registered
CSET register_slice_mode_wdch=Fully_Registered
CSET register_slice_mode_wrch=Fully_Registered
CSET reset_pin=true
CSET reset_type=Asynchronous_Reset
CSET ruser_width=1
CSET synchronization_stages=2
CSET synchronization_stages_axi=2
CSET tdata_width=64
CSET tdest_width=4
CSET tid_width=8
CSET tkeep_width=4
CSET tstrb_width=4
CSET tuser_width=4
CSET underflow_flag=false
CSET underflow_flag_axi=false
CSET underflow_sense=Active_High
CSET underflow_sense_axi=Active_High
CSET use_clock_enable=false
CSET use_dout_reset=true
CSET use_embedded_registers=false
CSET use_extra_logic=false
CSET valid_flag=false
CSET valid_sense=Active_High
CSET wach_type=FIFO
CSET wdch_type=FIFO
CSET wrch_type=FIFO
CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=1
CSET write_data_count=false
CSET write_data_count_width=4
CSET wuser_width=1
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-11-19T12:39:56Z
# END Extra information
GENERATE
# CRC: cda6b7a3
##############################################################
#
# Xilinx Core Generator version 14.3
# Date: Thu Feb 28 16:17:27 2013
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:fifo_generator:9.3
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc3s700an
SET devicefamily = spartan3a
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -4
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3
# END Select
# BEGIN Parameters
CSET add_ngc_constraint_axi=false
CSET almost_empty_flag=false
CSET almost_full_flag=false
CSET aruser_width=1
CSET awuser_width=1
CSET axi_address_width=32
CSET axi_data_width=64
CSET axi_type=AXI4_Stream
CSET axis_type=FIFO
CSET buser_width=1
CSET clock_enable_type=Slave_Interface_Clock_Enable
CSET clock_type_axi=Common_Clock
CSET component_name=wb_ddr_ctrl_wb_from_ddr
CSET data_count=false
CSET data_count_width=4
CSET disable_timing_violations=true
CSET disable_timing_violations_axi=false
CSET dout_reset_value=0
CSET empty_threshold_assert_value=2
CSET empty_threshold_assert_value_axis=1022
CSET empty_threshold_assert_value_rach=1022
CSET empty_threshold_assert_value_rdch=1022
CSET empty_threshold_assert_value_wach=1022
CSET empty_threshold_assert_value_wdch=1022
CSET empty_threshold_assert_value_wrch=1022
CSET empty_threshold_negate_value=3
CSET enable_aruser=false
CSET enable_awuser=false
CSET enable_buser=false
CSET enable_common_overflow=false
CSET enable_common_underflow=false
CSET enable_data_counts_axis=false
CSET enable_data_counts_rach=false
CSET enable_data_counts_rdch=false
CSET enable_data_counts_wach=false
CSET enable_data_counts_wdch=false
CSET enable_data_counts_wrch=false
CSET enable_ecc=false
CSET enable_ecc_axis=false
CSET enable_ecc_rach=false
CSET enable_ecc_rdch=false
CSET enable_ecc_wach=false
CSET enable_ecc_wdch=false
CSET enable_ecc_wrch=false
CSET enable_read_channel=false
CSET enable_read_pointer_increment_by2=false
CSET enable_reset_synchronization=true
CSET enable_ruser=false
CSET enable_tdata=false
CSET enable_tdest=false
CSET enable_tid=false
CSET enable_tkeep=false
CSET enable_tlast=false
CSET enable_tready=true
CSET enable_tstrobe=false
CSET enable_tuser=false
CSET enable_write_channel=false
CSET enable_wuser=false
CSET fifo_application_type_axis=Data_FIFO
CSET fifo_application_type_rach=Data_FIFO
CSET fifo_application_type_rdch=Data_FIFO
CSET fifo_application_type_wach=Data_FIFO
CSET fifo_application_type_wdch=Data_FIFO
CSET fifo_application_type_wrch=Data_FIFO
CSET fifo_implementation=Independent_Clocks_Distributed_RAM
CSET fifo_implementation_axis=Common_Clock_Block_RAM
CSET fifo_implementation_rach=Common_Clock_Block_RAM
CSET fifo_implementation_rdch=Common_Clock_Block_RAM
CSET fifo_implementation_wach=Common_Clock_Block_RAM
CSET fifo_implementation_wdch=Common_Clock_Block_RAM
CSET fifo_implementation_wrch=Common_Clock_Block_RAM
CSET full_flags_reset_value=1
CSET full_threshold_assert_value=13
CSET full_threshold_assert_value_axis=1023
CSET full_threshold_assert_value_rach=1023
CSET full_threshold_assert_value_rdch=1023
CSET full_threshold_assert_value_wach=1023
CSET full_threshold_assert_value_wdch=1023
CSET full_threshold_assert_value_wrch=1023
CSET full_threshold_negate_value=12
CSET id_width=4
CSET inject_dbit_error=false
CSET inject_dbit_error_axis=false
CSET inject_dbit_error_rach=false
CSET inject_dbit_error_rdch=false
CSET inject_dbit_error_wach=false
CSET inject_dbit_error_wdch=false
CSET inject_dbit_error_wrch=false
CSET inject_sbit_error=false
CSET inject_sbit_error_axis=false
CSET inject_sbit_error_rach=false
CSET inject_sbit_error_rdch=false
CSET inject_sbit_error_wach=false
CSET inject_sbit_error_wdch=false
CSET inject_sbit_error_wrch=false
CSET input_data_width=64
CSET input_depth=16
CSET input_depth_axis=1024
CSET input_depth_rach=16
CSET input_depth_rdch=1024
CSET input_depth_wach=16
CSET input_depth_wdch=1024
CSET input_depth_wrch=16
CSET interface_type=Native
CSET output_data_width=64
CSET output_depth=16
CSET overflow_flag=false
CSET overflow_flag_axi=false
CSET overflow_sense=Active_High
CSET overflow_sense_axi=Active_High
CSET performance_options=Standard_FIFO
CSET programmable_empty_type=No_Programmable_Empty_Threshold
CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold
CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold
CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold
CSET programmable_full_type=No_Programmable_Full_Threshold
CSET programmable_full_type_axis=No_Programmable_Full_Threshold
CSET programmable_full_type_rach=No_Programmable_Full_Threshold
CSET programmable_full_type_rdch=No_Programmable_Full_Threshold
CSET programmable_full_type_wach=No_Programmable_Full_Threshold
CSET programmable_full_type_wdch=No_Programmable_Full_Threshold
CSET programmable_full_type_wrch=No_Programmable_Full_Threshold
CSET rach_type=FIFO
CSET rdch_type=FIFO
CSET read_clock_frequency=1
CSET read_data_count=false
CSET read_data_count_width=4
CSET register_slice_mode_axis=Fully_Registered
CSET register_slice_mode_rach=Fully_Registered
CSET register_slice_mode_rdch=Fully_Registered
CSET register_slice_mode_wach=Fully_Registered
CSET register_slice_mode_wdch=Fully_Registered
CSET register_slice_mode_wrch=Fully_Registered
CSET reset_pin=true
CSET reset_type=Asynchronous_Reset
CSET ruser_width=1
CSET synchronization_stages=2
CSET synchronization_stages_axi=2
CSET tdata_width=64
CSET tdest_width=4
CSET tid_width=8
CSET tkeep_width=4
CSET tstrb_width=4
CSET tuser_width=4
CSET underflow_flag=false
CSET underflow_flag_axi=false
CSET underflow_sense=Active_High
CSET underflow_sense_axi=Active_High
CSET use_clock_enable=false
CSET use_dout_reset=true
CSET use_embedded_registers=false
CSET use_extra_logic=false
CSET valid_flag=false
CSET valid_sense=Active_High
CSET wach_type=FIFO
CSET wdch_type=FIFO
CSET wrch_type=FIFO
CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=1
CSET write_data_count=false
CSET write_data_count_width=4
CSET wuser_width=1
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-07-25T18:11:59Z
# END Extra information
GENERATE
# CRC: cfabdd53

426
coregen/wb_ddr_ctrl_wb_to_ddr.xco Executable file → Normal file
View File

@@ -1,213 +1,213 @@
##############################################################
#
# Xilinx Core Generator version 14.4
# Date: Tue Feb 26 21:38:19 2013
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:fifo_generator:9.3
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc3s700an
SET devicefamily = spartan3a
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -4
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3
# END Select
# BEGIN Parameters
CSET add_ngc_constraint_axi=false
CSET almost_empty_flag=false
CSET almost_full_flag=false
CSET aruser_width=1
CSET awuser_width=1
CSET axi_address_width=32
CSET axi_data_width=64
CSET axi_type=AXI4_Stream
CSET axis_type=FIFO
CSET buser_width=1
CSET clock_enable_type=Slave_Interface_Clock_Enable
CSET clock_type_axi=Common_Clock
CSET component_name=wb_ddr_ctrl_wb_to_ddr
CSET data_count=false
CSET data_count_width=4
CSET disable_timing_violations=false
CSET disable_timing_violations_axi=false
CSET dout_reset_value=0
CSET empty_threshold_assert_value=2
CSET empty_threshold_assert_value_axis=1022
CSET empty_threshold_assert_value_rach=1022
CSET empty_threshold_assert_value_rdch=1022
CSET empty_threshold_assert_value_wach=1022
CSET empty_threshold_assert_value_wdch=1022
CSET empty_threshold_assert_value_wrch=1022
CSET empty_threshold_negate_value=3
CSET enable_aruser=false
CSET enable_awuser=false
CSET enable_buser=false
CSET enable_common_overflow=false
CSET enable_common_underflow=false
CSET enable_data_counts_axis=false
CSET enable_data_counts_rach=false
CSET enable_data_counts_rdch=false
CSET enable_data_counts_wach=false
CSET enable_data_counts_wdch=false
CSET enable_data_counts_wrch=false
CSET enable_ecc=false
CSET enable_ecc_axis=false
CSET enable_ecc_rach=false
CSET enable_ecc_rdch=false
CSET enable_ecc_wach=false
CSET enable_ecc_wdch=false
CSET enable_ecc_wrch=false
CSET enable_read_channel=false
CSET enable_read_pointer_increment_by2=false
CSET enable_reset_synchronization=true
CSET enable_ruser=false
CSET enable_tdata=false
CSET enable_tdest=false
CSET enable_tid=false
CSET enable_tkeep=false
CSET enable_tlast=false
CSET enable_tready=true
CSET enable_tstrobe=false
CSET enable_tuser=false
CSET enable_write_channel=false
CSET enable_wuser=false
CSET fifo_application_type_axis=Data_FIFO
CSET fifo_application_type_rach=Data_FIFO
CSET fifo_application_type_rdch=Data_FIFO
CSET fifo_application_type_wach=Data_FIFO
CSET fifo_application_type_wdch=Data_FIFO
CSET fifo_application_type_wrch=Data_FIFO
CSET fifo_implementation=Independent_Clocks_Distributed_RAM
CSET fifo_implementation_axis=Common_Clock_Block_RAM
CSET fifo_implementation_rach=Common_Clock_Block_RAM
CSET fifo_implementation_rdch=Common_Clock_Block_RAM
CSET fifo_implementation_wach=Common_Clock_Block_RAM
CSET fifo_implementation_wdch=Common_Clock_Block_RAM
CSET fifo_implementation_wrch=Common_Clock_Block_RAM
CSET full_flags_reset_value=1
CSET full_threshold_assert_value=13
CSET full_threshold_assert_value_axis=1023
CSET full_threshold_assert_value_rach=1023
CSET full_threshold_assert_value_rdch=1023
CSET full_threshold_assert_value_wach=1023
CSET full_threshold_assert_value_wdch=1023
CSET full_threshold_assert_value_wrch=1023
CSET full_threshold_negate_value=12
CSET id_width=4
CSET inject_dbit_error=false
CSET inject_dbit_error_axis=false
CSET inject_dbit_error_rach=false
CSET inject_dbit_error_rdch=false
CSET inject_dbit_error_wach=false
CSET inject_dbit_error_wdch=false
CSET inject_dbit_error_wrch=false
CSET inject_sbit_error=false
CSET inject_sbit_error_axis=false
CSET inject_sbit_error_rach=false
CSET inject_sbit_error_rdch=false
CSET inject_sbit_error_wach=false
CSET inject_sbit_error_wdch=false
CSET inject_sbit_error_wrch=false
CSET input_data_width=61
CSET input_depth=16
CSET input_depth_axis=1024
CSET input_depth_rach=16
CSET input_depth_rdch=1024
CSET input_depth_wach=16
CSET input_depth_wdch=1024
CSET input_depth_wrch=16
CSET interface_type=Native
CSET output_data_width=61
CSET output_depth=16
CSET overflow_flag=false
CSET overflow_flag_axi=false
CSET overflow_sense=Active_High
CSET overflow_sense_axi=Active_High
CSET performance_options=Standard_FIFO
CSET programmable_empty_type=No_Programmable_Empty_Threshold
CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold
CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold
CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold
CSET programmable_full_type=No_Programmable_Full_Threshold
CSET programmable_full_type_axis=No_Programmable_Full_Threshold
CSET programmable_full_type_rach=No_Programmable_Full_Threshold
CSET programmable_full_type_rdch=No_Programmable_Full_Threshold
CSET programmable_full_type_wach=No_Programmable_Full_Threshold
CSET programmable_full_type_wdch=No_Programmable_Full_Threshold
CSET programmable_full_type_wrch=No_Programmable_Full_Threshold
CSET rach_type=FIFO
CSET rdch_type=FIFO
CSET read_clock_frequency=1
CSET read_data_count=false
CSET read_data_count_width=4
CSET register_slice_mode_axis=Fully_Registered
CSET register_slice_mode_rach=Fully_Registered
CSET register_slice_mode_rdch=Fully_Registered
CSET register_slice_mode_wach=Fully_Registered
CSET register_slice_mode_wdch=Fully_Registered
CSET register_slice_mode_wrch=Fully_Registered
CSET reset_pin=true
CSET reset_type=Asynchronous_Reset
CSET ruser_width=1
CSET synchronization_stages=2
CSET synchronization_stages_axi=2
CSET tdata_width=64
CSET tdest_width=4
CSET tid_width=8
CSET tkeep_width=4
CSET tstrb_width=4
CSET tuser_width=4
CSET underflow_flag=false
CSET underflow_flag_axi=false
CSET underflow_sense=Active_High
CSET underflow_sense_axi=Active_High
CSET use_clock_enable=false
CSET use_dout_reset=true
CSET use_embedded_registers=false
CSET use_extra_logic=false
CSET valid_flag=false
CSET valid_sense=Active_High
CSET wach_type=FIFO
CSET wdch_type=FIFO
CSET wrch_type=FIFO
CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=1
CSET write_data_count=false
CSET write_data_count_width=4
CSET wuser_width=1
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-11-19T12:39:56Z
# END Extra information
GENERATE
# CRC: 34700267
##############################################################
#
# Xilinx Core Generator version 14.3
# Date: Thu Feb 28 16:33:31 2013
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:fifo_generator:9.3
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc3s700an
SET devicefamily = spartan3a
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -4
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3
# END Select
# BEGIN Parameters
CSET add_ngc_constraint_axi=false
CSET almost_empty_flag=false
CSET almost_full_flag=false
CSET aruser_width=1
CSET awuser_width=1
CSET axi_address_width=32
CSET axi_data_width=64
CSET axi_type=AXI4_Stream
CSET axis_type=FIFO
CSET buser_width=1
CSET clock_enable_type=Slave_Interface_Clock_Enable
CSET clock_type_axi=Common_Clock
CSET component_name=wb_ddr_ctrl_wb_to_ddr
CSET data_count=false
CSET data_count_width=4
CSET disable_timing_violations=true
CSET disable_timing_violations_axi=false
CSET dout_reset_value=0
CSET empty_threshold_assert_value=2
CSET empty_threshold_assert_value_axis=1022
CSET empty_threshold_assert_value_rach=1022
CSET empty_threshold_assert_value_rdch=1022
CSET empty_threshold_assert_value_wach=1022
CSET empty_threshold_assert_value_wdch=1022
CSET empty_threshold_assert_value_wrch=1022
CSET empty_threshold_negate_value=3
CSET enable_aruser=false
CSET enable_awuser=false
CSET enable_buser=false
CSET enable_common_overflow=false
CSET enable_common_underflow=false
CSET enable_data_counts_axis=false
CSET enable_data_counts_rach=false
CSET enable_data_counts_rdch=false
CSET enable_data_counts_wach=false
CSET enable_data_counts_wdch=false
CSET enable_data_counts_wrch=false
CSET enable_ecc=false
CSET enable_ecc_axis=false
CSET enable_ecc_rach=false
CSET enable_ecc_rdch=false
CSET enable_ecc_wach=false
CSET enable_ecc_wdch=false
CSET enable_ecc_wrch=false
CSET enable_read_channel=false
CSET enable_read_pointer_increment_by2=false
CSET enable_reset_synchronization=true
CSET enable_ruser=false
CSET enable_tdata=false
CSET enable_tdest=false
CSET enable_tid=false
CSET enable_tkeep=false
CSET enable_tlast=false
CSET enable_tready=true
CSET enable_tstrobe=false
CSET enable_tuser=false
CSET enable_write_channel=false
CSET enable_wuser=false
CSET fifo_application_type_axis=Data_FIFO
CSET fifo_application_type_rach=Data_FIFO
CSET fifo_application_type_rdch=Data_FIFO
CSET fifo_application_type_wach=Data_FIFO
CSET fifo_application_type_wdch=Data_FIFO
CSET fifo_application_type_wrch=Data_FIFO
CSET fifo_implementation=Independent_Clocks_Distributed_RAM
CSET fifo_implementation_axis=Common_Clock_Block_RAM
CSET fifo_implementation_rach=Common_Clock_Block_RAM
CSET fifo_implementation_rdch=Common_Clock_Block_RAM
CSET fifo_implementation_wach=Common_Clock_Block_RAM
CSET fifo_implementation_wdch=Common_Clock_Block_RAM
CSET fifo_implementation_wrch=Common_Clock_Block_RAM
CSET full_flags_reset_value=1
CSET full_threshold_assert_value=13
CSET full_threshold_assert_value_axis=1023
CSET full_threshold_assert_value_rach=1023
CSET full_threshold_assert_value_rdch=1023
CSET full_threshold_assert_value_wach=1023
CSET full_threshold_assert_value_wdch=1023
CSET full_threshold_assert_value_wrch=1023
CSET full_threshold_negate_value=12
CSET id_width=4
CSET inject_dbit_error=false
CSET inject_dbit_error_axis=false
CSET inject_dbit_error_rach=false
CSET inject_dbit_error_rdch=false
CSET inject_dbit_error_wach=false
CSET inject_dbit_error_wdch=false
CSET inject_dbit_error_wrch=false
CSET inject_sbit_error=false
CSET inject_sbit_error_axis=false
CSET inject_sbit_error_rach=false
CSET inject_sbit_error_rdch=false
CSET inject_sbit_error_wach=false
CSET inject_sbit_error_wdch=false
CSET inject_sbit_error_wrch=false
CSET input_data_width=96
CSET input_depth=16
CSET input_depth_axis=1024
CSET input_depth_rach=16
CSET input_depth_rdch=1024
CSET input_depth_wach=16
CSET input_depth_wdch=1024
CSET input_depth_wrch=16
CSET interface_type=Native
CSET output_data_width=96
CSET output_depth=16
CSET overflow_flag=false
CSET overflow_flag_axi=false
CSET overflow_sense=Active_High
CSET overflow_sense_axi=Active_High
CSET performance_options=Standard_FIFO
CSET programmable_empty_type=No_Programmable_Empty_Threshold
CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold
CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold
CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold
CSET programmable_full_type=No_Programmable_Full_Threshold
CSET programmable_full_type_axis=No_Programmable_Full_Threshold
CSET programmable_full_type_rach=No_Programmable_Full_Threshold
CSET programmable_full_type_rdch=No_Programmable_Full_Threshold
CSET programmable_full_type_wach=No_Programmable_Full_Threshold
CSET programmable_full_type_wdch=No_Programmable_Full_Threshold
CSET programmable_full_type_wrch=No_Programmable_Full_Threshold
CSET rach_type=FIFO
CSET rdch_type=FIFO
CSET read_clock_frequency=1
CSET read_data_count=false
CSET read_data_count_width=4
CSET register_slice_mode_axis=Fully_Registered
CSET register_slice_mode_rach=Fully_Registered
CSET register_slice_mode_rdch=Fully_Registered
CSET register_slice_mode_wach=Fully_Registered
CSET register_slice_mode_wdch=Fully_Registered
CSET register_slice_mode_wrch=Fully_Registered
CSET reset_pin=true
CSET reset_type=Asynchronous_Reset
CSET ruser_width=1
CSET synchronization_stages=2
CSET synchronization_stages_axi=2
CSET tdata_width=64
CSET tdest_width=4
CSET tid_width=8
CSET tkeep_width=4
CSET tstrb_width=4
CSET tuser_width=4
CSET underflow_flag=false
CSET underflow_flag_axi=false
CSET underflow_sense=Active_High
CSET underflow_sense_axi=Active_High
CSET use_clock_enable=false
CSET use_dout_reset=true
CSET use_embedded_registers=false
CSET use_extra_logic=false
CSET valid_flag=false
CSET valid_sense=Active_High
CSET wach_type=FIFO
CSET wdch_type=FIFO
CSET wrch_type=FIFO
CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=1
CSET write_data_count=false
CSET write_data_count_width=4
CSET wuser_width=1
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-07-25T18:11:59Z
# END Extra information
GENERATE
# CRC: dad99623

48
src/wb_ddr_ctrl_wb.vhd
View File

@@ -73,10 +73,10 @@ component wb_ddr_ctrl_wb_from_ddr IS
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
@@ -86,10 +86,10 @@ component wb_ddr_ctrl_wb_to_ddr IS
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(60 DOWNTO 0);
din : IN STD_LOGIC_VECTOR(95 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(60 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
@@ -111,11 +111,11 @@ component wb_ddr_ctrl_wb_sc is
bte_i : in std_ulogic_vector(1 downto 0);
-- To/from ddr clock domain
ddr_din : out std_ulogic_vector(31 downto 0);
ddr_dout : in std_ulogic_vector(31 downto 0);
ddr_adr : out std_ulogic_vector(23 downto 0);
ddr_din : out std_ulogic_vector(63 downto 0);
ddr_dout : in std_ulogic_vector(63 downto 0);
ddr_adr : out std_ulogic_vector(22 downto 0);
ddr_we : out std_ulogic;
ddr_be : out std_ulogic_vector(3 downto 0);
ddr_be : out std_ulogic_vector(7 downto 0);
fifo_to_ddr_write : out std_ulogic;
fifo_from_ddr_read : out std_ulogic;
@@ -145,11 +145,11 @@ component wb_ddr_ctrl_wb_dc is
ctrl_ar_done : in std_logic;
-- To/from system clock domain
din : in std_ulogic_vector(31 downto 0);
dout : out std_ulogic_vector(31 downto 0);
adr : in std_ulogic_vector(23 downto 0);
din : in std_ulogic_vector(63 downto 0);
dout : out std_ulogic_vector(63 downto 0);
adr : in std_ulogic_vector(22 downto 0);
we : in std_ulogic;
be : in std_ulogic_vector(3 downto 0);
be : in std_ulogic_vector(7 downto 0);
fifo_to_sys_write : out std_ulogic;
fifo_from_sys_read : out std_ulogic;
@@ -163,10 +163,10 @@ signal s2d_fifo_rd, s2d_fifo_wr, d2s_fifo_rd, d2s_fifo_wr : std_ulogic;
signal s2d_fifo_empty, s2d_fifo_full, d2s_fifo_empty, d2s_fifo_full : std_ulogic;
-- FIFO data signals
signal s2d_fifo_din : std_ulogic_vector(60 downto 0);
signal d2s_fifo_din : std_ulogic_vector(31 downto 0);
signal s2d_fifo_dout : std_logic_vector(60 downto 0);
signal d2s_fifo_dout : std_logic_vector(31 downto 0);
signal s2d_fifo_din : std_ulogic_vector(95 downto 0);
signal d2s_fifo_din : std_ulogic_vector(63 downto 0);
signal s2d_fifo_dout : std_logic_vector(95 downto 0);
signal d2s_fifo_dout : std_logic_vector(63 downto 0);
signal ddr2_clk180 : std_ulogic;
@@ -191,11 +191,11 @@ system_cd_inst : wb_ddr_ctrl_wb_sc
bte_i => bte_i,
-- To/from ddr clock domain
ddr_din => s2d_fifo_din(31 downto 0),
ddr_din => s2d_fifo_din(63 downto 0),
ddr_dout => std_ulogic_vector(d2s_fifo_dout),
ddr_adr => s2d_fifo_din(55 downto 32),
ddr_we => s2d_fifo_din(56),
ddr_be => s2d_fifo_din(60 downto 57),
ddr_adr => s2d_fifo_din(86 downto 64),
ddr_we => s2d_fifo_din(87),
ddr_be => s2d_fifo_din(95 downto 88),
fifo_to_ddr_write => s2d_fifo_wr,
fifo_from_ddr_read => d2s_fifo_rd,
@@ -255,11 +255,11 @@ ddr_cd_inst : wb_ddr_ctrl_wb_dc
ctrl_ar_done => ctrl_ar_done,
-- To/from system clock domain
din => std_ulogic_vector(s2d_fifo_dout(31 downto 0)),
din => std_ulogic_vector(s2d_fifo_dout(63 downto 0)),
dout => d2s_fifo_din,
adr => std_ulogic_vector(s2d_fifo_dout(55 downto 32)),
we => s2d_fifo_dout(56),
be => std_ulogic_vector(s2d_fifo_dout(60 downto 57)),
adr => std_ulogic_vector(s2d_fifo_dout(86 downto 64)),
we => s2d_fifo_dout(87),
be => std_ulogic_vector(s2d_fifo_dout(95 downto 88)),
fifo_to_sys_write => d2s_fifo_wr,
fifo_from_sys_read => s2d_fifo_rd,

64
src/wb_ddr_ctrl_wb_dc.vhd
View File

@@ -53,11 +53,11 @@ entity wb_ddr_ctrl_wb_dc is
ctrl_ar_done : in std_logic;
-- To/from system clock domain
din : in std_ulogic_vector(31 downto 0);
dout : out std_ulogic_vector(31 downto 0);
adr : in std_ulogic_vector(23 downto 0);
din : in std_ulogic_vector(63 downto 0);
dout : out std_ulogic_vector(63 downto 0);
adr : in std_ulogic_vector(22 downto 0);
we : in std_ulogic;
be : in std_ulogic_vector(3 downto 0);
be : in std_ulogic_vector(7 downto 0);
fifo_to_sys_write : out std_ulogic;
fifo_from_sys_read : out std_ulogic;
@@ -83,18 +83,20 @@ architecture Behavioral of wb_ddr_ctrl_wb_dc is
row_addr : in std_ulogic_vector(12 downto 0);
ddr_address_en : out std_ulogic;
ddr_dout_en : out std_ulogic;
ddr_dout_high : out std_ulogic;
ddr_dmask_rst : out std_ulogic;
ddr_dmask_en : out std_ulogic;
dout_low_en : out std_ulogic;
ctrl_command_register_d : out std_logic_vector(2 downto 0);
ctrl_burst_done_d : out std_ulogic;
fifo_from_sys_read : out std_ulogic);
end component;
signal ddr_address : std_ulogic_vector(23 downto 0) := (others => '-');
signal ddr_address : std_ulogic_vector(22 downto 0) := (others => '-');
signal ddr_address_en : std_ulogic := '0';
signal ddr_dout : std_ulogic_vector(31 downto 0) := (others => '-');
signal ddr_dout_en : std_ulogic := '0';
signal ddr_dout_en, ddr_dout_high : std_ulogic := '0';
signal ddr_dmask : std_ulogic_vector(3 downto 0) := (others => '0');
signal ddr_dmask_rst, ddr_dmask_en : std_ulogic := '0';
@@ -102,6 +104,10 @@ signal ddr_dmask_rst, ddr_dmask_en : std_ulogic := '0';
signal ctrl_command_register_d : std_logic_vector(2 downto 0) := "000";
signal ctrl_burst_done_d : std_ulogic := '0';
signal dout_low : std_ulogic_vector(31 downto 0) := (others => '-');
signal dout_low_en : std_ulogic := '0';
signal ctrl_data_valid_toggle : std_ulogic := '0';
begin
wb_ddr_ctrl_wb_dc_fsm_inst: wb_ddr_ctrl_wb_dc_fsm
@@ -116,11 +122,13 @@ wb_ddr_ctrl_wb_dc_fsm_inst: wb_ddr_ctrl_wb_dc_fsm
ctrl_ar_done => ctrl_ar_done,
fifo_from_sys_empty => fifo_from_sys_empty,
we => we,
row_addr => adr(21 downto 9),
row_addr => adr(20 downto 8),
ddr_address_en => ddr_address_en,
ddr_dout_en => ddr_dout_en,
ddr_dout_high => ddr_dout_high,
ddr_dmask_rst => ddr_dmask_rst,
ddr_dmask_en => ddr_dmask_en,
--dout_low_en => dout_low_en,
ctrl_command_register_d => ctrl_command_register_d,
ctrl_burst_done_d => ctrl_burst_done_d,
fifo_from_sys_read => fifo_from_sys_read
@@ -137,14 +145,18 @@ ddr_address_reg : process(ddr2_clk180)
end process ddr_address_reg;
-- remap address for ddr controller (so column is lowest)
ctrl_input_address <= std_logic_vector(ddr_address(21 downto 9) & ddr_address(8 downto 0) & '0' & ddr_address(23 downto 22));
ctrl_input_address <= std_logic_vector(ddr_address(20 downto 8) & ddr_address(7 downto 0) & "00" & ddr_address(22 downto 21));
-- ddr_dout register
ddr_dout_reg : process(ddr2_clk180)
begin
if rising_edge(ddr2_clk180) then
if ddr_dout_en = '1' then
ddr_dout <= din;
if ddr_dout_high = '1' then
ddr_dout <= din(63 downto 32);
else
ddr_dout <= din(31 downto 0);
end if;
end if;
end if;
end process ddr_dout_reg;
@@ -154,9 +166,13 @@ ddr_dmask_reg : process(ddr2_clk180)
begin
if rising_edge(ddr2_clk180) then
if ddr_dmask_rst = '1' or ddr2_reset = '1' then
ddr_dmask <= (others => '0');
ddr_dmask <= (others => '1');
elsif ddr_dmask_en = '1' then
ddr_dmask <= be;
if ddr_dout_high = '1' then
ddr_dmask <= be(7 downto 4);
else
ddr_dmask <= be(3 downto 0);
end if;
end if;
end if;
end process ddr_dmask_reg;
@@ -185,9 +201,31 @@ ctrl_burst_done_reg : process(ddr2_clk180)
ctrl_burst_done <= ctrl_burst_done_d;
end if;
end process ctrl_burst_done_reg;
-- ctrl_data_valid tff
ctrl_data_valid_tff : process(ddr2_clk90)
begin
if rising_edge(ddr2_clk90) then
if ctrl_data_valid = '1' then
ctrl_data_valid_toggle <= not ctrl_data_valid_toggle;
end if;
end if;
end process ctrl_data_valid_tff;
dout_low_en <= ctrl_data_valid and not ctrl_data_valid_toggle;
-- dout_low register
dout_low_reg : process(ddr2_clk90)
begin
if rising_edge(ddr2_clk90) then
if dout_low_en = '1' then
dout_low <= std_ulogic_vector(ctrl_output_data);
end if;
end if;
end process dout_low_reg;
-- move data from ddr to fifo
dout <= std_ulogic_vector(ctrl_output_data);
fifo_to_sys_write <= ctrl_data_valid;
dout <= std_ulogic_vector(ctrl_output_data) & dout_low;
fifo_to_sys_write <= ctrl_data_valid and ctrl_data_valid_toggle;
end Behavioral;

63
src/wb_ddr_ctrl_wb_dc_fsm.vhd
View File

@@ -51,8 +51,10 @@ entity wb_ddr_ctrl_wb_dc_fsm is
-- Outputs
ddr_address_en : out std_ulogic;
ddr_dout_en : out std_ulogic;
ddr_dout_high : out std_ulogic;
ddr_dmask_rst : out std_ulogic;
ddr_dmask_en : out std_ulogic;
dout_low_en : out std_ulogic;
ctrl_command_register_d : out std_logic_vector(2 downto 0);
ctrl_burst_done_d : out std_ulogic;
fifo_from_sys_read : out std_ulogic
@@ -80,28 +82,18 @@ signal fifo_from_sys_read_int, fifo_from_sys_valid : std_ulogic := '0';
begin
-- input FIFO control
fifo_from_sys_read_int <= '1' when ((ctrl_state = S_IDLE and ctrl_auto_ref_req = '0' and fifo_pending = '0') or
(ctrl_state = S_REQUEST_INIT and we = '1') or
(ctrl_state = S_WRITE1 and ctrl_cmd_ack = '1') or
(ctrl_state = S_WRITE2 and not (fifo_from_sys_valid = '0' or row_addr /= burst_start_adr or
we = '0' or ctrl_auto_ref_req = '1')) or
(ctrl_state = S_WRITE4) or
(ctrl_state = S_READ3 or ctrl_state = S_READ5) or
(ctrl_state = S_READ4 and not (fifo_from_sys_valid = '0' or row_addr /= burst_start_adr or
we = '1' or ctrl_auto_ref_req = '1')) or
(ctrl_state = S_READ2)
) and fifo_from_sys_empty = '0' else
'0';
is_fifo_from_sys_valid : process(ddr2_clk0)
begin
if rising_edge(ddr2_clk0) then
fifo_from_sys_valid <= fifo_from_sys_read_int;
if fifo_from_sys_read_int = '1' then
fifo_from_sys_valid <= not fifo_from_sys_empty;
end if;
end if;
end process is_fifo_from_sys_valid;
fifo_from_sys_read <= fifo_from_sys_read_int;
fifo_from_sys_read <= fifo_from_sys_read_int and not fifo_from_sys_empty;
ctrl_fsm_state : process(ddr2_clk180)
begin
@@ -192,25 +184,48 @@ ctrl_fsm_state : process(ddr2_clk180)
end if;
end if;
end process ctrl_fsm_state;
-- input FIFO control
--fifo_from_sys_read_int <= '1' when ((ctrl_state = S_IDLE and ctrl_auto_ref_req = '0' and fifo_pending = '0') or
-- (ctrl_state = S_REQUEST_INIT and we = '1') or
-- (ctrl_state = S_WRITE1 and ctrl_cmd_ack = '1') or
-- (ctrl_state = S_WRITE2 and not (fifo_from_sys_valid = '0' or row_addr /= burst_start_adr or
-- we = '0' or ctrl_auto_ref_req = '1')) or
-- (ctrl_state = S_WRITE4) or
-- (ctrl_state = S_READ3 or ctrl_state = S_READ5) or
-- (ctrl_state = S_READ4 and not (fifo_from_sys_valid = '0' or row_addr /= burst_start_adr or
-- we = '1' or ctrl_auto_ref_req = '1')) or
-- (ctrl_state = S_READ2)
-- ) else
-- '0';
ctrl_fsm_out : process(ctrl_state, ddr2_reset, we, ctrl_cmd_ack, fifo_from_sys_valid,
row_addr, burst_start_adr, ctrl_auto_ref_req)
begin
ddr_dmask_rst <= '0';
ddr_dmask_en <= '0';
ddr_dout_en <= '0';
ddr_address_en <= '0';
ddr_dmask_rst <= '0'; -- dmask register reset
ddr_dmask_en <= '0'; -- dmask register enable
ddr_dout_en <= '0'; -- output register enable
ddr_dout_high <= '-'; -- output register low/high mux
ddr_address_en <= '0'; -- address register enable
dout_low_en <= '0'; -- input data lower half register enable
ctrl_burst_done_d <= '0';
ctrl_command_register_d <= ctrl_command_nop;
fifo_from_sys_read_int <= '0';
case ctrl_state is
when S_INITIALIZE =>
ctrl_command_register_d <= ctrl_command_initialize;
when S_IDLE =>
if ctrl_auto_ref_req = '0' and fifo_pending = '0' then
fifo_from_sys_read_int <= '1';
end if;
when S_REQUEST_INIT =>
if we = '1' then
ddr_dmask_en <= '1';
ddr_dout_en <= '1';
ddr_dout_high <= '0';
ctrl_command_register_d <= ctrl_command_write;
--fifo_from_sys_read_int <= '1';
else
ctrl_command_register_d <= ctrl_command_read;
end if;
@@ -220,6 +235,8 @@ ctrl_fsm_out : process(ctrl_state, ddr2_reset, we, ctrl_cmd_ack, fifo_from_sys_v
if ctrl_cmd_ack = '1' then
ddr_dmask_en <= '1';
ddr_dout_en <= '1';
ddr_dout_high <= '1';
fifo_from_sys_read_int <= '1';
end if;
ctrl_command_register_d <= ctrl_command_write;
when S_WRITE2 =>
@@ -230,15 +247,19 @@ ctrl_fsm_out : process(ctrl_state, ddr2_reset, we, ctrl_cmd_ack, fifo_from_sys_v
else
ddr_dmask_en <= '1';
ddr_dout_en <= '1';
ddr_dout_high <= '0';
--fifo_from_sys_read_int <= '1';
end if;
ctrl_command_register_d <= ctrl_command_write;
when S_WRITE3 =>
ddr_dmask_en <= '1';
ddr_dout_en <= '1';
ddr_dout_high <= '1';
ddr_address_en <= '1';
ctrl_command_register_d <= ctrl_command_write;
when S_WRITE4 =>
ctrl_command_register_d <= ctrl_command_write;
fifo_from_sys_read_int <= '1';
when S_WRITE_END1 =>
ctrl_burst_done_d <= '1';
@@ -246,8 +267,10 @@ ctrl_fsm_out : process(ctrl_state, ddr2_reset, we, ctrl_cmd_ack, fifo_from_sys_v
ctrl_command_register_d <= ctrl_command_read;
when S_READ2 =>
ctrl_command_register_d <= ctrl_command_read;
--fifo_from_sys_read_int <= '1';
when S_READ3 =>
ctrl_command_register_d <= ctrl_command_read;
fifo_from_sys_read_int <= '1';
when S_READ4 =>
if fifo_from_sys_valid = '0' or row_addr /= burst_start_adr or
we = '1' or ctrl_auto_ref_req = '1' then
@@ -255,9 +278,11 @@ ctrl_fsm_out : process(ctrl_state, ddr2_reset, we, ctrl_cmd_ack, fifo_from_sys_v
ctrl_burst_done_d <= '1';
else
ddr_address_en <= '1';
--fifo_from_sys_read_int <= '1';
end if;
when S_READ5 =>
ctrl_command_register_d <= ctrl_command_read;
fifo_from_sys_read_int <= '1';
when S_READ_END1 =>
ctrl_burst_done_d <= '1';

157
src/wb_ddr_ctrl_wb_sc.vhd
View File

@@ -48,11 +48,11 @@ entity wb_ddr_ctrl_wb_sc is
bte_i : in std_ulogic_vector(1 downto 0);
-- To/from ddr clock domain
ddr_din : out std_ulogic_vector(31 downto 0);
ddr_dout : in std_ulogic_vector(31 downto 0);
ddr_adr : out std_ulogic_vector(23 downto 0);
ddr_din : out std_ulogic_vector(63 downto 0);
ddr_dout : in std_ulogic_vector(63 downto 0);
ddr_adr : out std_ulogic_vector(22 downto 0);
ddr_we : out std_ulogic;
ddr_be : out std_ulogic_vector(3 downto 0);
ddr_be : out std_ulogic_vector(7 downto 0);
fifo_to_ddr_write : out std_ulogic;
fifo_from_ddr_read : out std_ulogic;
@@ -62,14 +62,18 @@ entity wb_ddr_ctrl_wb_sc is
end wb_ddr_ctrl_wb_sc;
architecture Behavioral of wb_ddr_ctrl_wb_sc is
type states is (S_IDLE, S_WRITE_CLASSIC1, S_READ_CLASSIC1, S_READ_CLASSIC2);
type states is (S_IDLE,
S_WRITE_CLASSIC1,
S_WRITE_BURST1, S_WRITE_BURST2, S_WRITE_BURST_WAIT1,
S_WRITE_BURST_WAIT2,
S_READ_CLASSIC1, S_READ_CLASSIC2, S_READ_CLASSIC3);
signal state : states := S_IDLE;
signal fifo_from_ddr_read_int, fifo_from_ddr_valid : std_ulogic;
begin
fifo_from_ddr_read_int <= '1' when (((state = S_READ_CLASSIC1 and fifo_to_ddr_full = '0') or
(state = S_READ_CLASSIC2)
fifo_from_ddr_read_int <= '1' when ((--(state = S_READ_CLASSIC1 and fifo_to_ddr_full = '0') or
(state = S_READ_CLASSIC1)
) and fifo_from_ddr_empty = '0') or rst_i = '1' else
'0';
@@ -94,34 +98,62 @@ wb_slave : process(clk_i)
ack_o <= '0';
state <= S_IDLE;
else
ddr_din <= (others => '-');
ddr_adr <= (others => '-');
--ddr_din <= (others => '-');
--ddr_adr <= (others => '-');
ddr_we <= '-';
ddr_be <= (others => '-');
--ddr_be <= (others => '-');
fifo_to_ddr_write <= '0';
ack_o <= '0';
case state is
when S_IDLE =>
if stb_i = '1' then
if we_i = '1' then
if cti_i = "010" then -- incrementing burst
null;
else -- classic cycle or unsupported
if fifo_to_ddr_full = '0' then
ddr_din <= dat_i;
ddr_adr <= adr_i;
ddr_we <= '1';
ddr_be <= not sel_i;
fifo_to_ddr_write <= '1';
state <= S_WRITE_CLASSIC1;
if cti_i = "010" and bte_i = "00" then -- incrementing
-- linear burst
if fifo_to_ddr_full = '0' then
ack_o <= '1';
if adr_i(2) = '0' then -- aligned start
ddr_adr <= (others => '-');
ddr_din(63 downto 32) <= (others => '-');
ddr_din(31 downto 0) <= dat_i;
ddr_be(7 downto 4) <= (others => '-');
ddr_be(3 downto 0) <= not sel_i;
state <= S_WRITE_BURST1;
else -- unaligned start
ddr_adr <= adr_i(25 downto 3);
ddr_din(31 downto 0) <= (others => '-');
ddr_din(63 downto 32) <= dat_i;
ddr_be <= not sel_i & "1111";
ddr_we <= '1';
fifo_to_ddr_write <= '1';
state <= S_WRITE_BURST2;
end if;
end if;
else -- classic cycle or unsupported
if fifo_to_ddr_full = '0' then
if adr_i(2) = '0' then
ddr_din(31 downto 0) <= dat_i;
ddr_din(63 downto 32) <= (others => '-');
ddr_be <= "1111" & not sel_i;
else
ddr_din(31 downto 0) <= (others => '-');
ddr_din(63 downto 32) <= dat_i;
ddr_be <= not sel_i & "1111";
end if;
ddr_adr <= adr_i(25 downto 3);
ddr_we <= '1';
fifo_to_ddr_write <= '1';
ack_o <= '1';
state <= S_WRITE_CLASSIC1;
end if;
end if;
else
if cti_i = "010" then -- incrementing burst
null;
else -- classic cycle or unsupported
if fifo_to_ddr_full = '0' then
ddr_adr <= adr_i;
ddr_adr <= adr_i(25 downto 3);
ddr_we <= '0';
fifo_to_ddr_write <= '1';
state <= S_READ_CLASSIC1;
@@ -131,29 +163,84 @@ wb_slave : process(clk_i)
end if;
when S_WRITE_CLASSIC1 =>
if fifo_to_ddr_full = '0' then
ddr_din <= (others => '-');
ddr_adr <= std_ulogic_vector(unsigned(adr_i) + 1);
ddr_adr <= (others => '-');
state <= S_IDLE;
when S_WRITE_BURST1 => -- high dword, commit
ddr_din(63 downto 32) <= dat_i;
ddr_be(7 downto 0) <= not sel_i;
ddr_adr <= adr_i(25 downto 3);
if fifo_to_ddr_full = '0' then
ddr_we <= '1';
ddr_be <= (others => '1');
fifo_to_ddr_write <= '1';
ack_o <= '1';
state <= S_IDLE;
end if;
when S_READ_CLASSIC1 =>
if cti_i = "111" then -- EOB, aligned end
state <= S_IDLE;
ack_o <= '0';
else
state <= S_WRITE_BURST2;
ack_o <= '1';
end if;
else -- FIFO full
state <= S_WRITE_BURST_WAIT1;
ack_o <= '0';
end if;
when S_WRITE_BURST2 => -- low dword
ddr_adr <= (others => '-');
ddr_din(63 downto 32) <= (others => '-');
ddr_din(31 downto 0) <= dat_i;
ddr_be(7 downto 4) <= (others => '-');
ddr_be(3 downto 0) <= not sel_i;
if cti_i = "111" then -- EOB, unaligned end
ddr_be(7 downto 4) <= (others => '1');
ddr_adr <= adr_i(25 downto 3);
if fifo_to_ddr_full = '1' then
ddr_we <= '1';
fifo_to_ddr_write <= '1';
state <= S_IDLE;
else
state <= S_WRITE_BURST_WAIT2;
end if;
ack_o <= '0';
else
state <= S_WRITE_BURST1;
ack_o <= '1';
end if;
when S_WRITE_BURST_WAIT1 =>
if fifo_to_ddr_full = '0' then
ddr_adr <= std_ulogic_vector(unsigned(adr_i) + 1);
ddr_we <= '0';
ddr_we <= '1';
fifo_to_ddr_write <= '1';
if cti_i = "111" then
state <= S_IDLE;
ack_o <= '0';
else
state <= S_WRITE_BURST2;
ack_o <= '1';
end if;
end if;
when S_WRITE_BURST_WAIT2 =>
ddr_we <= '1';
fifo_to_ddr_write <= '1';
state <= S_IDLE;
when S_READ_CLASSIC1 =>
ddr_adr <= (others => '-');
if fifo_from_ddr_valid = '1' then
state <= S_READ_CLASSIC2;
end if;
when S_READ_CLASSIC2 =>
if fifo_from_ddr_valid = '1' then
dat_o <= ddr_dout;
ack_o <= '1';
state <= S_IDLE;
ddr_adr <= (others => '-');
if adr_i(2) = '0' then
dat_o <= ddr_dout(31 downto 0);
else
dat_o <= ddr_dout(63 downto 32);
end if;
ack_o <= '1';
state <= S_READ_CLASSIC3;
when S_READ_CLASSIC3 =>
ddr_adr <= (others => '-');
state <= S_IDLE;
end case;
end if;
end if;

47
tb/wb_ddr_ctrl_tb.vhd
View File

@@ -6,7 +6,7 @@
-- Author : Matthias Blankertz <matthias@blankertz.org>
-- Company :
-- Created : 2013-02-26
-- Last update: 2013-02-27
-- Last update: 2013-02-28
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
@@ -216,8 +216,51 @@ begin -- testbench
wait until rising_edge(clk_i);
end loop;
stb_i <= '0' after 2 ns;
assert dat_o = x"deadbeef" report "Read failed: unexpected data" severity failure;
assert dat_o = x"deadbeef" report "Read failed: unexpected data" severity warning;
wait until rising_edge(clk_i);
-- simple write cycle
wait until rising_edge(clk_i);
stb_i <= '1' after 2 ns;
we_i <= '1' after 2 ns;
sel_i <= "1111" after 2 ns;
adr_i <= x"000011" after 2 ns;
dat_i <= x"12345678" after 2 ns;
wait until rising_edge(clk_i);
while ack_o = '0' loop
wait until rising_edge(clk_i);
end loop;
stb_i <= '0' after 2 ns;
wait until rising_edge(clk_i);
-- simple read cycle
wait until rising_edge(clk_i);
stb_i <= '1' after 2 ns;
we_i <= '0' after 2 ns;
adr_i <= x"000010" after 2 ns;
wait until rising_edge(clk_i);
while ack_o = '0' loop
wait until rising_edge(clk_i);
end loop;
stb_i <= '0' after 2 ns;
assert dat_o = x"deadbeef" report "Read failed: unexpected data" severity warning;
wait until rising_edge(clk_i);
-- simple read cycle
wait until rising_edge(clk_i);
stb_i <= '1' after 2 ns;
we_i <= '0' after 2 ns;
adr_i <= x"000011" after 2 ns;
wait until rising_edge(clk_i);
while ack_o = '0' loop
wait until rising_edge(clk_i);
end loop;
stb_i <= '0' after 2 ns;
assert dat_o = x"1234567" report "Read failed: unexpected data" severity warning;
wait until rising_edge(clk_i);
assert false report "Test complete" severity failure;
wait;
end process WaveGen_Proc;