Matthias Blankertz 95aa43b2d5 - Debugging wb_ddr_ctrl ...

- Changed wb_ddr_ctrl_wb FIFO to 64 bit data width
- Added write burst support to wb_ddr_ctrl_wb_sc

2013-02-28 21:10:44 +01:00

constr

- Import project

2013-02-26 23:54:37 +01:00

coregen

- Debugging wb_ddr_ctrl

2013-02-28 21:10:44 +01:00

ddr2_sdram/vhdl_bl4/example_design

- Import project

2013-02-26 23:54:37 +01:00

src

- Debugging wb_ddr_ctrl

2013-02-28 21:10:44 +01:00

tb

- Debugging wb_ddr_ctrl

2013-02-28 21:10:44 +01:00

.gitignore

- Fixed DDR reset polarity

2013-02-27 12:13:26 +01:00

2d_display_engine.xst

- Import project

2013-02-26 23:54:37 +01:00

Default.wcfg

- Debugging wb_ddr_ctrl

2013-02-28 21:10:44 +01:00

Makefile

- Seperated control and data path in wb_ddr_ctrl_wb_dc

2013-02-28 15:54:48 +01:00

planahead_postsynth.tcl

- Fixed DDR reset polarity

2013-02-27 12:13:26 +01:00

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372 KiB

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VHDL 69.1%

Verilog 10.1%

SystemVerilog 8%

Raku 7.9%

C++ 2.6%

Other 2.2%